JPH04256180A - System for verifying logic circuit - Google Patents

Abstract

PURPOSE:To permit execution with small medium resources to be possible and to shorten design time. CONSTITUTION:An instruction specification input means 1 inputs instruction specification description (a) which expresses an instruction specification executed in an object logic circuit and generates simulation model information (c) which is a simulation possible form. A function specification input means 2 inputs function specification description (b) which expresses the function of the object logic circuit and generates simulation model information (c) which is the simulation possible form. A simulation means 3 executes a simulation based on simulation model information (c) and generates simulation result information (d). A test diagnosis procedure generating means 4 generates test diagnosis procedure information (e) based on instruction specification description (a) and simulation result information (d).

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit verification method, and more particularly to a logic circuit verification method for verifying the hardware design of a large-scale logic circuit.

0002

[Background Art] Conventional logic circuit verification methods first verify the validity of instruction specifications expressing the specifications of instructions to be executed in the target logic circuit in order to clarify the hardware functions of the target logic circuit and evaluate the performance. Verify manually, then create a test diagnostic program from the instruction specifications to test and diagnose the target logic circuit, verify the validity of the test diagnostic program using simulation specific to the target logic circuit, and A functional specification expressing the functional configuration and operation of a target logic circuit materialized based on the instruction specification is created, and a logic simulator is used to verify the logical validity of the functional specification.

[0003] Related documents are shown below.

(1) “Fundamentals of VLSI CAD” (1
983) Author: Kenji Kani and 2 others Ohmsha, Chapter 1
Design flow and CAD ・Chapter 4 CAD of logic circuits (2) “Improving the reliability of computer systems” (1977
) Written by Hiroshi Inose, Information Processing Society of Japan, Chapter 7 Failure Diagnosis (3) "Logical Design of Computers" (1983) Translated by Shunji Okugawa and 1 other person Kyoritsu Publishing, Chapter 4 Design of Computers

[Problems to be Solved by the Invention] The conventional logic circuit verification method described above first expresses the specifications of instructions to be executed in the target logic circuit in order to clarify the hardware functions of the target logic circuit and evaluate the performance. The validity of the instruction specifications is verified manually, and then a test diagnostic program is created from the instruction specifications to test and diagnose the target logic circuit, and a simulator specific to the target logic circuit is used to verify the validity of the test diagnostic program. Furthermore, based on the instruction specifications, a functional specification expressing the functional configuration and operation of the target logic circuit is created, and a logic simulator is used to verify the logical validity of the functional specification. Therefore, there are disadvantages in that it takes a great deal of time to design and verify a large-scale logic circuit, and requires a large amount of media resources.

[0005]

[Means for Solving the Problems] The logic circuit verification method of the present invention inputs an instruction specification description expressing the instruction specifications to be executed in a target logic circuit, and creates simulation model information in a simulation-enabled format. an input means; a functional specification input means for inputting a functional specification description expressing a function of a target logic circuit to create simulation model information in a format that can be simulated; and a simulation means for inputting the simulation model information and performing a simulation. , test diagnosis procedure creation means for inputting the instruction specification description and simulation result information created by the simulation means to create test diagnosis procedure information.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention. The instruction specification input means 1 inputs an instruction specification description a that describes the specifications of an instruction to be executed in the target logic circuit, and converts it into simulation model information c in a format that can be input by the simulation means 3.

The functional specification input means 2 inputs a functional specification description b that describes the functional configuration and logical operation of the target logic circuit based on the instruction specification description a whose logical validity is guaranteed, and performs simulation. The means 3 converts it into simulation model information c in an inputtable format.

The simulation means 3 is capable of simulating the operation of the instruction specification executed in the target logic circuit by inputting the simulation model information c created by the instruction specification input means 1, and furthermore, the simulation means 3 can simulate the operation of the instruction specification executed in the target logic circuit by inputting the simulation model information c created by the instruction specification input means 1. By inputting the simulation model information c, the functional configuration and logical operation of the target logic circuit can be simulated, and furthermore, the test diagnosis procedure information e created by the test diagnosis procedure creation means 4 at the time of simulation.
By using this, testing and diagnosis of the target logic circuit can be performed at the time of hardware design.

The test diagnosis procedure creation means 4 uses the simulation model information c created by the instruction specification input means 1 based on the instruction specification description a whose logical validity is guaranteed, so that the simulation means 3 can calculate the operation of the instruction specification. Simulation result information d, which is the result of simulating the above, and instruction specification description a, whose logical validity is guaranteed, are input to create test diagnosis procedure information e for testing and diagnosing the target logic circuit.

First, a hardware designer of a large-scale logic circuit expresses the specifications of the instructions to be executed in the target logic circuit using an instruction specification description a, and further clarifies the hardware functions and performance of the target logic circuit. For evaluation, the instruction specification input means 1 is used to convert the instruction specification description a into simulation model information c in a format that can be input to the simulation means 3, and by inputting the simulation model information c, the target logic circuit is simulation means 3 capable of simulating the operation of instruction specifications executed by
The logical validity of instruction specification description a is verified using

Next, the hardware designer of the large-scale logic circuit creates simulation result information d by simulating the instruction operation according to the above procedure based on the instruction specification description a whose logical validity is guaranteed. , further uses the test diagnosis procedure creation means 4 to generate simulation result information d and instruction specification description a whose logical validity is guaranteed.
Test and diagnosis procedure information e for testing and diagnosing the target logic circuit is created.

[0013] Then, the hardware designer of the large-scale logic circuit uses the functional specification description b to design the functional configuration and logical operation of the target logic circuit based on the instruction specification description a whose logical validity is guaranteed. Further, the functional specification input means 2 is used to convert the functional specification description b into the simulation model information c, which is in a format that can be input by the simulation means 3, and the test diagnosis procedure information created by the test diagnosis procedure creation means 4 is further expressed. e and the simulation model information c created by the functional specification input means 2, the functional specification description b is made using the simulation means 3 which enables simulation of the functional configuration and logical operation of the target logic circuit in test procedures and diagnostic procedures. Verify logical validity.

FIG. 2 is a block diagram showing details of one embodiment of the invention. The instruction specification description 5 expresses the specifications of the instruction executed by the target logic circuit, and describes the post-instruction format and the method of expressing the instruction word. f1 is an image diagram of the post-instruction format, where the operation part OP of the instruction consists of 4 bits and the first address part R of the instruction consists of 6 bits.
It is expressed that it is composed of 1 and the second address part R2 of the instruction composed of 6 bits. f2 is an image diagram of the expression method after the command, "ADD" of "ADDΔA,B"
represents an addition instruction, which is a type of instruction operation part OP,
"A" represents the specific address of the first address part R1 of the instruction,
"B" represents the specific address of the second address part R2 of the instruction,
"," represents the separation between the first address part R1 and the second address part R2, and as a whole pair, "ADDΔA,B" means "Add the value of register A and the value of register B, and store the operation result in register A." It expresses the command "to do".

First, a hardware designer of a large-scale logic circuit expresses the specifications of the instructions to be executed in the target logic circuit using the instruction specification description 5, and further clarifies the hardware functions and performance of the target logic circuit. For evaluation, the instruction specification input means 6 is used to convert the instruction specification description 5 into simulation model information 7, and by inputting the simulation model information 7, a simulation means 8 is provided which makes it possible to simulate the operation of the instruction specification. This is used to confirm the logical operation of the instruction specification description 5, that is, to verify its logical validity.

Next, the hardware designer of the large-scale logic circuit simulates the instruction operation according to the above procedure based on the instruction specification description 5 whose logical validity is guaranteed, and creates simulation result information 9. Here, "INPUT-A=1, B=
2” is the register A as the simulation input pattern.
"RESULT-A=3" represents that register A is set to state value 1 and register B is set to state value 2, and "RESULT-A=3" represents that register A becomes state value 3 as a result of the simulation.

Next, the hardware designer of the large-scale logic circuit uses the test diagnosis procedure creation means 10 to generate test diagnosis procedure information 11 from the simulation result information 9 and the instruction specification description 5 whose logical validity is guaranteed. create. Here, the test diagnosis procedure information 11 expresses the test procedure and diagnosis procedure for testing and diagnosing the target logic circuit. g1 is
It represents the test environment setting, that is, the test data setting, which is the first step in the test procedure, and "A = 1, B = 2" means that register A is set to 1 and register B is set to 2. is expressed. g2 represents the test command execution, which is the second step in the test procedure, and is "ADDΔA,B".
represents that the instruction to be tested is an addition instruction and an addition operation between registers A and B is to be executed. g
3 represents the third stage of the test procedure, that is, comparing the result of the test command with the correct value, and "A=3?" indicates that the result of the test command is stored. It expresses that the value of register A is compared with the correct value 3. g4 and g5 represent the verification result display, which is the fourth step in the test procedure, and "OK!" in g4 indicates that the execution result of the test command and the correct value match, that is, the test target command was executed normally. Further, g5 "error" represents that the execution result of the test instruction and the correct value do not match, that is, the execution of the test target instruction was abnormal.

The functional specification description 12 expresses the functional configuration and logical operation of the target logic circuit that embodies the target logic circuit based on the instruction specification description 5. h1 expresses the configuration and logical operation of register A, h2 expresses the configuration and logical operation of register B, h3 expresses the configuration and logical operation of the adder, and i1, i2, i3, i4, and i5 respectively. It represents the connections of a logic circuit.

Finally, the hardware designer of the large-scale logic circuit uses the functional specification description 12 to describe the functional configuration and logical operation of the target logic circuit based on the instruction specification description 5 whose logical validity is guaranteed. The functional specification description 12 is further converted into simulation model information 7 using the functional specification input means 13, and the test diagnosis procedure information 11 created by the test diagnosis procedure creation means 10 and the test diagnosis procedure information 11 created by the functional specification input means 13 are expressed using Confirmation of the logical function and logical operation of the functional specification description 12, that is, logical validity, using a simulation means 8 that allows simulation of the functional configuration and logical operation in test procedures and diagnostic procedures by inputting the simulation model information 7. Verify.

[0020]

[Effects of the Invention] As explained above, the logic circuit verification method of the present invention enables verification of the logical validity of instruction specifications and verification of the logical validity of functional specifications using a single simulation means. Moreover, since the test diagnosis procedure, that is, the test diagnosis program, can be automatically generated from the instruction specifications, design verification of large-scale logic circuits can be executed with less media resources, and the design period can be significantly reduced. There is.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention.

FIG. 2 is a block diagram showing details of the logic circuit verification method shown in FIG. 1;

[Explanation of symbols]

1 Instruction specification input means 2 Functional specification input means 3 Simulation means 4 Test diagnosis procedure creation means

Claims (1)

[Claims] [Claim 1] Instruction specification input means for inputting an instruction specification description expressing instruction specifications to be executed in a target logic circuit and creating simulation model information in a format that can be simulated, and a function expressing a function of the target logic circuit. a functional specification input means for inputting a specification description and creating simulation model information in a format that can be simulated; a simulation means for inputting the simulation model information and performing a simulation; and a simulation created by the command specification description and the simulation means. and test diagnosis procedure creation means for inputting result information and creating test diagnosis procedure information.