JPH0411945B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary] In a sector mark compensation method for read data of a recording device recorded in units of sectors, when a sector mark is detected at a position less than or equal to the reference sector length, the start position of the sector is determined at that position. otherwise, a sector reference signal is generated at the reference sector length position. This results in
Even if a sector mark is not detected or overdetected, the sector mark can be properly compensated for and malfunctions can be prevented.

[Industrial application field]

The present invention provides a sector mark compensation method for compensating for undetected or overdetected sector marks that occur when reading from a recording device that is recorded in sectors on a recording medium and has a sector mark at the beginning of each sector;
In particular, the present invention relates to a sector mark compensation method suitable for high-density recording devices such as optical disks.

[Conventional technology]

In a high-density recording device such as an optical disk, when data is recorded on a recording medium, the data is recorded in units of sectors having a format as illustrated in FIG.

In FIG. 4, SM is a sector mark, which is provided at the beginning of a sector and indicates the starting position of the sector. ID is an identifier that indicates the location of the sector. FLAG is a flag that indicates the usage status of that sector. DATA
is a data field in which user data, control data, etc. are recorded. The gap is provided to absorb rotational fluctuations of the disk.
SYNC ₁ to _{SYNC 3} are synchronization counter marks that indicate the synchronization timing of the following fields. Among these, SM, SYNC ₁ , ID, and SYNC ₃ constitute a sector header and are preformatted during disk manufacturing.

When detecting the sector mark of each sector from the data read from an optical disk on which data is recorded in such a sector format, a counter is provided to count the sector length starting from the position of the sector mark. When the counter value reaches the sector length, a sector mark detection gate (SM detection gate) with a certain width is generated as shown in Figure 5b, and the signal extracted within this gate width is used as the sector mark signal. Detect (Figure 5c).

However, in high-density recording media such as optical disks, the sector mark at the beginning of each sector may not be detected due to medium defects or the like.

If a sector mark is not detected, the data in that block cannot be reproduced.

Therefore, in the past, when a sector mark was not detected, sector mark compensation was performed by generating a pseudo sector mark at the falling edge of the SM detection gate, as shown in Figure 5d. .

[Problem that the invention seeks to solve]

In the conventional sector mark compensation method, when a sector mark is not detected, a pseudo sector mark is generated at the rear end of the SM detection gate to compensate for the sector mark.

The SM detection gate is set wider than the width of the sector mark, as shown in FIG. 5b, in order to ensure that the sector mark can be detected even if there is rotational variation in the optical disk. Therefore, the pseudo sector mark generated at the falling edge of the SM detection gate is the fifth
As shown in Figure d, this occurs when the sector is far into the SYNC ₁ area. For this reason, there is a problem in that the margin for performing synchronization pull-in decreases, resulting in incomplete synchronization pull-in or, in some cases, failure in synchronization pull-in.

In addition, if over-detection of sector marks, that is, detection of multiple sector marks occurs due to defects in the manufacturing of the optical disk or defects in the circuit, data playback and sector mark detection operations are performed using multiple sector mark signals. There was a problem with malfunctions.

In the present invention, data is recorded on a recording medium in units of sectors,
This system effectively compensates for undetected or overdetected sector marks that occur when reading data from a recording device that has a sector mark at the beginning of each sector, and prevents malfunctions in data playback and sector mark detection operations. The purpose is to provide an improved sector mark detection method.

[Means for solving problems]

The solution taken by the present invention will be explained with reference to FIG. FIG. 1 is a block diagram showing the basic configuration of the present invention.

In FIG. 1, a sector mark detection circuit (SM detection circuit) 11 detects sector marks from data read out from a recording device (not shown).

Reference numeral 12 denotes a sector length counter, which generates a sector length signal indicating sector length information starting from the time of restoration.

13 is sector mark compensation means (SM compensation means)
receives the sector mark signal (SM signal) from the SM detection means 11 and the sector length signal from the sector length counter 12, and detects that the SM signal is at a position equal to or less than the reference sector length set corresponding to the regular sector length; When a sector mark is detected within a predetermined sector detection interval (SM detection interval), a sector reference signal Ss indicating the sector start position is generated at the position of the first detected SM signal, and the SM signal is set to the reference sector length. If it is not detected at the following times, the sector reference signal Ss is generated at the position of the reference sector length.

14 is a counter recovery means, and when the SM signal reaches a predetermined value,
When the SM signal is detected within the SM detection interval, the sector length counter 12 is reset by the first detected SM signal, and when it is not detected within this SM detection interval, the sector reference signal generated at the position of the reference sector length is used. The sector length counter 12 is reset by the signal Ss.

[Effect]

Currently, the sector length of the regular sector format is 1360 bytes, the standard sector length is 1360 bytes, which is the same as the regular sector length, and the SM detection interval is 1350 to 1370.
The operation of the present invention will be explained using a byte as an example.

The sector length counter 12 performs a counter operation,
The count value at each point in time is input as a sector length signal to the SM compensating means 13 and the counter restoring means 14.

The SM compensation means 13 receives the signal from the SM detection circuit 11.
When the SM signal and the sector length signal from the sector length counter 12 are received, and when the SM signal is less than or equal to the standard sector length of 1360 bytes, that is, when the SM signal is input, the count value of the sector length signal is less than or equal to 1360 bytes, and the specified value is When detected within the SM detection interval of 1350 to 1370 bytes, the first detected SM signal is output as a sector reference signal Ss indicating the start position of the sector.

When the SM signal is not detected when the sector length signal is less than or equal to the standard sector length, that is, when the SM signal is input when the count value of the sector length signal exceeds the standard sector length of 1360 bytes, or when the count value of the sector length signal is If the SM signal is not detected even after the standard sector length of 1360 bytes is exceeded, the position of the standard sector length,
That is, the sector reference signal Ss is generated at the position where the count value of the sector length signal reaches 1360 bytes.

On the other hand, when an SM signal is detected within the set SM detection interval of 1350 to 1370 bytes, the counter reset means 14 resets the sector length counter 12 with the first detected SM signal, and within this SM detection interval. If it is not detected, the sector length counter is returned to a predetermined reference value by the sector reference signal Ss generated at the position of the reference sector length.

By doing the above, the sector reference signal Ss indicating the sector start position is generated at the sector mark detection position or the position of the reference sector length (1360 bytes). In either case, the sector reference signal Ss is generated at a position that does not exceed 1360 bytes, which is the reference sector length corresponding to the regular sector length.
Of course, if the SM signal is detected correctly,
Even if the SM signal is dropped and not detected, the sector reference signal Ss can be generated at a time point corresponding to the original SM signal detection time point. Therefore, this sector reference signal will not enter the SYNC ₁ section adjacent to the SM section in the sector frame, and data reproduction operations including synchronization pull-in processing can be performed normally.

Also, if an SM signal is over-detected within the SM detection interval (1350 to 1360 bytes) that is earlier than the standard sector length, a sector reference signal is generated at the time of the first detected SM signal, and If the SM signal is over-detected at a later point in time, the sector reference signal will be generated at the reference sector length (1360 bytes).
It is possible to prevent interference with synchronization pull-in due to excessive signal detection.

Furthermore, the sector length counter 12 is reset at the time of detection of the first SM signal detected within the SM detection interval or at the time of the standard sector length, so of course if the SM signal is detected correctly, the SM signal may be dropped. Even if the SM signal is not detected, the sector length counter 12 can be returned to the position corresponding to the original SM signal detection position.

This also applies when an SM signal is over-detected within the SM detection interval, and the first SM signal detected within the SM detection interval causes the sector length counter 12 to
will be reinstated. Therefore, even if an SM signal is over-detected, the sector length counter can be restored at the correct SM signal detection position or at a position close to the reference sector length, so that the next sector's SM signal detection operation can be performed normally. It can be done.

〔Example〕

An embodiment of the present invention will be described with reference to FIGS. 2 and 3. FIG. 2 is a block diagram illustrating the configuration of an embodiment of the present invention, and FIG. 2 is an operation timing chart of the embodiment.

(A) Configuration of Embodiment In FIG. 2, the SM detection circuit 11, sector length counter 12, SM compensation means 13, and counter recovery means 14 are as described in FIG.

In the sector length counter 12, CL is a system clock input terminal, and LOAD is an input terminal for a load signal for restoring the counter.

In the SM compensation means 13, 131 is a front end comparator (FCMP) in which the sector length value of the front end of the SM detection interval is set, and the count value of the sector length signal input from the sector length counter 12 is the front end comparator (FCMP). When the sector length reaches the front end, a front end detection signal Df is generated. A reference comparator (SCMP) 132 is set with a reference sector length value, and generates a reference detection signal Ds when the sector length signal inputted from the sector length counter 12 reaches the reference sector length.

133 is an OR circuit, 134 is an AND circuit, 13
5 is a first sector gate. The first sector gate consists of a JK type flip-flop,
J terminal is set terminal, K terminal is reset terminal,
The Q terminal is an output terminal that generates a positive output when set, and CL is the system clock input terminal.

The OR circuit 133 is connected to the SM detection circuit 11 or
The OR output of FCMP 132 is added to AND circuit 134. The AND circuit 134 generates the sector reference signal Ss when the AND condition of the Q outputs of the OR circuit 133 and the first sector gate 135 is satisfied. This sector reference signal Ss is also applied to the K terminal of the first sector gate 135 to reset it.

The J terminal of the first sector gate 135
The front end detection signal Df of FCMP131 is added,
Set this to the set state.

In the counter recovery means 14, 141 is a rear end comparator (BCMP) in which a sector length value indicating the rear end of the SM detection interval is set, and the count value of the sector length signal input from the sector length counter 12 is set. When the sector length reaches the rear end of the SM detection interval, the rear end detection signal Db is generated. ).

142 is an AND circuit, 143 and 144 are OR
The circuit 145 is a second sector gate. Second
The sector gate 145 is the first sector gate 13
5, it is composed of a JK type flip-flop, and the contents of the symbols J, K, Q, and CL are also the same.

The AND circuit 142 outputs the Q outputs of the SM detection circuit 11 and the second sector gate 145.
Added to OR circuits 143 and 144. The OR circuit 143 is a combination of the AND circuit 142 and the BCMP 141.
The OR output is applied to the K terminal of the second sector gate 145 to reset it. OR circuit 143
generates a load signal in response to the AND outputs of the AND circuits 142 and 134, adds it to the LOAD terminal of the sector length counter 12, and returns it. The J terminal of the second sector gate 145 has
The front end detection signal Df of FCMP131 is added,
Set this to the set state.

Although the SM compensating means 13 of the embodiment shares some of the functions of the counter restoring means 14, for convenience of explanation, it will be explained separately as shown in the drawing.

(B) Operation of the embodiment The operation of the embodiment will be explained with reference to the operation timing chart in FIG.

In Figure 3, if the SM signal is detected between the front end of the SM detection interval and the reference sector length, if the SM signal is detected between the reference sector length and the rear end of the SM detection interval, then This is an operation timing chart when the signal is dropped and not detected within the SM detection section.

Hereinafter, the operation of the embodiment will be explained separately for each of these cases. In the following explanation, the regular sector length is 1360 bytes, and the standard sector length is 1360 bytes, which is the same as the regular sector length.
The SM detection section has 1350 bytes at the front end and 1350 bytes at the rear end.
Assume that the area is 1350 to 1370 bytes, which is 1370 bytes.

When the SM signal is detected between the front end of the SM detection interval and the reference sector length When the count value of the sector length signal output by the sector length counter 12 reaches 1350 bytes, which is the front end of the SM detection interval, the FCMP 131 detects the front end. A signal Df ₁ is generated (FIG. 3a).

This front end detection signal _Df1 is applied to each J terminal of the first sector gate 135 and the second sector gate 145, and when it falls, both gates are set in the set state (FIGS. 3d and 3e). The Q outputs of both gates 135 and 145 are applied to AND circuits 134 and 142, respectively.

When the SM detection circuit 11 detects an SM signal from read data from an optical disk (not shown), one of the SM signals is applied to an AND circuit 134 through an OR circuit 133 (FIG. 3f).

Since the AND condition of the Q output of the OR circuit 133 and the first sector gate 135 is satisfied, the AND circuit 134 generates a sector reference signal Ss and sends it to a controller (not shown) (FIG. 3g).

The sector reference signal Ss is applied to the K terminal of the first sector gate 135, and the sector reference signal Ss is applied to the K terminal of the first sector gate 135.
The first sector gate 135 is reset at the falling edge of Ss (FIG. 3d, g). The negative Q output of the first sector gate 135 (assumed) is
It is added to the AND circuit 134 to block passage of subsequent SM signals.

By doing this, the detected SM
Since the sector reference signal Ss is correctly generated by the signal, data reproduction can be performed satisfactorily without interfering with the synchronization pull-in process.
Also, since only one sector reference signal Ss is generated by the first detected SM signal, even if the SM signal is over-detected,
The number of sector reference signals Ss generated is suppressed to one. Therefore, it is possible to prevent the controller from malfunctioning due to generation of a large number of reference signals Ss due to over-detection of the SM signal.

On the other hand, the other SM signal detected by the SM detection circuit 11 is applied to an OR circuit 144 through an AND circuit 142.

When the OR circuit 144 receives the SM signal, it generates a load signal and inputs the sector length counter 12.
LOAD terminal and return it to a predetermined reference value (for example, 0 value) (Fig. 3h). When the sector length counter 12 returns to the reference value,
The system clock starts counting again and outputs a sector length signal for detecting the SM signal of the next sector.

Moreover, the SM signal passing through the AND circuit 142 is
Furthermore, it is applied to the K terminal of the second sector gate 145 through the OR circuit 143, and the second sector gate 145 is reset at the fall of the SM signal (FIG. 3e, f). Second sector gate 14
The output of 5 is added to the AND circuit 142,
Blocks further SM signal passage.

By doing this, the detected SM
Since the sector length counter 12 is reset by the signal, the correct sector length signal starting from the detected SM signal is returned to the sector length counter 12.
It is possible to accurately detect the SM signal of the next sector.

Also, even if over-detection occurs in the SM signal,
The sector length counter 12 is reset by the first SM signal detected, and all other SM signals are blocked. If the count start point of the sector length counter 12 is delayed from the original SM signal detection time, the SM detection interval for SM signal detection of the next sector and the generation time of the reference sector length will be delayed, so the generation of the sector reference signal Ss. may be delayed and interfere with the synchronization pull-in process. However, in the present invention, the sector length counter 12 is
is restored, such a problem does not occur and the synchronization pull-in process is performed normally.

When an SM signal is detected between the reference sector length and the rear end of the SM detection interval When the count value of the sector length signal output by the sector length counter 12 reaches 1350 bytes, which is the front end of the SM detection interval, the FCMP 131 detects the front end. A detection signal Df is generated (Fig. 3a). This front end detection signal Df is the first sector gate 1
35 and the J terminal of the second sector gate 145, and when the voltage falls, both gates are set to the set state (FIGS. 3d and 3e). both gates 13
The Q outputs of 5 and 145 are connected to the AND circuit 134.
and 142, respectively. The above operation is the same as in the case described above.

Subsequently, when the counter value of the sector length signal output from the sector length counter 12 reaches the reference sector length of 1360 bytes, the SCMP 132 generates the reference detection signal Ds (FIG. 3b).

This reference detection signal Ds is applied to an AND circuit 134 through an OR circuit 133. AND
Since the AND condition of the Q output of the OR circuit 133 and the first sector gate 135 is satisfied, the circuit 134 generates a sector reference signal Ss and sends it to a controller (not shown) (FIG. 3g).

The sector reference signal Ss is applied to the K terminal of the first sector gate 135, and the sector reference signal Ss is applied to the K terminal of the first sector gate 135.
At the falling edge of Ss, the sector game 135 is reset (FIG. 3 d, g). The output of the first sector gate 135 is applied to an AND circuit 134 to block passage of subsequent SM signals.

The sector reference signal Ss is further applied to the LOAD terminal of the sector length counter 12 through an OR circuit 144 to restore it (FIG. 3h).

In this state, when the SM detection circuit 11 detects an SM signal from read data from an optical disk (not shown), the SM signal is sent to the AND circuit 14.
2 to the OR circuit 144 (AND circuit 134 is cut off). OR
When the circuit 144 receives the SM signal, it generates a load signal and inputs the sector length counter 12.
In addition to the LOAD terminal, this is also restored (Fig. 3 f, h).

By doing this, you can first
Sector length counter 1 once restored by Ss
2 is restored again by the SM signal, so a correct sector length signal starting from the detected SM signal is output from the sector length counter, making it possible to accurately detect the SM signal of the next sector.

On the other hand, the controller uses the sector reference signal Ss
Therefore, the synchronization pull-in process is not disturbed and the data reproduction process is performed satisfactorily.

The detected SM signal is sent to the AND circuit 142.
The signal is applied to the K terminal of the second sector gate 145 through the OR circuit 143, and the second sector gate 145 is reset at the falling edge of the SM signal (FIG. 3e, f). Second sector gate 14
The output of 5 is added to the AND circuit 142,
Blocks further SM signal passage. By doing this, even if an SM signal is over-detected, the above-mentioned operation will be performed with the SM signal detected first, and all other SM signals will be blocked, so that the count of the sector length counter 12 will continue. It is possible to prevent the starting point from being delayed from the original detection point of the SM signal.

Furthermore, even if over-detection occurs in the SM signal, the generation position of the sector reference signal Ss described above is not affected in any way, so it is possible to prevent malfunctions due to over-detection of the SM signal.

When the SM signal is dropped and is not detected within the SM detection area.

When the counter value of the sector length signal output from the sector length counter 12 reaches 1350 bytes, which is the front end of the SM detection section, the FCMP 131 generates the front end detection signal Df (FIG. 3a). This front end detection signal Df is the first sector gate 1
35 and the second sector gate 145 are set (FIG. 3d, e).

Subsequently, when the counter value of the sector length signal output from the sector length counter 12 reaches the reference sector length of 1360 bytes, the SCMP 132 generates the reference detection signal Ds (FIG. 3b). This reference detection signal Ds is applied to an AND circuit 134 to generate a sector reference signal Ss, which is sent to the controller (FIG. 3g).

This sector reference signal Ss resets the first sector gate 135, and its output is
It is added to the AND circuit 134 and blocks the passage of subsequent SM signals (Fig. 3 d, g). Furthermore, the sector reference signal Ss is applied to the LOAD terminal of the sector length counter 12 through the OR circuit 144 to restore it (FIG. 3h).

The above operation is the same as the operation in the case described above.

Now, assuming that the sector length counter 12 is reset to 0 value, if we count 10 bytes after the reset, we will add it to the previous standard sector length of 1360 bytes, which is the sector length at the end of the SM detection area.
It reaches 1370 bytes. Therefore, BCMP141
, 10 bytes, ie, the difference between the rear end and the reference sector length, is set as a sector length value indicating the rear end of the SM detection section.

When the count value of the sector length signal output by the sector length counter 12 after recovery reaches 10 bytes, the BCMP 141 generates the rear end detection signal Db of the SM detection section (FIG. 3c).

This trailing edge detection signal Db is applied to the K terminal of the second sector gate 145 through the OR circuit 143, and the second sector gate 145 is reset at the fall of the trailing edge detection signal Db (FIG. 3c, e).
The output of the second sector gate 145 is applied to the AND circuit 142 to block passage of subsequent SM signals.

By doing this, even if the SM signal is dropped in the input read data, the sector reference signal will be detected at the reference sector length of 1360 bytes.
Ss is generated, a controller (not shown) is activated, and the sector length counter 12 is restored, so that controller operations including synchronization pull-in processing, return operations of the sector length counter 12, and counter operations are performed normally. I can do it.

Although one embodiment of the present invention has been described above, each structure of the present invention is not limited to each structure of this embodiment. Furthermore, the sector format is not limited to that shown in FIG. 4.

〔Effect of the invention〕

As explained above, according to the present invention, the following effects can be obtained.

(b) Even if a sector mark is dropped during read data from a recording device, a sector reference signal is generated at the reference sector length position and data playback processing including synchronization pull-in and recovery of the sector length counter are performed. It can be done normally.

(b) If a sector mark is normally detected within the sector mark detection interval, the sector length counter is loaded with this sector mark regardless of the sector reference signal, so the correct sector length signal is generated from the sector length counter. I can do it.

(c) Even if a sector mark is over-detected, malfunction can be prevented and data reproduction processing including synchronization pull-in and recovery of the sector length counter can be performed normally.

[Brief explanation of drawings]

Fig. 1...Explanatory diagram of the basic configuration of the present invention, Fig. 2...Explanatory diagram of the configuration of an embodiment of the present invention, Fig. 3...
. . . An operational flowchart of the same embodiment; FIG. 4; an explanatory diagram of sector format; FIG. 5; an explanatory diagram of a conventional sector mark compensation system. 1 and 2, 11... Sector mark (SM) detection circuit, 12... Sector length counter, 13... Sector mark compensation means, 14... Counter recovery means.

Claims (1)

[Claims] 1. A sector mark that compensates for undetected or overdetected sector marks that occur when data is read from a recording device that is recorded in sectors on a recording medium and has a sector mark at the beginning of each sector. In the compensation method, (a) a sector mark detection circuit 11 that detects a sector mark from input data, and (b) a sector that generates a sector length signal that indicates sector length information starting from the time of restoration. (c) receiving the sector mark signal from the sector mark detection means 11 and the sector length signal from the sector length counter 12, and detecting that the sector mark signal is equal to or less than the reference sector length set corresponding to the regular sector length; When a sector mark is detected at the position of , and within a predetermined sector mark detection interval, a sector reference signal indicating the start position of the sector is generated at the position of the first detected sector mark signal, and the sector mark signal corresponds to the reference sector length. (d) When a sector mark signal is detected within a predetermined sector mark detection interval, the sector mark compensation means 13 generates a sector reference signal at the position of the reference sector length when the sector mark signal is not detected at the following position. The sector length counter 12 is activated by the sector mark signal detected in
and, when no sector mark signal is detected within the sector mark detection period, a counter return means 14 for returning the sector length counter 12 by a sector reference signal generated at the position of the reference sector length. A sector mark compensation method featuring: