JPH0412406B2 - - Google Patents
Info
- Publication number
- JPH0412406B2 JPH0412406B2 JP58187494A JP18749483A JPH0412406B2 JP H0412406 B2 JPH0412406 B2 JP H0412406B2 JP 58187494 A JP58187494 A JP 58187494A JP 18749483 A JP18749483 A JP 18749483A JP H0412406 B2 JPH0412406 B2 JP H0412406B2
- Authority
- JP
- Japan
- Prior art keywords
- pulse
- output
- ppr
- phase
- binary data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000000630 rising effect Effects 0.000 claims 1
- 229920005630 polypropylene random copolymer Polymers 0.000 description 13
- 238000007792 addition Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01P—MEASURING LINEAR OR ANGULAR SPEED, ACCELERATION, DECELERATION, OR SHOCK; INDICATING PRESENCE, ABSENCE, OR DIRECTION, OF MOVEMENT
- G01P13/00—Indicating or recording presence, absence, or direction, of movement
- G01P13/02—Indicating direction only, e.g. by weather vane
- G01P13/04—Indicating positive or negative direction of a linear movement or clockwise or anti-clockwise direction of a rotational movement
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Manipulation Of Pulses (AREA)
- Transmission And Conversion Of Sensor Element Output (AREA)
- Control Of Electric Motors In General (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は、パルスジエネレータの１回転あたり
の出力パルス数をそのスリツト数以下で任意に可
変できる出力パルス数可変装置に関するものであ
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output pulse number variable device that can arbitrarily vary the number of output pulses per revolution of a pulse generator within the number of slits.
従来サーボモータ等の回転数を検出するために
用いられるパルスジエネレータ（以下、PGと称
する）は、その１回転あたりの出力パルス数（以
下、PPRと称する）が固定されている。ところ
が、NC工作機等のサーボ系の回転数フイードバ
ツクに用いられるPGのPPRは、ボールネジのピ
ツチやギヤ比、又は、パルス処理部の逓倍比など
から決定されるのが実情である。
Conventionally, a pulse generator (hereinafter referred to as PG) used to detect the rotation speed of a servo motor or the like has a fixed number of output pulses per rotation (hereinafter referred to as PPR). However, the reality is that the PPR of a PG used for rotation speed feedback in a servo system such as an NC machine tool is determined from the pitch and gear ratio of a ball screw, or the multiplication ratio of a pulse processing section.
そのため、各種条件にあつたPGを提供するた
めに、前記PPRの異なる機種を多数備えておか
なければならないという欠点があつた。 Therefore, in order to provide PGs that meet various conditions, it is necessary to have a large number of different types of PPRs.
本発明は、上記欠点を解消し、PGから出力さ
れる２相パルスのPPRをそのPGのスリツト数以
下の範囲で任意に可変できる装置を提供すること
を目的とする。
SUMMARY OF THE INVENTION An object of the present invention is to eliminate the above drawbacks and provide a device that can arbitrarily vary the PPR of a two-phase pulse output from a PG within a range equal to or less than the number of slits in the PG.
以下、図面を参照して本発明の具体的実施例を
説明する。第１図は、本発明の具体的回路図であ
り、１はパルス処理回路部、２は積分回路部、３
は２相化回路部、４はPPR設定部である。ただ
し、ここでは、PGのスリツト数を1024（＝210）
として説明する。従来であれば、スリツト数イコ
ールPPRである。
Hereinafter, specific embodiments of the present invention will be described with reference to the drawings. FIG. 1 is a specific circuit diagram of the present invention, in which 1 is a pulse processing circuit section, 2 is an integration circuit section, and 3 is a specific circuit diagram of the present invention.
4 is a two-phase circuit section, and 4 is a PPR setting section. However, here, the number of slits in PG is 1024 (= 2 10 )
It will be explained as follows. Conventionally, the number of slits equals PPR.
さて、パルス処理回路部１は、EXOR１−ａ、
インバータ１−ｂ、FULL ADDER１−Ｃ、Ｄ
フリツプフロツプ１−ｄからなつており、PGの
２相パルス出力Ai，Biを２進数データΣ1，Σ0に
変換するものである。すなわち、図示した回路か
らわかるように、PGが正転時は（Σ1，Σ0）＝
（０、１）、逆転時は（Σ1，Σ0）＝（１、１）、停止
時は（Σ1，Σ0）＝（０、０）となるように構成さ
れている。 Now, the pulse processing circuit section 1 includes EXOR1-a,
Inverter 1-b, FULL ADDER1-C, D
It consists of flip-flops 1-d and converts the two-phase pulse outputs Ai and Bi of the PG into binary data Σ 1 and Σ 0 . In other words, as can be seen from the illustrated circuit, when the PG rotates in the normal direction, (Σ 1 , Σ 0 ) =
(0, 1), (Σ 1 , Σ 0 )=(1, 1) when reversing, and (Σ 1 , Σ 0 )=(0, 0) when stopped.
PPR設定部４は、10個のスイツチからなり、
1023（＝210−１）以下の数が自由に設定できる。 The PPR setting section 4 consists of 10 switches,
Any number below 1023 (=2 10 -1) can be set.
積分回路部２は、パルス処理回路部１の出力
Σ0のタイミングにしたがつて、Ｄフリツプフロ
ツプ２−ｄが保持する前回値に、PPR設定部４
で設定した値を加算又は減算する。Σ0とともに
出力されたΣ1が“０”のとき加算、“１”のとき
減算となる。 The integrating circuit section 2 sets the PPR setting section 4 to the previous value held by the D flip-flop 2-d in accordance with the timing of the output Σ 0 of the pulse processing circuit section 1.
Add or subtract the value set in . When Σ 1 output together with Σ 0 is "0", addition is performed, and when it is "1", subtraction is performed.
すなわち、Ｄフリツプフロツプの出力B1〜B10
がFULL ADDER２−Ｃに入力されるので、ア
キユムレータとして機能するのである。 That is, the outputs B 1 to B 10 of the D flip-flop
is input to FULL ADDER2-C, so it functions as an accumulator.
なお、B1〜B10の加減等によつて生ずる桁あふ
れ（オーバーフロー又はアンダーフロー）は、
Bx-1，Bxに現われる。 In addition, overflow (overflow or underflow) caused by adjustment of B 1 to B 10 , etc.
Appears in B x-1 , B x .
２相化回路部３は、２進数データBx-1，Bxを
２相出力に変換する。 The two-phase circuit section 3 converts the binary data B x-1 and B x into two-phase output.
さて、ここで、要求出力PPRを500とし、すな
わち500＝1F4（Ｈ）＝111110100（２）をPPR設定
部４に設定し、Ｄフリツプフロツプ２−ｄの初期
状態を仮りに、B10（Ｈ）として動作させた場合
を第２図に示す。
Now, here, the required output PPR is set to 500, that is, 500=1F4(H)=111110100(2) is set in the PPR setting section 4, and the initial state of the D flip-flop 2-d is temporarily set as B10(H). Figure 2 shows a case in which it is operated.
すなわち初期状態B10（Ｈ）の最上位２桁Bx
Bx-1は“１”、“０”でありA0，B0は、“１”、
“１”となる。 In other words, the most significant two digits B x of the initial state B10 (H)
B x-1 is “1”, “0”, and A 0 , B 0 are “1”,
It becomes “1”.
次にPPR設定部４で設定された1F4（Ｈ）を加
算すると、Bx，Bx-1は“１”、“１”となりA0，
B0は“０”、“１”となる。 Next, when 1F4 (H) set in the PPR setting section 4 is added, B x and B x-1 become “1” and “1”, and A 0 ,
B 0 becomes “0” and “1”.
このようにして、くり返し加算したものをタイ
ムチヤートに示している。 In this way, the repeated additions are shown on the time chart.
PPR＝1024の２相パルスAi，Biから変換され
た２相パルスA0，B0はPPR500となつていること
がわかる。 It can be seen that the two-phase pulses A 0 and B 0 converted from the two-phase pulses Ai and Bi of PPR=1024 have a PPR of 500.
つまり積分回路への入力比が500／210であるの
で、オーバーフロー率がそのまま500／210となり
１周1024個のパルスに対して500パルスが出力さ
れるのである。 In other words, since the input ratio to the integrating circuit is 500/2 10 , the overflow rate becomes 500/2 10 as is, and 500 pulses are output for 1024 pulses per cycle.
以上述べたように本発明によれば、PGのスリ
ツト数以下であれば任意の数に２相パルスを変換
することができ、融通性の高い装置を提供でき
る。
As described above, according to the present invention, it is possible to convert two-phase pulses into any number of pulses as long as the number is equal to or less than the number of slits in the PG, thereby providing a highly flexible device.
なお、本発明の装置はPG本体に組み込んでも
よく、別個に設けても良い。 Note that the device of the present invention may be incorporated into the PG main body, or may be provided separately.
第１図は、本発明の具体的実施例、第２図は、
本発明の動作を説明する図である。
１−ｃ，２−ｃ：FULL ADDER、１−ｄ，
２−ｄ：Ｄフリツプフロツプ。
FIG. 1 shows a specific embodiment of the present invention, and FIG. 2 shows a specific embodiment of the present invention.
It is a figure explaining operation of the present invention. 1-c, 2-c: FULL ADDER, 1-d,
2-d: D flip-flop.
Claims (1)
ルスを該パルスジエネレータの回転方向によつ
て定まる所定の２進数データに変換するパルス
処理回路部と、 (b) １回転あたりの所望の出力パルス数（ただし
パルスジエネレータのスリツト数以下）を２進
数の各桁の１または０をそれぞれ電気信号のオ
ンオフで設定するPPR設定部と、 (c) 前記PPR設定部で設定された定数である各
桁のオンオフ信号と、前記パルス処理回路部の
出力信号（２進数データ）として得られる前記
２相パルスの少なくとも一方が立ち上がりまた
は立ち下がりのタイミングに同期する前記パル
ス処理回路部の出力２進数データとの排他的論
理和をとることで、前記タイミングに同期し
て、初期値ゼロが設定され以後前回値を保持し
ているＤフリツプフロツプに対し、前記PPR
設定部で設定された定数を加算または減算を繰
り返す積分回路部と、 (d) 前記積分回路部の上位の桁あふれ分の２桁の
２進数データを２相パルスに変換する２相化回
路とを、 備えることを特徴とする出力パルス数可変装置。[Scope of Claims] 1 (a) a pulse processing circuit section that converts a two-phase pulse output from a pulse generator into predetermined binary data determined by the rotational direction of the pulse generator; (b) 1 (c) a PPR setting section that sets the desired number of output pulses per rotation (but not more than the number of slits of the pulse generator) by turning each digit of the binary number 1 or 0 on and off of an electrical signal; (c) the PPR setting section; The pulse processing circuit synchronizes with the rising or falling timing of at least one of the on/off signal of each digit, which is a set constant, and the two-phase pulse obtained as an output signal (binary data) of the pulse processing circuit unit. By performing an exclusive OR with the output binary data of the D flip-flop, in synchronization with the timing, the PPR
(d) an integrating circuit section that repeatedly adds or subtracts a constant set in the setting section; and (d) a two-phase circuit that converts the two-digit binary data corresponding to the upper digit overflow of the integrating circuit section into a two-phase pulse. An output pulse number variable device comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58187494A JPS6078352A (en) | 1983-10-05 | 1983-10-05 | Varying device of output pulse number |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58187494A JPS6078352A (en) | 1983-10-05 | 1983-10-05 | Varying device of output pulse number |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6078352A JPS6078352A (en) | 1985-05-04 |
| JPH0412406B2 true JPH0412406B2 (en) | 1992-03-04 |
Family
ID=16207041
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58187494A Granted JPS6078352A (en) | 1983-10-05 | 1983-10-05 | Varying device of output pulse number |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6078352A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4713564B2 (en) * | 2007-03-30 | 2011-06-29 | 正判 横田 | Tape cutter |
-
1983
- 1983-10-05 JP JP58187494A patent/JPS6078352A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6078352A (en) | 1985-05-04 |
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