JPH04124744A - Initialization system for main storage - Google Patents

Abstract

PURPOSE:To reduce the load of a higher rank host and to shorten the starting time of an information processor by providing the hardware in order to initialize a main storage when the information processor is started. CONSTITUTION:When an information processor 7 is started, a main storage initialization signal 5 becomes 'true'. Thus a main storage control signal generating circuit 4 starts a writing operation to a main storage 1. At the same time, an address generating circuit 2 produces successively all existing addresses of the storage 1 from an address 0 with synchronization secured with the circuit 4. Meanwhile an initialization write data '0' output circuit 3 always outputs the write data '0'. That is, the address data '0' produced by the circuit 2 at initialization are successively written into the storage 1. The signal 5 becomes 'false' concurrently with the end of writing operations to all addresses of the storage 1. Thus the initializing operation of the storage 1 is completed.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an initialization method for a main memory device.

[Conventional technology]

Conventionally, in this type of initialization method, the upper host uses firmware to initialize the main memory by writing write data "O" to all existing addresses of the main memory. Ta.

[Problem to be solved by the invention]

In the conventional method described above, write operations are performed on all addresses of the main memory where the upper host resides, so if the capacity of the existing main memory is large, the initialization operation alone takes time, and during that time, The main storage initialization method of the present invention has the drawback that the main storage device can only perform write operations to the main storage device and occupies the main storage device. a main memory device consisting of a dynamic RAM capable of configuring the data, a circuit that outputs "O" as write data during initialization, and an address generation circuit that outputs only during initialization.
It has a main memory g orthogonal periodization signal means which becomes "true" at the start of initialization and becomes "false" at the end of initialization of all addresses of the main memory device, and a main memory device control signal generation circuit.

〔Example〕

The present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

The information processing device 7 includes a main memory device 1, an address generation circuit 2 at the time of initialization, a circuit 3 that outputs write data "0" at the time of initialization, a main memory device control signal generation circuit 4, and an upper post 6. It consists of

When the information processing device 7 is started up, the initialization signal 5 becomes "true". After monitoring that the main memory Ha initialization signal 5 is “true”, the main memory device control signal generation circuit 4
Start a write operation to.

At the time of initialization, the address generation circuit 2 monitors that the main memory initialization signal 5 is "true" and then sequentially generates all existing addresses of the main memory 1 starting from address O, and generates a main memory control signal generation circuit. Occurs in synchronization with 4.

The circuit 3 which outputs write data "0" at initialization always outputs "O" as write data after monitoring that the main memory initialization signal 5 is "true". That is, the address generation circuit 2 at the time of initialization, the circuit 3 that outputs write data "0" at the time of initialization, and the main memory g position control signal generation circuit 4 determine that the main memory device initialization signal 5 is "true". By monitoring, data "0'" is sequentially written into the main memory device 1 at the addresses generated by the address generation circuit 2 at the time of initialization.

At the same time as the write operation to all existing addresses of the main memory device 1 is completed, the main memory device initialization signal 5 becomes “false” and the initialization operation to the main memory device 1 is completed. During this time, the upper post 6 is initializing not the main storage device 1 but other devices.

〔Effect of the invention〕

As explained above, the present invention provides hardware for initializing the main storage device when starting up an information processing device, thereby reducing the load on the upper host, improving throughput, and reducing startup time. It has the effect of speeding up the process.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Main memory device, 2... Address generation circuit at the time of initialization, 3... Circuit that outputs write data "0" at the time of initialization, 4... Main memory g position control signal generation circuit, 5...
・Main storage device initialization signal, 6... Upper host, 7...
・Information processing equipment.

Claims (1)

[Claims] It has a main memory device consisting of a dynamic RAM that can be read and written from a host host, has a circuit that outputs "0" as write data during initialization, and has an address generation circuit that outputs only during initialization. and main memory initialization signal means that becomes "true" at the start of initialization and becomes "false" when initialization of all addresses of the main memory device is completed, and includes a control signal generation circuit for the main memory device. A method for initializing the main memory when starting up an information processing device.