JPH0412529A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To contrive to realize a prescribed isolation breakdown strength without reducing the film thickness of an isolation oxide film and without adjusting an impurity concentration in a channel stopper by a method wherein a frame, which has a prescribed thickness and consists of a nitride film, is formed on the sidewall of an opening part. CONSTITUTION:An oxide film 2 and a polycrystalline silicon film 3 are laminated in order, are formed on the main surface of a semiconductor substrate 1 and a nitride film 4 is formed on this film 3. An opening part 11 of a prescribed form is formed by removing selectively the films 4 and 3 in the depth direction from this film 4 down to the film 3 leaving the film 3 of a prescribed thickness under the lower part of the opening part 11. After that, a frame, which has a prescribed thickness and consists of the film 4, is formed on the sidewall of this opening part 11 and moreover, an isolation oxide film 16 is formed by oxidizing the opening part 11 using this film 4 as a mask. Thereby, the thickness, which is situated on the upper side of the surface of the substrate 1, of the formed film 16 becomes roughly equal with the thickness, which is situated on the lower part of the surface of the substrate 1, of the film 16 and the thickness of the film 16 on the lower side of the substrate surface becomes one of a sufficient degree to obtain reliably a prescribed isolation breakdown strength without adjusting an impurity concentration in a channel stopper.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to an improvement in a method for forming an element isolation structure in a semiconductor device.

[Background Art] In recent years, as semiconductor devices have become highly integrated, the miniaturization of each element constituting a large-scale integrated circuit device (LSI) has progressed rapidly. A field effect transistor is one of the elements constituting a semiconductor device. Device isolation technology for isolating each field effect transistor is one of the most important technologies for constructing highly integrated semiconductor devices. In particular, large-capacity dynamic random access memory (DR)
In semiconductor devices such as AM), the dimensions of a memory cell are influenced by the dimensions of element isolation. That is, the size of the memory cell is determined by how the distance between elements is reduced. Therefore, technological development regarding miniaturization of element isolation structures of semiconductor devices is progressing.

Today, the most well-known device isolation method is LOCO3 (
local oxidation ofsilic
This is a method called the on) method. Research is underway to further improve this LOCO8 method and reduce the element isolation width to the sub-micron order. Figures 4A to 4F
The diagram shows, for example, Oxidation Rate
Reduction in the Submi
crometer LOCO8Process
IEEE TRANSACTIONS ON
ELECTRON DEVICES, VOL,
ED-34, No. 11. NOVEMBERp
2255-2259 1987, illustrating a method for forming an isolation oxide film in order of steps; FIG. The method disclosed in this document differs from the LOCO8 method in that a nitride film is formed on the underlying oxide film with a polycrystalline silicon film interposed, and this method uses 5EPOX (Select
ive Polysilicon Oxidati
on) law.

In the method disclosed in the above document, with reference to FIG. 4A,
First, a silicon oxide film 2 is formed over the entire surface of a p-type silicon substrate (or p-type well) 1.

A polycrystalline silicon film 3 is formed on this silicon oxide film 2. Silicon nitride film 4 is formed on polycrystalline silicon film 3 so as to have an opening that exposes at least a part of the surface of polycrystalline silicon film 3 .

Referring to FIG. 4B, a second silicon nitride film 5 is formed over the entire surface of silicon nitride film 4 so as to fill the opening.

As shown in FIG. 4C, silicon nitride film 5 is selectively removed using an anisotropic etching technique such as reactive ion etching. As a result, the spacer nitride film 6 remains on the side wall portion defining the opening of the silicon nitride film 4.

As a result, even if the silicon nitride film 4 in FIG. 4A has an opening width that is at the patterning limit of the photolithography technique, an opening that has a width S smaller than that limit is formed. Thereafter, field oxidation treatment is performed in a wet oxygen atmosphere.

Referring to FIG. 4D, a thick isolation oxide film 7 is formed.

At this time, the isolation oxide film 7 is ion-implanted by p-type impurity ions in the step shown in FIG. 4C or by high-energy ion-implantation of p-type impurities in the step shown in FIG. 4D. A channel stopper region may be formed underneath. FIG. 4E shows a structure in which a p+ impurity region 8 as a channel stopper is formed under a thick isolation oxide film 7.

Thereafter, silicon nitride film 4.5 and polycrystalline silicon film 3 are removed by etching. In this way, isolation oxide film 7 having an element isolation width on the order of sub-microns is completed (FIG. 4F).

According to the above-mentioned prior art, by forming a spacer nitride film in the opening of the nitride film, an opening smaller than the patterning limit (about 0.5 μm) of photolithography technology can be formed. This makes it less than 1 μm and even 0
．． A nitride film having an opening width on the sub-micron order of less than 5 μm can be formed.

[Problem to be solved by the invention] However, in the manufacturing method in the above-mentioned prior art,
There were the following problems.

First, since thermal oxidation of the polysilicon film formed above the semiconductor substrate 1 mainly progresses, the cross-sectional shape of the isolation oxide film 7 has a thickness tl above the surface of the semiconductor substrate 1, as shown in FIG. 4F. , is significantly larger than the thickness t2 below it. As a result, more important for element isolation,
The thickness of the isolation oxide film 7 below the surface of the semiconductor 1 is not ensured sufficiently, and the isolation breakdown voltage for preventing the formation of a parasitic channel is degraded.

Now, let us consider the case where a conductive layer such as a wiring layer is formed on the isolation oxide film. FIG. 5 shows a structure in which a conductive layer such as a wiring layer is formed on an oxide film separating field effect transistors. Referring to FIG. 5, isolation oxide film 7 is formed on p-type silicon substrate 1. Referring to FIG. N9 impurity regions 8a and 8b are formed on both sides of isolation oxide film 7. Under the isolation oxide film 7 is a p" layer as a channel stopper.
An impurity region 8 is formed. A conductive layer 10 such as a wiring layer is formed on the isolation oxide film 7.

In such an element isolation structure, a parasitic MO3h transistor is configured. The parasitic MO8) transistor is composed of a conductive layer lO functioning as a gate electrode, n+ impurity regions 8a and 8b functioning as source/drain regions, and an isolation oxide film 7 functioning as a gate insulating film.

In the above parasitic MO3) transistor, the gate voltage (
The relationship between vo) and drain current (ID) is shown by the solid line in FIG. According to this, when the gate voltage exceeds Vtfl, that is, when a voltage exceeding Vtfl is applied to the conductive layer 10, the parasitic MO8) transistor operates. The smaller the film pressure t of this isolation oxide film 7, the Vtf
The value of l becomes smaller. In other words, when the film thickness of the isolation oxide film 7 becomes smaller, a parasitic channel is more likely to be formed under the isolation oxide film 7. To solve this problem, a p+ impurity region 8 is formed as a channel stopper under the isolation oxide film 7. It is possible to increase the concentration of As a result, as shown in FIG. 6, the minimum gate voltage at which the parasitic MOS transistor operates is Vt.
fl to Vtf2.

However, increasing the concentration of p4 impurity region 8 will degrade the breakdown voltage of the pn junction between adjacent n1 impurity regions ga and 8b. For example, the drain voltage (VD) and drain current (It
)) is shown in FIG. Now, the gate voltage (V
c) is Ov, and the relationship between drain voltage and drain current is shown by a solid line. At this time, when the concentration of the p" impurity region 8 is increased, the relationship between the drain voltage and the drain current changes as shown by the two-dot chain line. This means that when the drain voltage is v2 lower than ■1, the drain current is It means increasing rapidly, i.e. n0
A short-circuit phenomenon, so-called punch-through, between impurity regions 8a and 8b will occur at lower applied voltages. Therefore, even if the impurity concentration of the channel stopper is increased in order to prevent the formation of a parasitic channel due to the phenomenon of the film thickness of the isolation oxide film, it will conversely deteriorate the withstand voltage of the p-n junction and eventually cause the punch-through phenomenon. This is a factor that can easily cause this.

Furthermore, in order to prevent the film thickness of the isolation oxide film from decreasing due to the reduction in the opening width of the nitride film, that is, the isolation width, it is conceivable to lengthen the time of the field oxidation process. However, if the time of the field oxidation treatment is increased, the isolation oxide film expands laterally, or the so-called bird's beak becomes larger.

This results in a larger device isolation width.

As described above, in the prior art, even if it is possible to reduce the opening width of the region to be oxidized by sub-micron order by using a spacer nitride film, it is difficult to reduce the separation breakdown voltage. Not sub-9 micron
It has been difficult to form a field oxide film having an isolation width on the order of magnitude.

Therefore, an object of the present invention is to solve the above-mentioned problems, and to prevent the film thickness of the isolation oxide film from decreasing in the device isolation width of the sub-micron order, and to prevent the formation of parasitic channels. An object of the present invention is to provide a method for manufacturing a semiconductor device that can have a predetermined isolation breakdown voltage without adjusting the impurity concentration of a channel stopper under a film.

[Means for Solving the Problems] According to the method of manufacturing a semiconductor device according to the present invention, first, an oxide film and a polycrystalline silicon film are sequentially stacked and formed on the main surface of a semiconductor substrate. A nitride film is formed on this polycrystalline silicon film.

By selectively removing in the depth direction from the nitride film to the polycrystalline silicon film, an opening with a predetermined shape is created.
A polycrystalline silicon film of a predetermined thickness is left below. Thereafter, a frame of a nitride film having a predetermined thickness is formed on the side wall of this opening, and the opening is oxidized using this nitride film as a mask, thereby forming an isolation oxide film.

[Function] In this invention, an opening is formed by selectively removing not only the nitride film but also the polycrystalline silicon film, leaving a polycrystalline silicon film of a predetermined thickness beneath the opening; A nitride film frame is formed on the side wall. Therefore, while maintaining the effect of reducing bird's beak due to the presence of the polycrystalline silicon film, the oxidation reaction above the semiconductor substrate surface is suppressed, and the oxidation reaction of silicon below the surface is promoted.

As a result, the thickness of the isolation oxide film formed is almost uniform on the top and bottom of the semiconductor substrate surface, and the thickness of the isolation oxide film below the semiconductor substrate surface can be adjusted to a predetermined value without adjusting the impurity concentration of the channel stopper. This is sufficient to ensure the separation pressure of .

[Embodiments] Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

FIGS. 1A to 1G are partial cross-sectional views showing, in order of steps, a method for forming an element isolation oxide film in an embodiment of the present invention.

Referring to FIG. 1A, a silicon oxide film 2 having a thickness of about 500 Å is formed over the entire surface of a p-type silicon substrate (or p-type well) 1. On this silicon oxide film 2, a polycrystalline silicon film 3 and a silicon nitride film 4 each having a thickness of about 2000 Å are formed.

Next, referring to FIG. 1B, an opening 11 is formed in silicon nitride film 4 and polycrystalline silicon film 3 in a region where an isolation oxide film is to be formed, using photolithography.

Below the bottom of this opening 11, a polycrystalline silicon film 3 with a predetermined thickness remains between it and the silicon oxide film 2.

Next, referring to FIG. 1C, a silicon nitride film 5 having a thickness of about 1000 Å is formed over the entire surface of the semiconductor substrate l. Thereafter, this silicon nitride film 5 is subjected to anisotropic etching such as reactive ion etching to form a spacer nitride film 16 on the side wall of the opening 11 (FIG. 1D).

Next, referring to FIG. 1E, boron, which is a p-type impurity, is implanted into semiconductor substrate 1 through opening 11. Next, referring to FIG. The ion implantation conditions are an acceleration voltage of 507100 keV and an implantation amount of about 0.8X10" to 3XIQ13/cm2.

Next, in a wet oxygen atmosphere at about 950°C,
By applying field oxidation treatment for 0 minutes, 30
Isolation oxide film 7 having a thickness of approximately 00A is formed.

At the same time, the semiconductor substrate 1 has a surface concentration of 1×
A p0 impurity region 12 of about 1017 to 1×1018/Cm3 is formed as a channel stopper under the isolation oxide film 7 (FIG. 1F).

In order to form the channel stopper, in the above embodiment, ion implantation is performed before field oxidation treatment, but high energy ion implantation may be performed after field oxidation treatment. The ion implantation conditions at this time were an acceleration voltage of 100 to 250 keV, and an implantation amount of 1 x 1012 to 250 keV.
It is about 5×10 12 to cm 2 . By applying heat treatment in the post-process, the surface concentration is reduced to 1×1017
The p“ impurity region 12 is approximately 1×10 18 /cm 3
is formed.

Thereafter, as shown in FIG. 1G, silicon nitride film 4, spacer nitride film 16 and polycrystalline silicon film 3 are removed by etching.

According to the process of this embodiment, by appropriately selecting the thickness of the polycrystalline silicon film 3 below the opening 11, the shape of the isolation oxide film 7 can be made to have a substantially uniform thickness above and below the surface of the semiconductor substrate 1. It is possible to form the protrusions in the form of a large diameter and without producing angular protrusions. By thinning the polycrystalline silicon film 3 in the area to be thermally oxidized, the oxidation reaction of the polycrystalline silicon film 3 on the semiconductor substrate 1 and the oxidation reaction of the silicon near the surface of the semiconductor substrate 1 are reduced. This is because the process progresses more or less evenly.

Further, since the polycrystalline silicon film 3 of a predetermined thickness exists below the opening 11, the spread of the bird's beak due to thermal oxidation is suppressed compared to the case where the silicon oxide film 2 is exposed. As a result, compared to the method shown as a conventional example, the spread of the bird's beak can be made smaller when forming the isolation insulating film 7 of the same thickness.

3. Polycrystalline silicon film when this embodiment is applied to a 64 mega DRAM. Silicon nitride film 4. Preferred shapes and dimensions of the opening 11, isolation oxide film 7, etc. are shown in the table below. Symbols for each dimension are as shown in FIG. 2A, which is an enlarged view of the vicinity of the opening 11 in FIG. 1D, and FIG. 2B, which is an enlarged view of the vicinity of the isolation oxide film 7 of FIG. 1G.

Note that in this embodiment, the formation of the spacer nitride film 16 is an essential condition in order to obtain the isolation oxide film 7 with an appropriate shape. That is, the third A immediately after the opening 11 is formed.
When thermal oxidation is performed without forming the spacer nitride film 16 in the state shown in the figure, thermal oxidation proceeds relatively quickly near the interface between the polycrystalline silicon film 3 and the silicon nitride film 4 on the sidewall of the opening 11. However, as shown in FIG. 3B, an angular protrusion 7a is formed. If 7a occurs at this time,
When forming conductive wiring etc. on the layer above the isolation insulating film 7 in a subsequent process, etching residue 13 may adhere to the recess under the protrusion 7a (see Figure 3C), which may cause a short circuit between adjacent conductive wirings. There is a risk that such problems may occur.

[Effects of the Invention] As described above, according to the present invention, the opening selectively removes not only the nitride film but also the polycrystalline silicon film, and furthermore, there is a polycrystalline silicon film of a predetermined thickness below the nitride film. Since a nitride film frame is formed on the side wall of the opening, the following effects can be obtained.

First, the isolation oxide film can be formed to have a substantially uniform thickness above and below the surface of the semiconductor substrate while maintaining the effect of suppressing the spread of bird's beak. This ensures a sufficient thickness of the isolation oxide film below the semiconductor substrate surface, and as a result, the operation of the parasitic MO8) transistor is prevented without adjusting the impurity concentration of the channel stopper, and the isolation breakdown voltage is improved. be able to.

In addition, the isolation oxide film does not produce angular protrusions (because it is formed, when forming conductive wiring etc. on the layer above the isolation oxide film, there are problems such as short circuits due to the adhesion of etching residue). can be prevented from occurring.

[Brief explanation of drawings]

Figure 1A, Figure 1B, Figure 1C, Figure 1D, Figure 1E,
FIGS. 1F and 1G are partial cross-sectional views sequentially showing the manufacturing process of a semiconductor device in an embodiment of the present invention. FIG. 2A is an enlarged cross-sectional view showing the vicinity of the opening 11 immediately after the spacer nitride film 16 is formed on the side wall of the opening 11 in this embodiment, and FIG. 2B is an enlarged sectional view showing the isolation oxide film 7 in this embodiment. FIG. 3 is an enlarged cross-sectional view showing the vicinity of the isolation oxide film 7 after completion of the process. 3A, 3B, and 3C are partial cross-sectional views sequentially showing the steps of forming the isolation oxide film 7 to explain the problems when the spacer nitride film 16 is not formed in the steps of this embodiment. It is a diagram. FIGS. 4A, 4B, 4C, 4D, 4E, and 4F are partial cross-sectional views sequentially showing the steps of forming an isolation region in a conventional semiconductor device manufacturing method. Figure 5 shows a parasitic MO8 constructed using an isolation oxide film)
FIG. 2 is a cross-sectional view conceptually showing a transistor. FIG. 6 is a graph conceptually showing the relationship between the gate voltage and drain current of the parasitic MO8 transistor shown in FIG. FIG. 7 is a graph conceptually showing the relationship between the drain voltage and drain current of the parasitic MO3) transistor shown in FIG. In the figure, 1 is a semiconductor substrate, 2 is a silicon oxide film, and 3 is a semiconductor substrate.
1 is a polycrystalline silicon film, 4.5 is a silicon nitride film, 7 is an isolation oxide film, 11 is an opening, and 16 is a spacer nitride film. In addition, parts given the same numbers in the figures indicate the same or equivalent elements. 7: 4 negative and 1k (D

Claims (1)

[Claims] (1) A method for manufacturing a semiconductor device having an element isolation structure, which includes the steps of sequentially stacking an oxide film, a polycrystalline silicon film, and a nitride film on the main surface of a semiconductor substrate, and starting from the nitride film to the polycrystalline silicon film. forming an opening in a predetermined shape while leaving a polycrystalline silicon film with a predetermined thickness by selectively removing the polycrystalline silicon film in the depth direction; A method for manufacturing a semiconductor device, comprising the step of forming a frame of a nitride film.