JPH0412536A - compound semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a compound semiconductor device, and particularly to a technique that is effective when applied to a compound semiconductor device having a Pn junction diode element.

[Conventional technology]

Gallium arsenide field effect transistors (GaA
s-MESFET) is known.

This GaAs-MESFET is formed on the main surface of a GaAs substrate (a compound semiconductor substrate or a semi-insulating substrate). Ga
As-MESFET mainly has a channel region.

It consists of a source region, a drain region, and a gate electrode.

The inventor is developing a highly integrated GaAs-MESFET for use in the UHF band. This type of GaAs-MESFET is 200[v]
A higher electrostatic breakdown voltage is required. To obtain such electrostatic breakdown voltage, it is common to incorporate an electrostatic breakdown prevention circuit (static protection element). For example, a GaAs-MESFET currently being developed by the present inventor employs a dual gate structure, and an electrostatic breakdown prevention circuit is inserted between each of the first gate electrode, the second gate electrode, and the source region. This electrostatic breakdown prevention circuit is composed of a pn junction type diode element.

The pn junction diode element, which is the electrostatic breakdown prevention circuit, has an n-type semiconductor region (cathode region) and a p-type semiconductor region (anode region) formed on the main surface of a GaAs substrate.
Consists of. The p-type semiconductor region is formed by diffusing P-type impurities from the main surface of the GaAs substrate into the main surface of the GaAs substrate in a region defined by a diffusion mask using a thermal diffusion method. An end of the p-type semiconductor region contacts the n-type semiconductor region to form a pn junction. Zn (zinc) is generally used as the p-type impurity because it has a high activation rate and can be formed at a high impurity concentration.

The pn junction diode element includes a p-type semiconductor region, n
An anode electrode and a cathode electrode are connected to each of the type semiconductor regions. Each of the anode electrode and cathode electrode is
It is formed on a passivation film that covers the pn junction diode element, and is connected to each region through the opening formed in this passivation film. For example, the passivation film has a higher G a A than a silicon nitride (Si, N4) film.
It is formed of a PSG film that has low stress with the s-substrate.

Note that G, which has this type of pn junction diode element,
Regarding aAs-MESFET, see, for example, IEICE, rED84-86J, Vol. 84. No.

185, pages 7 to 13.

[Problem to be solved by the invention]

The present inventor discovered the following problems with the above-mentioned pn junction diode element as the electrostatic breakdown prevention circuit.

Zn, which is a p-type impurity in the p-type semiconductor region of the p-n junction diode element, has a lateral diffusion distance along the surface of the GaAs substrate (lateral diffusion distance) compared to a diffusion distance in the depth direction of the GaAs substrate. ) is large.

For example, Zn causes abnormal diffusion in which the lateral diffusion distance is 4 to 7 times longer than the depth direction diffusion distance. This Zn
The abnormal diffusion occurs between the GaAs substrate and the passivation film (P
This is thought to be due to the low adhesive strength with the SG film. Therefore, the area occupied by the P-type semiconductor region, that is, the anode region on the GaAs substrate increases, and the area occupied by the -pn junction diode element increases, resulting in a decrease in the degree of integration of the compound semiconductor device.

In addition, the abnormally diffused region in the lateral direction of the p-type semiconductor region of the p-n junction diode element has a higher concentration of P than other regions.
The impurity concentration of type impurities decreases.

In other words, the parasitic resistance value of this abnormally diffused region increases, increasing the series resistance value between the anode electrode and the cathode electrode. For this reason, the on-resistance in terms of V and characteristics of the pn junction diode element increases, and in particular, it cannot absorb surge voltage (excessive voltage), resulting in frequent electrostatic breakdown of the MESFET.

An object of the present invention is to provide a technique that can improve the degree of integration in a compound semiconductor device having a pn junction diode element.

Another object of the present invention is to provide a technique capable of reducing the on-resistance value of the pn junction diode element.

Another object of the present invention is to provide a technique capable of improving the electrostatic breakdown voltage of the MESFET in a compound semiconductor device having a MESFET that uses a pn junction diode element as an electrostatic breakdown prevention circuit.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means to solve the problem]

A brief overview of typical inventions disclosed in this application is as follows.

(1) In a compound semiconductor device comprising a pn junction diode element on the main surface of a compound semiconductor substrate, the pn
A junction diode element intersects a p-type semiconductor region formed in a first region of the main surface of the compound semiconductor substrate, and a surface of the first region at an end of the first region of the main surface of the compound semiconductor substrate. In addition, the n-type semiconductor region is formed in a second region extending in the depth direction of the compound semiconductor substrate.

The second region in which the n-type semiconductor region of the pn junction diode element is formed is an inner wall of a moat or an outer wall of a mesa formed on the main surface of the compound semiconductor substrate.

(2) The pn junction diode element constitutes a protection element of an electrostatic breakdown prevention circuit inserted between the gate electrode and source region of the MESFET.

[For production]

According to the above-mentioned means (1), since the lateral diffusion along the main surface of the compound semiconductor substrate of the P-type semiconductor region (anode region) of the p-n junction diode element can be suppressed on the surface of the second region, the p-n junction The area occupied by the type diode element can be reduced, and the degree of integration of the compound semiconductor device can be improved. Also,
Since the parasitic resistance value caused by the lateral diffusion of the p-type semiconductor region of the p-n junction diode element can be reduced, the on-resistance in terms of V and characteristics of the diode element can be reduced. Further, the lateral diffusion of the P-type semiconductor region of the p-n junction diode element is suppressed at the surface of the second region, and the suppressed p-type impurity is distributed along the surface of the second region in the depth direction of the compound semiconductor substrate. Therefore, the pn junction surface between the p-type semiconductor region and the n-type semiconductor region can be curved, and the pn junction area can be increased. As a result, the area occupied by the pn junction diode element can be reduced, and the degree of integration of the compound semiconductor device can be improved.

According to the above-mentioned means (2), the on-resistance of the pn junction diode element can be reduced, so that the surge voltage absorption efficiency can be increased and the electrostatic breakdown voltage of the MESFET can be improved.

Hereinafter, regarding the configuration of the present invention, the electrostatic breakdown prevention circuit will be described.
An embodiment in which the present invention is applied to a compound semiconductor device having a dual-gate structure GaAs-MESFET constituted by an n-junction diode element will be described.

Note that throughout the description of the embodiments, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Embodiments of the invention]

FIG. 2 (equivalent circuit diagram) shows the structure of a compound semiconductor device having a GaAs-MESFET, which is an embodiment of the present invention.

As shown in Figure 2, G
The aAs-MESFET (Tr) has a dual gate structure. In other words, GaAs-MESFET (Tr)
has two first gate electrodes (G1) and a second gate electrode (G1).
G2), a gate electrode (G), a source electrode (
S) and a drain electrode (D).

The first of this GaAs-MESFET(Tr)
An electrostatic breakdown prevention circuit is inserted between each of the gate electrode (Gl) and the second gate electrode (G2) and the source electrode (S). This electrostatic breakdown prevention circuit is composed of a back-to-back pn junction diode element (DI) and a pn junction diode element (D2).

One pn junction diode element (Dl) is inserted between the first gate electrode (G1) and the source electrode (S).

A pn junction diode element (Dl) is composed of two diode elements whose cathode regions are connected to each other. The anode region of one of the diode elements is connected to the first gate electrode (G1), and the anode region of the other diode element is connected to the source electrode (S).

Moreover, the other pn junction type diode element (D2) is the second
It is inserted between the gate electrode (G2) and the source electrode (S). The pn junction diode element (D2) is composed of two diode elements whose cathode regions are connected to each other. The seven node regions of one of the diode elements are connected to the second gate electrode (G2), and the other seven node regions are connected to the source electrode (S).

Next, the specific structure of the GaAs-MESFET (Tr) pn junction diode element D (Di, D2) will be explained using FIG. 1 (a sectional view of the main part).

The aforementioned compound semiconductor device is composed of a GaAs substrate (compound semiconductor substrate or semi-insulating substrate) 1.

The main surface of this GaAs substrate 1, which is the element formation surface, has the
Each of an aAs-MESFET (Tr) and a pn junction diode element is mounted. The main surface of the GaAs substrate 1 is composed of a (100') crystal plane. Although not shown, in the manufacturing process of compound semiconductor devices, Ga
The orientation flat of the As semiconductor wafer (the state before the dicing process of the GaAs substrate 1) is (0
1) Consists of crystal planes.

The GaAs-MESFET (Tr) has a gate electrode (G
) is the conductive film 3. It is composed of an n-type semiconductor region 2A which is a channel region, and a pair of go-type semiconductor regions 2 which are a source region (S) and a drain region (D).

The conductive film 3 is made of AQ, for example. Go-type semiconductor region 2
A wiring 9 is connected to the main surface of the substrate with an electrode 7 interposed therebetween. The electrode plate is composed of a laminated film in which AuGe, Ni, and Au are laminated in sequence, for example. This electrode 7 is connected to the surface of the Go-type semiconductor region 2 through an opening formed in the passivation film 6. The passivation film 6 is made of GaAs
The stress between the substrate 1 and the substrate 1 is small; for example, it is made of a PSG film.

Wiring 9 is connected to electrode 7 through an opening formed in passivation film 8 .

The pn junction diode element (D) constituting the electrostatic breakdown prevention circuit is composed of a p° type semiconductor region 5 used as an anode region and a go type semiconductor region 2 used as a cathode region. This P.

An anode electrode (not shown) 7 and a cathode electrode 7 are connected to the surfaces of the n-type semiconductor region 5 and the n-type semiconductor region 2, respectively.

Basically, the Go-type semiconductor region 2 which is the cathode region is manufactured substantially the same as the n-type semiconductor region 2 which is the source region (S) or drain region (D) of the GaAs-MESFET (Tr). formed in the process. The r1'' type semiconductor region 2 is 1, for example, 10'' [at.

G a
A 0.3 [μm in the depth direction from the surface of the substrate l
] to a depth (xj).

between the p° type semiconductor region 5 which is the anode region and the cathode electrode 7, that is, the p° type semiconductor region 5 at the end thereof.
A moat (groove) 4 is provided in the formation region of the n-junction surface and on the n° type semiconductor region 2 side thereof. In other words, the n° type semiconductor region 2 is formed on the main surface of the GaAs substrate 1 along the inner wall and bottom of the moat 4 provided at the end of the p type semiconductor region 5, and The moat 4 formed on the main surface of the GaAs substrate 1 up to the cathode electrode has a cross-sectional shape of a rectangular or inverted trapezoid (the width of the bottom deeper than the main surface compared to the opening width of the main surface). (Small shape) Although not shown, the planar shape of the moat 4 is a slit shape that is elongated in the direction perpendicular to the paper surface of FIG.

The inner wall in the longitudinal direction of the slit shape of this moat 4 is composed of a plane substantially parallel to the orientation flat described above, and the inner wall in the longitudinal direction of this moat 4 is a (011) crystal plane (aligned with the along) is formed. Note that depending on the conditions used in the manufacturing process, such as the etching solution, the cross-sectional shape of the moat 4 is configured to have an inverted trapezoidal shape as described above, so that the inner wall in the longitudinal direction of the moat 4 is (01
1) Composed of crystal planes close to crystal planes. In this way, when the moat 4 whose longitudinal inner wall of the slit shape is formed of (011,) crystal planes is processed by dry etching or wet etching, it can be seen in Figs. 1 and 3 (enlarged cross-sectional views of main parts). As shown, the cross-sectional shape can be easily formed into a rectangular shape or an inverted trapezoidal shape. The moat 4 having this cross-sectional shape is
According to the basic research conducted by the present inventor, the amount of lateral abnormal diffusion of P-type impurities (for example, Zn) on the main surface side of the GaAs substrate 1 can be reduced compared to a moat with a trapezoidal cross-sectional shape. Obtained. For example, the width of the slit shape in the short side direction of the moat 4 is set to 1 to 2 [μm1. Depth 1 to 2 μm
]. The depth of this moat 4 should be at least deeper than the depth at the end of the P° type semiconductor region 5.

The p° type semiconductor region 5, which is the anode region, is formed with a high impurity concentration of, for example, 101 g [atoms/al], and is slightly deeper from the surface of the GaAs substrate l than the n° type semiconductor region 2. Ru. As shown in FIG. 3, the p° type semiconductor region 5 is formed by diffusing n type impurities by thermal diffusion using a diffusion mask (for example, a photoresist film) 10. Zn, which has a high activation rate and can be formed at a high impurity concentration, is used as the n-type impurity. In addition to Zn, n-type impurities include M
g * M n + B e etc. may also be used.

A method for forming this pn junction diode element (D) will be briefly explained using FIGS. 1 and 3.

First, in the formation region of the pn junction diode element (D), the moat 4 extending in the depth direction is formed on the main surface of the GaAs substrate 1. The moat 4 is formed using dry etching or wet etching.

Next, an n° type semiconductor region (cathode region) 2 is formed in the formation region of the pn junction diode element (D). The n° type semiconductor region 2 is formed, for example, by introducing an n type impurity using a combination of ion implantation and thermal diffusion. In the ion implantation method, the main surface of the GaAs substrate 1,
An n-type impurity is introduced into each bottom of the moat 4. This n
The type impurity is GaAS-MES'FET (Tr
) is also introduced into the formation regions of the source and drain regions. The thermal diffusion method introduces n-type impurities into the inner wall of the moat 4. Using a mask, this n-type impurity is introduced only into the formation region of the pn junction diode element (D).

Next, a diffusion mask 10 is formed in which a region for forming the anode region of the pn junction diode element (D) is opened.

Then, as shown in FIG. 3, this diffusion mask 1
A p'-type semiconductor region (anode region) 5 is formed by diffusing a P-type impurity (Zn) onto the main surface of the GaAs substrate 1 by thermal diffusion using Zn. By forming this p° type semiconductor region 5, a pn junction diode element (D) is substantially completed.

As shown in FIG. 3, the p° type semiconductor region 5 of the pn junction diode element (D) causes abnormal lateral diffusion of Zn toward the moat 4 along the main surface of the GaAs substrate 1. Lateral diffusion of Zn is suppressed by the slit-shaped inner wall of the moat 4 in the longitudinal direction. In other words, within the area defined by the inner wall of the moat 4 on the anode area side, pn
A P° type semiconductor region 5 of a junction diode element (D) is formed.

Further, the lateral diffusion of the p-type semiconductor region 5 occurs in the moat 4 near the interface between the inner wall of the moat 4 and the passivation film 6 (the part surrounded by the elliptical dotted line in FIG. 3).
hardly diffused in the depth direction 12 along the inner wall of 6
According to the basic research of the present inventor, the inner wall of moat 4 (01
1) It is considered that this is based on the fact that the amount of diffusion on the crystal plane is smaller than the amount of diffusion on the (011) crystal plane, for example. Also,
In the manufacturing process, after forming the p° type semiconductor region 5 and before forming the passivation film 6, the present inventor performs pre-cleaning before depositing the passivation film 6. It is believed that this is based on the removal of a shallow depth diffusion region of Zn along the inner wall. This pre-cleaning is performed using an ammonia-based etching solution having an etching rate of, for example, 100 to 300 [persons/in].

Further, the lateral diffusion at the end of the p' type semiconductor region 5 on the cathode region side is suppressed by the inner wall of the moat 4, and the Zn impurity concentration becomes slightly higher in this suppressed region. Zn is pushed and diffused in the depth direction in a defined state.

In other words, as much as this Zn is pushed out, the pn junction diode element (D) has a pn junction surface of the p° type semiconductor region 5 and the n° type semiconductor region 2.
It is curved compared to the bonding surface 11, and the pn junction area can be increased. According to the basic research of the present inventor, the pn junction area is approximately 20
[%] results were obtained.

In this way, in a compound semiconductor device that includes a pn junction diode element (D) on the main surface of the GaAs substrate 1, the pn junction diode element (D) is located on the main surface of the GaAs substrate 1. p' type semiconductor region formed in one region5. and intersects the surface of the first region at the end of the first region of the main surface of the GaAs substrate 1 and the Ga
It is composed of an n° type semiconductor region 2 formed in a second region (M of the moat 4) extending in the depth direction of the As substrate 1. The second region in which the Go-type semiconductor region 2 of this pn junction diode element (D) is formed is the inner wall in the longitudinal direction of the slit shape of the moat 4 formed on the main surface of the GaAs substrate 1. With this configuration, (1) the p° type semiconductor region (anode region) 5 of the pn junction diode element (D);
The lateral diffusion along the main surface of the G a As substrate 1 is the second
Since it is suppressed by the surface of the area (inner wall of moat 4), pn
The area occupied by the junction diode element (D) can be reduced and the degree of integration of the compound semiconductor device can be improved. (2) Since the parasitic resistance value (R shown in FIG. 3) caused by the lateral diffusion of the p-type semiconductor region 5 of the p-n junction diode element (D) can be reduced, the V According to the inventor's basic research, the on-resistance of the diode element in the vlI characteristic was reduced by 30 to 40%, and the noise characteristics of the diode element were also improved. Ta.

In addition, the input impedance of GaAs-MESFET(Tr) is changed from 0.6 [KΩ] to 0.4 [KΩ].
I was able to lower it to (3) The lateral diffusion of the p-type semiconductor region 5 of the p-n junction diode element (D) is suppressed on the surface of the second region, and the suppressed p-type impurity (Z
n) is diffused in the depth direction of the GaAs substrate 1 along the surface of the second region, so that the P° type semiconductor region 5 and n°
By curving the pn junction surface with the type semiconductor region 2, the Pn junction area can be increased. As a result, the area occupied by the pn junction diode element (D) can be reduced, so that the degree of integration of the compound semiconductor device can be further improved.

Further, the pn junction diode element (D) is made of GaA
It constitutes a protection element of an electrostatic breakdown prevention circuit inserted between a gate electrode (G) and a source region (S) of an s-MESFET (Tr). With this configuration.

Since the on-resistance of the pn junction diode element (D) can be reduced, the surge voltage absorption efficiency is increased.

The electrostatic breakdown voltage of GaAs-MESFET (Tr) can be improved. According to the basic research conducted by the present inventors, it was possible to improve the electrostatic breakdown voltage of the GaAs-MESFET (Tr) from 170 [V] to 250 [V].

Although the invention made by the present inventor has been specifically explained above based on the above embodiments, 9 the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

For example, the present invention provides a P' type semiconductor region (anode region) 5 provided on the upper surface of a mesa (trapezoidal island region) formed by mesa etching on the main surface of the GaAs substrate 1;
A pn junction diode element (D) may be formed by the n' type semiconductor region 2 provided on the outer wall of the mesa.

Furthermore, the present invention is not limited to single compound semiconductor devices, but can be applied to integrated compound semiconductor devices and semiconductor lasers.

r Effects of the Invention The effects obtained by typical inventions disclosed in this application are briefly explained below.

In a compound semiconductor device having a pn junction diode element, the degree of integration can be improved.

The on-resistance value of the pn junction diode element can be reduced.

A pn junction diode element is used as an electrostatic breakdown prevention circuit. In a compound semiconductor device having a MESFET, M
The electrostatic breakdown voltage of ESFET can be improved.

[Brief explanation of drawings]

FIG. 1 shows a GaAS-MESF that is an embodiment of the present invention.
FIG. 2 is an equivalent circuit diagram of the compound semiconductor device, and FIG. 3 is an enlarged sectional view of the main portion of the compound semiconductor device. In the figure, 1... Ga As substrate, 2... n° type semiconductor region, 3... conductor film, 4... moat, 5...
p° type semiconductor region, D... pn junction type diode element, Tr... Ga As MESFET.

Claims (1)

[Claims] 1. In a compound semiconductor device comprising a pn junction diode element on a main surface of a compound semiconductor substrate, the pn junction diode element is formed in a first region of the main surface of the compound semiconductor substrate. a p-type semiconductor region, and a second region formed at an end of the first region on the main surface of the compound semiconductor substrate, intersecting the surface of the first region and extending in the depth direction of the compound semiconductor substrate. 1. A compound semiconductor device comprising a type semiconductor region. 2. The compound semiconductor device according to claim 1, wherein the pn junction diode element constitutes a protection element of an electrostatic breakdown prevention circuit inserted between a gate electrode and a source region of a MESFET. 3. The second region in which the n-type semiconductor region of the pn junction diode element is formed is an inner wall of a moat or an outer wall of a mesa formed on the main surface of a compound semiconductor substrate. The compound semiconductor device according to claim 2.