JPH04125965A - Semiconductor device - Google Patents

Abstract

PURPOSE:To suppress low an output impedance, to maintain a high S/N and to detect a signal in a high sensitivity by a method wherein a change in the amount of charge stored in a light-receiving region is converted into an impedance by a transistor and the impedance is outputted. CONSTITUTION:An input gate electrode 71, a retention gate electrode 72 and an output gate electrode 73 are provided in order on a P-type substrate 1 between an N-type light-receiving region 2 and an N-type storage region 3 via an insulating film. In this constitution, charges generated in the region 3 are once held in a potential well directly under the electrode 72 via the electrode 71 and then, transferred to the region 3 via the electrode 73. Here, the region 3 is connected to the electrode 73 of a transistor for output use. Thereby, changes in the amount of a charge stored in the region 2 are converted into an impedance by the transistor and the impedance can be outputted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly relates to a semiconductor device that outputs a signal according to incident light.

[Conventional technology]

Conventionally, as such a semiconductor device, one shown in FIG. 3 is known. A p-type substrate 1 such as 81 is doped with an n-type impurity to form an n-type light-receiving region 2, and an n-type accumulation region 3 for accumulating photogenerated carriers is formed at a nearby position.

The p-type substrate 1 has an n-type drain 4 and an n-type source 5.
A field effect transistor (F
ET) is formed, and the n-type storage region 3 and gate electrode 6 are connected. In addition, an n-type light receiving region 2 and an n-type accumulation region 3
A capture gate electrode 7 is provided between them, and a capture signal G4 is applied thereto. Note that a grounded electrode 8 is provided on the back surface of the p-type substrate 1.

In the above configuration example, when signal light IN is input with a reverse bias voltage applied between the p-type substrate 1 and the n-type light-receiving region 2, charges are accumulated in the n-type light-receiving region 2. After the n-type storage region 3 is reset by the switch S, this charge is taken into the n-type storage region 3 via the take-in gate electrode 7, thereby changing the potential of the gate electrode 6 of the FET. Then, the detection signal is impedance-converted by the FET and output from the n-type source 5 to the outside via the terminal OUT. In this way, conventionally, by providing the intake gate electrode 7 between the n-type light receiving region 2 and the n-type accumulation region 3, the signal output can be achieved while keeping the output impedance low and maintaining a good S/N ratio. I was doing it.

[Problem to be solved by the invention]

However, according to the above-mentioned conventional technology, it is difficult to output a signal with high sensitivity due to the following reasons. To explain this with reference to diagram M4, first assume that in the circuit shown in the diagram, capacitors C and C are reset with switch S2 open and both have the same potential voo. In this state, when the potential of the capacitor C becomes Vol due to the photogenerated carriers, the potential change is (Voo-2.1). At this time,
When switch S is closed, capacitor C1 and cavantor C
If the electric charge is distributed between 2 and the potential after distribution is V, then it becomes V - V - (C/(C1+C210x1 (Voo-Vol)). In the above equation, (voo-■x) is Corresponds to the potential change of the gate electrode 6 of the FET, (v
Since oo-vol) corresponds to the potential change of the n-type light-receiving region 2, as long as the capacitance of the gate electrode 6, that is, the capacitor C2, has a finite size, the FET gate potential change and the photodiode potential change are There will no longer be a 1:1 relationship. Moreover, when capacitor C2 becomes large,
The gate potential change is reduced compared to the potential change of the n-type light receiving region 2. For example, capacitor C2 is 9
If it is twice the value, the change in the gate potential will be 1/10 of the change in the potential of the n-type light receiving region 2, and even in the case of C-C2, it will be 1/2. Therefore, if the signal charges in the n-type light-receiving region 2 are taken into the n-type storage region 3 as a voltage output as shown in FIG. 3, highly sensitive signal detection cannot be achieved.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device for photodetection that has a low output impedance, a high S/N ratio, and can detect signals with high sensitivity.

[Means to solve the problem]

A semiconductor device according to the present invention includes a semiconductor substrate of a first conductivity type, a light receiving region of a second conductivity type that generates charges in response to incident light, and a resettable region that accumulates charges sent from the light receiving region. In a device comprising a storage region of the second conductivity type and a signal output transistor having a gate electrode connected to the storage region, a semiconductor substrate between the light receiving region and the storage region is provided with charge in the light receiving region. It is characterized by being provided with an input gate electrode for taking in the charges, a holding gate electrode for temporarily holding the taken-in charges, and an output gate electrode for taking out the held charges to the storage region.

[Effect]

According to the present invention, charges generated in the light receiving region are temporarily held in the potential well directly under the holding gate electrode via the input gate electrode, and then transferred to the storage region via the output gate electrode.

Here, since the storage region is connected to the gate electrode of the output transistor, the resulting change in the amount of charge stored in the light receiving region can be impedance-converted by the transistor and output.

〔Example〕

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

FIG. 1 is a sectional view of a semiconductor device according to an embodiment. This is characteristically different from the conventional example shown in FIG. The electrode 71, the holding gate electrode 72, and the output gate electrode 73 are provided in this order. Here, an input control signal G1 is applied to the human-powered gate electrode 71, whereby the charge generated in the n-type light receiving region 2 is taken in. Holding gate electrode 7
A holding control signal G2 is applied to the holding control signal G2, whereby the charges taken in are temporarily held (accumulated). An output control signal G3 is applied to the output gate electrode 73, whereby the held charge is taken out to the n-type storage region 3.

Next, the operation of the above embodiment will be explained using the potential well diagram shown in FIG.

First, the n-type storage region 3 is reset by temporarily closing the switch S1 (FIG. 1).

In the initial state, both the n-type light receiving region 2 and the n-type storage region 3 are reset, and the input gate electrode 71, the holding gate electrode 72, and the output gate electrode 73 are all in an off state. When the signal light IN enters the n-type light-receiving region 2 in this state, charges are accumulated in the potential well of the n-type light-receiving region 2 according to the amount of light (as shown in FIG. 2(b)). Next, a pulse is applied to the holding gate electrode 72 as the holding control signal G2, and a deep potential well is formed directly under the holding gate electrode 72 (as shown in FIG. gate electrode 7], the potential well immediately below the input gate electrode 71 is lowered and the gate is opened. Then, the charge in the n-type light-receiving region 2 passes directly under the input gate electrode 71, is taken into the potential well directly under the holding gate electrode 72, and is held (as shown in FIG. 2(d)). In the above case, the pulses may be applied to the manual gate electrode 71 and the holding gate electrode 72 at opposite times or at the same time.

Next, after the charge path directly under the input gate electrode 71 is closed by the input control signal G1 (as shown in FIG. A charge path is opened directly below the electrode 73. As a result, the charges held directly under the holding gate electrode 72 are taken out to the n-type storage region 3 (as shown in FIG. 2(f)). After that, when the gate directly below the output gate electrode 73 is closed by the output control signal G3, n
The transfer of charge from the type light-receiving region 2 to the n-type accumulation region 3 is completed (as shown in FIG. 3(g)). Here, the n-type accumulation region 3 is F
Since it is connected to the gate electrode 6 of the ET, the potential of the gate electrode 6 changes in accordance with the change in the amount of charge in the n-type storage region 3, and is applied to the outside from the terminal OUT through the FET.

Therefore, the signal is output in the form of impedance conversion.

According to the above embodiment, the gate electrode 6 of the output FET and p
By making the capacitance formed with the type substrate 1 as small as possible, a change in the amount of charge in the n-type storage region 3 can be read as a large change in potential from the relationship V-Q/C. Note that since the photodetecting section is composed of a photodiode, it can have any shape. Further, by cooling it, it is possible to achieve higher sensitivity.

〔Effect of the invention〕

As explained above in detail, in the present invention, the charges generated in the light receiving region are temporarily held in the potential well directly under the holding gate electrode via the input gate electrode, and then transferred to the accumulation region via the output gate electrode. be done. Here, since the storage region is connected to the gate electrode of the output transistor, the resulting change in the amount of charge stored in the light receiving region can be impedance-converted by the transistor and output. Therefore, the output impedance is low, the S/N ratio is high, and signals can be detected with high sensitivity.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a semiconductor device for photodetection according to an embodiment of the present invention, and FIG. 2 is a potential well diagram showing its operation.
FIG. 3 is a sectional view of a conventional semiconductor device, and FIG. 4 is an explanatory diagram of the operation. 1...p-type substrate, 2...n-type light receiving region, 3...n
type accumulation region, 4... n-type drain, 5... n-type source, 6... gate electrode, 7... intake gate electrode, 7
1... Input gate electrode, 72... Holding gate electrode,
73...Output gate electrode. Figure 2 of operation example of representative patent attorney Yoshiki Hase

Claims (1)

[Claims] A first conductivity type semiconductor substrate includes a second conductivity type light receiving region that generates charges according to incident light, and a resettable second conductive region that accumulates the charges sent from the light receiving region. In a semiconductor device comprising a conductivity type storage region and a signal output transistor having a gate electrode connected to the storage region, a portion of the light receiving region is provided on the semiconductor substrate between the light receiving region and the storage region. an input gate electrode that takes in charge;
A semiconductor device comprising: a holding gate electrode that temporarily holds captured charges; and an output gate electrode that extracts the held charges to the storage region.