JPH04127331A - Interruption control system - Google Patents

Abstract

PURPOSE:To avoid the discrepancy of a source operand value after returning from an interruption processing by controlling the execution timing of the interruption processing generated in a pipeline processing. CONSTITUTION:The system is provided with a destination register number storage means which is fetched after a first instruction, and holds a number of a second data register 6 in a second instruction decoding period for fetching a source operand before writing a destination operand of a first instruction in a second data register 6, and a coincidence detecting circuit 9 for detecting a coincidence of a number of a second data register 6, and a number of a data register for fetching a source operand of a second instruction designated by an instruction decoding means 2 and outputting a coincidence detecting signal. In such a state, the timing is controlled as an interruption control signal CI by an AND gate 7. In such a way, it does not occur that a value of the source operand of a second instruction after an interruption processing becomes different.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an interrupt control method, and particularly to an interrupt control method for a central processing unit in an information processing system.

[Conventional technology]

There are at least the following two interrupt control methods for conventional pipeline processing central processing units.

In the first method, when interrupt processing is executed between instruction 1 and instruction j, the pipeline processing of instruction i is completed, and the pipeline processing of all instructions fetched after instruction i is stopped, and then the This method executes interrupt processing and re-executes the pipeline processing starting from the instruction fetch processing of instruction j.

In this method, for example, in a certain clock, five instructions, i.e., instruction i, instruction J, instruction l, instruction m, each perform five processes, i.e., operand write processing,
It is assumed that an interrupt processing request is made when instruction execution processing, operand read processing, instruction decode processing, and instruction fetch processing are executed in a pipeline. First, the operand write processing for instruction i is terminated, and then the instruction execution processing for instruction j, the operand fetch processing for the instruction, the instruction decode processing for instruction 1, and the instruction fetch processing for instruction m are stopped, and the interrupt processing is started. This method transfers control and then resumes pipeline processing from instruction fetch processing of instruction j.

The second method is to complete the pipeline processing of instruction i and save all intermediate states of the pipeline processing that precedes the operand write processing of instruction i, then execute interrupt processing, and then process the saved pipeline processing. This method re-executes pipeline processing by resetting all intermediate states.

In this method, for example, similarly to the first method, five instructions, i.e., instruction i, instruction j, and instruction l, and instruction m each perform five processes in a certain clock, i.e., operand write processing, and instruction execution. It is assumed that an interrupt processing request is made when processing, operand read processing, instruction decoding processing, and instruction fetch processing are executed in pie run-in.

First, the operand write processing of instruction i is finished, and then,
All pipeline states of instruction execution processing for instruction j, operand fetch processing for the instruction, instruction decoding processing for instruction l, and instruction fetch processing for instruction m are saved, control is transferred to interrupt processing, and interrupt processing is terminated. Reset the saved state and resume pipeline processing with operand write processing for instruction j, instruction execution processing for the instruction, operand fetch processing for instruction l, instruction decode processing for instruction m, and instruction fetch processing for instruction n. It is a method.

Generally, in the second method, control for saving and resetting intermediate states of all pipeline processing is considered to be complicated.

[Problem to be solved by the invention]

In the first conventional interrupt control method described above, when the same register is specified as the destination register of instruction i and the source register of instruction j, there is a case where interrupt processing is executed between instruction i and instruction j. There is a drawback that the value of the source operand of instruction j is different when it is not executed.

That is, the source operand of the former instruction j is instruction i
The source operand of the latter instruction j is the value of the destination operand of the latter instruction This is the destination obeland value of the instruction.

[Means to solve the problem]

The interrupt control method of the present invention includes: an instruction fetch unit that fetches an instruction; an instruction decoding unit that decodes the fetched instruction and outputs a decoded instruction; and first and second data that stores operand data. a register; operand fetching means for fetching a source operand from the first data register specified by the decode instruction; and instruction execution for performing an operation specified by the decode instruction on the source operand to obtain a testnation operand. and operand write means for fetching the destination operand and writing it to the second data register specified by the decode instruction, the pipeline processing method processing the instructions in a predetermined order by pipeline processing. In the computer interrupt control method, a second instruction is fetched after the first instruction and fetches the source operand before writing the destination operand of the first instruction to the second data register. destination register number storage means for holding the number of the second data register during the decoding period of the instruction; a match detection circuit that detects a match with the number of the data register from which the source operand is fetched and outputs the match detection circuit; and an AND circuit that takes the AND of the -several output signal and the interrupt request signal. It is something that you have.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram showing the configuration of an embodiment of the present invention.

In FIG. 1, the interrupt control system of the present invention includes an instruction fetch means 1, an instruction decode means 2, an operand fetch means 3, an instruction execution means 4, an operand write means 5, a data register 6, and a source operando bus 10
, 11, destination operand bus 12, instruction bus 20, decode buses 21 to 23, source operand 30.31, and destination operand 32.
, an AND gate 7 , a test nation register number storage means 8 , and a -number output circuit 9 .

FIG. 2 is a pipeline time chart of the circuit shown in FIG. 1, and shows a case where interrupt processing is executed between instruction 1 and instruction 2.

In FIG. 2, CK is the system block. A
~E indicates pipeline processing constituting each instruction, A indicates instruction fetch processing, B indicates instruction decode processing, C indicates operand fetch processing, D indicates instruction execution processing, and E indicates operand write processing.

In addition, RI is an interrupt request signal, AI is an interrupt enable signal,
CI indicates an interrupt control signal. T indicates the timing at which the interrupt control signal CI becomes 1' and the process shifts to interrupt processing.

Next, the operation of this embodiment will be explained.

First, instruction pipeline processing will be explained with reference to FIG.

The instruction fetch means 1 fetches an instruction in one certain clock. In the next 120 steps, the instruction decoding means 2 inputs the instruction via the instruction bus 20 and completes the decoding.

The operand fetch means 3 reads out the source operand designated by the decode bus 21 from the data register 6 via the source operand buses 10 and 11 in the next half clock.

In the next one clock, the instruction execution means 4 executes the operation specified by the decode bus 22 on the source operands SOI and SO2 output from the operand fetch means 3, and transfers the execution result to the destination operand DO.
It is outputted to the operand write means 5 as a.

At the next half clock, the operand write means 5 writes back the test nation operand Do to the test nation register on the data register 6 specified by the decode bus 23 via the destination operand bus 12.

Next, processing when there is an interrupt request will be explained.

When the instruction decoding process of the instruction 2 is executed by the instruction decoding means 2, the instruction 2 is executed by the operand fetching means 3 and the instruction execution means 4, as shown in the pipeline timing of FIG. Processing is being carried out for each.

At this time, the destination register number storage means 8 is
It holds the destination register number decoded in the instruction decoding process of instruction 1.

The coincidence detection circuit 9 compares the source register number of the instruction 2 output from the SR instruction decoding means 2 and the destination register number DR of the instruction 1 output from the test nation register number storage means 8, and determines that they do not match. '1' is output as the interrupt permission signal AI.

The AND gate 7 outputs the interrupt request signal RI and the OC.
The logical product is output as the interrupt control signal CI at timing T in FIG.

In response to the interrupt control signal CI, the instruction execution means 4, the operand fetch means 5, the instruction decode means 2, which precedes the operand write processing of the instruction 1 in the operand write means 5.
All pipeline processing for instruction 2 and below in instruction fetch means 1 is stopped, and after the operand write processing for instruction 1 is completed, interrupt processing is executed.

Next, a second embodiment of the present invention will be described.

FIG. 3 is a block diagram showing a second embodiment of the present invention.

The difference from the first embodiment shown in FIG. 1 is that the instruction execution process is divided into two pipeline processes, and as shown in FIG. It is a matter of implementation.

In FIG. 3, the interrupt control system of the present embodiment includes an instruction fetch means 1, an instruction decode means 2, an operand fetch means 3, an operand write means 5, and a data register 6 similar to those of the first embodiment. and AND gate 7, two instruction execution means 13.14, instruction execution means decode bus 24, two destination register number storage means 15.16, and two coincidence detection circuits 17.18. , two 1-clock delay circuits 19.26, and AN
D gate 27.

FIG. 4 is a pipeline time chart of the circuit shown in FIG. 3, and shows a case where interrupt processing is executed between instructions 2 and 3.

The difference between FIG. 4 and FIG. 2 is that the interrupt permission signal AI in FIG. Execution processing DI
, D2.

Next, the operation of this embodiment will be explained.

First, instruction pipeline processing will be explained with reference to FIG.

The processing for three clocks from instruction fetch to operand fetch 4 is the same as in the first embodiment described above.

At the next one clock, the instruction execution means 13
2 is executed on the source operands SO1 and SO2 output from the operand fetch means 3, and an intermediate result MI is output.

At the next one clock, the instruction execution means 14 executes the operation specified by the decode bus 24 on the intermediate result M1, and outputs the execution result to the operand write means 5 as the destination operand DO.

In the next half clock, the operand write means 5 writes the destination operand bus 1 to the destination register on the data register 6 specified by the decode bus 23.
Write back the destination operand DO via 2.

Next, processing when there is an interrupt request will be explained.

When the instruction decoding means 2 is executing the instruction decoding process for the instruction 3, the destination register number storage means 15 stores the destination register number of the instruction 2, and the destination register number storage means 16
hold the destination register number of instruction 1, respectively.

- The multiple pressure circuit 17 receives the source register number SR of the instruction 3 outputted from the instruction decoding means 2, the destination register number D of the instruction 1 and the instruction 2 outputted from the destination register number storage means 15 and 16, respectively.
Compare RI and DR2', and since they do not match, it is "1'"
are output to one-clock delay circuits 19 and 26, respectively.

When configuring the pipeline A to E in FIG. 4, it is further necessary to compare the source register number of instruction 4 and the destination register number of instruction 2.

When the instruction decoding means 2 is decoding the instruction 4 in the next clock, the destination register number storage means 15 stores the destination register number of the instruction 3. The means 16 each hold the destination register number of the instruction 2.

The coincidence detection circuit 18 compares the source register number SR of the instruction 4 and the destination register number DR2 of the instruction 2, and since they do not match, it sets 1' to the third interrupt permission signal AI3.
Output as . In this embodiment, the interrupt enable signal AIL~
Since interrupts are permitted only when AI3 is all 1', an AND gate 27 outputs an AND signal AI.

Interrupt request signal RI and interrupt permission signal AI in FIG. 4 are ANDed.
The gate 7 performs an AND operation, and the output thereof, the interrupt control signal CI, is outputted at timing T in FIG.

The interrupt control signal CI causes the instruction execution means 13 and 14, the operand fetch means 3, the instruction decode means 2, and the pipe after the instruction 3 in the instruction fetch means 1 to be activated before the operand write processing of the instruction 2 by the operand write means 5. All line processing is stopped, and after the operand write processing of instruction 2 is completed, interrupt processing is performed.

〔Effect of the invention〕

As explained above, according to the present invention, by controlling the execution timing of interrupt processing that occurs during pipeline processing, it is possible to avoid conflicts in source operand values after returning from interrupt processing. .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is an operation time chart of the circuit shown in FIG. 1, FIG. 3 is a block diagram showing a second embodiment of the present invention, and FIG. The figure is an operation time chart of the circuit shown in FIG. 3. 1... Instruction fetching means, 2... Instruction decoding means, 3... Operand fetching means, 4, 13.14.
... Instruction execution means, 5... Operand write means, 6
...Data register, 7,27...AND gate,
8.15. -16...Test nation register number storage means, 9, 17.18...-Number configuration circuit, 10.
DESCRIPTION OF SYMBOLS 11... Source operand bus, 12... Destination operand bus, 19.26... 1 clock delay circuit, 20... Instruction bus, 21-24... Decode bus.

Claims (1)

[Scope of Claims] Instruction fetching means for fetching an instruction; instruction decoding means for decoding the fetched instruction and outputting a decoded instruction; first and second data registers storing operand data; operand fetch means for fetching a source operand from the first data register specified by the decode instruction; instruction execution means for executing an operation specified by the decode instruction on the source operand to obtain a destination operand; operand write means for fetching a destination operand and writing it to the second data register specified by the decode instruction, and a pipeline processing system for processing the instructions in a predetermined order by pipeline processing. a second instruction fetched after the first instruction and fetching the source operand before writing the destination operand of the first instruction to the second data register; destination register number storage means for holding the number of the second data register during a period; and fetching the number of the second data register and the source operand of the second instruction specified by the instruction decoding means. The interrupter is characterized in that it has a coincidence detection circuit that detects a coincidence with the number of the data register and outputs a coincidence detection signal, and an AND circuit that takes an AND of the coincidence detection signal and an interrupt request signal. Inclusive control method.