JPH04127596A - Manufacture of high frequency wiring board - Google Patents
Manufacture of high frequency wiring boardInfo
- Publication number
- JPH04127596A JPH04127596A JP24919690A JP24919690A JPH04127596A JP H04127596 A JPH04127596 A JP H04127596A JP 24919690 A JP24919690 A JP 24919690A JP 24919690 A JP24919690 A JP 24919690A JP H04127596 A JPH04127596 A JP H04127596A
- Authority
- JP
- Japan
- Prior art keywords
- film
- wiring
- base film
- dielectric
- base
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004519 manufacturing process Methods 0.000 title claims description 18
- 239000004020 conductor Substances 0.000 claims abstract description 27
- 238000000034 method Methods 0.000 claims abstract description 25
- 238000004381 surface treatment Methods 0.000 claims abstract description 10
- 239000000758 substrate Substances 0.000 claims abstract description 9
- 238000007772 electroless plating Methods 0.000 claims description 5
- 239000010936 titanium Substances 0.000 abstract description 3
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 abstract description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 abstract description 2
- 229910052719 titanium Inorganic materials 0.000 abstract description 2
- 239000010949 copper Substances 0.000 description 7
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 6
- 229910052802 copper Inorganic materials 0.000 description 6
- 239000003054 catalyst Substances 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000010586 diagram Methods 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 238000005498 polishing Methods 0.000 description 3
- 239000011347 resin Substances 0.000 description 3
- 229920005989 resin Polymers 0.000 description 3
- 239000011651 chromium Substances 0.000 description 2
- 238000000151 deposition Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000009719 polyimide resin Substances 0.000 description 2
- 229920001343 polytetrafluoroethylene Polymers 0.000 description 2
- 239000004810 polytetrafluoroethylene Substances 0.000 description 2
- 229910052804 chromium Inorganic materials 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000009832 plasma treatment Methods 0.000 description 1
- -1 polytetrafluoroethylene Polymers 0.000 description 1
- 238000007788 roughening Methods 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000001771 vacuum deposition Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Manufacturing Of Printed Wiring (AREA)
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は、高密度配線を有する高周波配線用基板の製造
方法に関するものである。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a method of manufacturing a high frequency wiring board having high density wiring.
〈従来の技術〉
高周波用配線基板の製造は、第2図(i)ないしく i
v )の製造工程図に示す方法で行われていた。<Prior art> The production of high frequency wiring boards is as shown in Figure 2 (i) or i.
v) was carried out by the method shown in the manufacturing process diagram.
この製造方法は、第2図(i)に示す如く、基板31上
にパラジウム(Pd)等の触媒32を付与し、さらにレ
ジスト膜33を形成して、ホトリソグラフィー技術とエ
ツチング技術とにより後述する導体配線を形成する部分
のレジスト膜33を除去する。前記触媒32の付与は、
触媒32で導体膜が形成されない程度に、蒸着法または
湿式法によって行う。As shown in FIG. 2(i), this manufacturing method involves applying a catalyst 32 such as palladium (Pd) on a substrate 31, further forming a resist film 33, and using photolithography and etching techniques as described later. The resist film 33 in the portion where the conductor wiring is to be formed is removed. The application of the catalyst 32 includes:
A vapor deposition method or a wet method is used to the extent that a conductive film is not formed with the catalyst 32.
次に、第2図(ii )に示す如く、レジスト膜33を
除去した部分に無電解銅メッキ法により無電解銅を堆積
させた導体配線34を形成する。Next, as shown in FIG. 2(ii), a conductor wiring 34 is formed by depositing electroless copper on the portion from which the resist film 33 has been removed by electroless copper plating.
続いて、レジスト膜33を除去して、第2図(iii
)に示すように、ポリイミド樹脂の中間誘電体膜35で
前記配線導体34を覆う。Subsequently, the resist film 33 is removed, and as shown in FIG.
), the wiring conductor 34 is covered with an intermediate dielectric film 35 made of polyimide resin.
続いて、第2図(iv )に示す如く、配線導体34の
表面が露出するまで中間誘電体膜35の表面を機械的に
研磨する。そして、第1層の配線が終了する。Subsequently, as shown in FIG. 2(iv), the surface of the intermediate dielectric film 35 is mechanically polished until the surface of the wiring conductor 34 is exposed. Then, the first layer wiring is completed.
さらに、多層配線を行う場合には、第1層の配線が終了
した基板を前記基板31として、上記工程を繰り返す。Further, when performing multilayer wiring, the above steps are repeated using the substrate 31 on which the first layer wiring has been completed.
〈発明が解決しようとする課題〉
しかしながら、上記製造方法によって、信号の伝播速度
を向上させるために中間誘電体膜をポリテトラフルオロ
エチレン(PTFE) 等のフッ素樹脂で形成した場合
には、フッ素樹脂表面に接着性がないことにより触媒の
密着性が極めて悪くなる。このため、フッ素樹脂表面に
導体配線を形成することが困難なので、中間誘電体膜に
フッ素樹脂を用いることが不可能になる。この結果、中
間誘電体膜が十分に小さい誘電率を有する材料で形成で
きなくなり、高周波信号の伝播速度の向上が図れない。<Problems to be Solved by the Invention> However, when the intermediate dielectric film is formed of a fluororesin such as polytetrafluoroethylene (PTFE) using the above manufacturing method in order to improve the signal propagation speed, the fluororesin Due to the lack of adhesiveness on the surface, the adhesion of the catalyst becomes extremely poor. For this reason, it is difficult to form conductor wiring on the surface of the fluororesin, making it impossible to use the fluororesin for the intermediate dielectric film. As a result, the intermediate dielectric film cannot be formed of a material having a sufficiently small dielectric constant, and the propagation speed of high-frequency signals cannot be improved.
また、機械的な研磨によって、導体配線を中間誘電体膜
中まり露出させるために、製造工程が複雑になる。In addition, mechanical polishing exposes the conductor wiring within the intermediate dielectric film, which complicates the manufacturing process.
本発明は、上記課題を解決するために成されたもので、
製造が容易で、高周波信号の伝播速度に優れた高周波用
配線基板の製造方法を提供することを目的とする。The present invention was made to solve the above problems, and
It is an object of the present invention to provide a method for manufacturing a high frequency wiring board that is easy to manufacture and has an excellent propagation speed of high frequency signals.
く課題を解決するための手段〉
本発明は、上記目的を達成するために成されたものであ
る。Means for Solving the Problems> The present invention has been accomplished in order to achieve the above objects.
すなわち、基板上に誘電体下地膜を形成して、さらに形
成した誘電体下地膜の表面処理を行って導体下地膜の接
着性を向上させ、その後誘電体下地膜上に導体下地膜を
形成する0次に導体下地膜で配線下地パターンを形成す
る。続いて配線下地パターン側の全面に中間誘電体膜を
形成した後、中間誘電体膜の表面処理を行って導体下地
膜の接着性を向上させる。その後配線下地パターン上の
中間誘電体膜を除去して、無電解メッキ法により、中間
誘電体膜を除去した部分に導体配線を形成する製造方法
である。That is, a dielectric base film is formed on a substrate, the formed dielectric base film is further subjected to surface treatment to improve the adhesion of the conductive base film, and then a conductive base film is formed on the dielectric base film. Next, a wiring base pattern is formed using a conductor base film. Subsequently, an intermediate dielectric film is formed on the entire surface of the wiring underlying pattern, and then surface treatment is performed on the intermediate dielectric film to improve the adhesion of the conductive underlying film. This is a manufacturing method in which the intermediate dielectric film on the wiring base pattern is then removed, and conductive wiring is formed in the portion where the intermediate dielectric film has been removed by electroless plating.
〈作用〉
上記した高周波用配線基板の製造方法では、表面処理を
行った誘電体下地膜上に真空成膜法を用いて導体下地膜
を形成したことにより、誘電体下地膜の表面の接着性が
向上するので、誘電体下地膜は低誘電率の材料で形成さ
れる。また、導体下地膜で配線下地パターンを形成し、
その後配線下地パターン側に中間誘電体膜を形成してか
ら中間誘電体膜の表面処理を行うことにより、中間誘電
体膜の表面の接着性が向上するので、中間誘電体膜も低
誘電率の材料で形成される。この結果、中間誘電体膜は
低誘電率を有する材料で形成されるので、高周波信号の
伝播速度は高まる。<Function> In the above-described method for manufacturing a high-frequency wiring board, a conductive base film is formed using a vacuum film forming method on a dielectric base film that has been surface-treated, thereby improving the adhesiveness of the surface of the dielectric base film. Therefore, the dielectric base film is formed of a material with a low dielectric constant. In addition, a wiring base pattern is formed using a conductive base film,
After that, by forming an intermediate dielectric film on the wiring base pattern side and then performing surface treatment on the intermediate dielectric film, the adhesion of the surface of the intermediate dielectric film is improved, so the intermediate dielectric film also has a low dielectric constant. formed of material. As a result, the intermediate dielectric film is formed of a material having a low dielectric constant, so that the propagation speed of high frequency signals is increased.
さらに配線下地パターン上の中間誘電体膜を除去し、そ
の後無電解メッキ法により導体配線を形成したことによ
り、導体配線の表面は平面に形成される。Further, by removing the intermediate dielectric film on the wiring base pattern and then forming the conductor wiring by electroless plating, the surface of the conductor wiring is formed to be flat.
〈実施例〉
本発明の実施例を第1図■ないし■に示す製造工程図に
より説明する。<Example> An example of the present invention will be explained with reference to manufacturing process diagrams shown in FIGS.
第1図■に示す如く、基板11上に誘電体下地膜12を
形成する。この誘電体下地膜12にはフッ素樹脂または
ポリイミド樹脂等の低誘電率を有する樹脂を用いる。ま
た、誘電体下地膜12の形成には、誘電体下地膜12に
なる樹脂を基板11上に塗布して熱硬化させる。または
誘電体下地膜12になる樹脂のフィルムを基板11に貼
り付ける。As shown in FIG. 1, a dielectric base film 12 is formed on a substrate 11. As shown in FIG. For this dielectric base film 12, a resin having a low dielectric constant, such as fluororesin or polyimide resin, is used. Further, to form the dielectric base film 12, a resin that will become the dielectric base film 12 is applied onto the substrate 11 and cured by heat. Alternatively, a resin film that will become the dielectric base film 12 is attached to the substrate 11.
その後、誘電体下地膜12の表面処理を行って、後述す
る導体下地膜の密着性を良くする。この表面処理の方法
には、エツチングによって表面を粗化する方法またはプ
ラズマ処理によって表面の化学的性質を変える方法があ
る。Thereafter, the dielectric base film 12 is surface-treated to improve the adhesion of the conductive base film, which will be described later. This surface treatment method includes a method of roughening the surface by etching or a method of changing the chemical properties of the surface by plasma treatment.
そして、真空成膜法によって、誘電体下地膜12上に無
電解銅メッキの触媒になる金属、例えば!M(Cu)の
導体下地膜13を形成する。真空成膜法には、真空蒸着
法またはスパッタ法等を用いる。また、誘電体下地膜1
2と導体下地膜13との密着性が良(ない場合には、誘
電体下地膜12上に誘電体下地膜12との密着性に優れ
た金属膜、例えばクロム(Cr)膜またはチタニウム(
Ti)膜を形成してから導体下地膜13を形成する。Then, by using a vacuum film forming method, a metal that becomes a catalyst for electroless copper plating is applied onto the dielectric base film 12, for example! A conductive base film 13 of M (Cu) is formed. For the vacuum film forming method, a vacuum evaporation method, a sputtering method, or the like is used. In addition, dielectric base film 1
2 and the conductive base film 13 (if not, a metal film with excellent adhesion to the dielectric base film 12, such as a chromium (Cr) film or a titanium (
After forming the Ti film, a conductive base film 13 is formed.
次に、導体下地膜13上にレジスト膜を形成する。その
後第1図■に示すように、ホトリソグラフィー技術によ
りレジスト膜でレジストパターン14を形成し、このレ
ジストパターン14をエツチングマスクにして導体下地
膜(13)のエツチングを行う。そして、配線下地パタ
ーン15を形成する。Next, a resist film is formed on the conductor base film 13. Thereafter, as shown in FIG. 1 (2), a resist pattern 14 is formed using a resist film by photolithography, and the conductive base film (13) is etched using this resist pattern 14 as an etching mask. Then, a wiring base pattern 15 is formed.
その後第1図■に示す如く、配線下地パターン15例の
全面に中間誘電体膜16を形成する。この中間誘電体膜
16は、前記下地誘電体膜12と同様の方法により形成
する。そして、この中間誘電体膜16の表面処理を前記
誘電体下地膜12の表面処理と同様の方法により行う。Thereafter, as shown in FIG. 1 (2), an intermediate dielectric film 16 is formed on the entire surface of the 15 wiring base patterns. This intermediate dielectric film 16 is formed by the same method as the base dielectric film 12. Then, the surface treatment of this intermediate dielectric film 16 is performed in the same manner as the surface treatment of the dielectric base film 12.
次に、中間誘電体膜16の表面にレジスト膜を形成し、
第1図■に示すように、ホトリソグラフィー技術により
配線下地パターン15上のレジスト膜を除去して、レジ
ストパターン17を形成する。その後、レジストパター
ン17をエツチングマスクにし、アンダーカットを防止
するために異方性エツチング技術を用いて、配線下地パ
ターン15上の中間誘電体膜16(2点鎖線部)を除去
する。Next, a resist film is formed on the surface of the intermediate dielectric film 16,
As shown in FIG. 1, the resist film on the wiring underlying pattern 15 is removed by photolithography to form a resist pattern 17. Thereafter, using the resist pattern 17 as an etching mask, the intermediate dielectric film 16 (double-dashed line) on the wiring base pattern 15 is removed using an anisotropic etching technique to prevent undercutting.
そして第1図■に示す如く、前記中間誘電体膜16を除
去した部分に、無電解銅メッキ法により配線下地パター
ン15上に銅を析出させて導体配線1−8を形成する。Then, as shown in FIG. 1, copper is deposited on the wiring base pattern 15 by electroless copper plating in the area where the intermediate dielectric film 16 has been removed, thereby forming the conductor wiring 1-8.
この析出表面は平面になり、銅の析出は中間誘電体膜1
6の表面と同一平面を形成する高さまで行う。This deposition surface becomes a flat surface, and the copper is deposited on the intermediate dielectric film 1.
This is done to a height that forms the same plane as the surface of 6.
このように、無電解メッキ法によって導体配線18の表
面は平面に形成されるので、従来の製造方法のように機
械的な研磨によって導体配線18の上面を中間誘電体膜
16より露出させる工程を行う必要がない。As described above, since the surface of the conductor wiring 18 is formed flat by the electroless plating method, the step of exposing the upper surface of the conductor wiring 18 from the intermediate dielectric film 16 by mechanical polishing as in the conventional manufacturing method is not necessary. There's no need to do it.
以上のようにして、基板11上に第1層目の配線が形成
される。In the manner described above, the first layer of wiring is formed on the substrate 11.
さらに多層配線を行う場合には、前記第1図■で説明し
た工程が終了した後に、中間誘電体膜16と導体配線1
8との上面に前述したと同様の導体下地膜を形成する。Furthermore, when performing multilayer wiring, after the process described in FIG.
A conductive base film similar to that described above is formed on the upper surface of 8.
そして、前記第1図■で説明した工程より前記第1図■
で説明した工程まで順に行うことにより、第2N目の配
線を形成する。Then, from the process explained in FIG. 1■, the process shown in FIG.
By sequentially performing the steps up to the steps described above, the 2N-th wiring is formed.
第3N目以降の配線を形成するには、第2J!目の配線
を形成した工程を繰り返せばよい。To form the 3Nth and subsequent wirings, the 2nd J! The process of forming the eye wiring may be repeated.
〈発明の効果〉
以上、説明したように本発明の製造方法によれば、表面
処理を行った誘電体下地股上に真空成膜法によって導体
下地膜を形成し、さらに、導体下地膜で配線下地パター
ンを形成し、その後配線下地パターン側に中間誘電体膜
を形成してから中間誘電体膜の表面処理を行ったので、
導体下地膜または中間誘電体膜と導体配線との接着性が
良くなる。この結果、導体下地膜と中間誘電体膜とは低
誘電率材料で形成できるので、高周波信号の伝播速度の
向上が図れる。<Effects of the Invention> As described above, according to the manufacturing method of the present invention, a conductive base film is formed on the surface-treated dielectric base layer by a vacuum film forming method, and the conductor base film is further used to form a wiring base film. The pattern was formed, and then the intermediate dielectric film was formed on the wiring base pattern side, and the surface of the intermediate dielectric film was then treated.
The adhesion between the conductor base film or intermediate dielectric film and the conductor wiring is improved. As a result, the conductive base film and the intermediate dielectric film can be formed of a low dielectric constant material, so that the propagation speed of high frequency signals can be improved.
また、無電解めっき法により導体配線を形成したので、
導体配線の上面が平面で形成されるために機械的研磨工
程が省略できる。この結果、配線基板の製造が容易にな
る。In addition, since the conductor wiring was formed by electroless plating,
Since the upper surface of the conductor wiring is formed flat, a mechanical polishing step can be omitted. As a result, manufacturing of the wiring board becomes easier.
第1図は、実施例の製造工程図、
第2図は、従来例の製造工程図である。
11・・・配線基板、 12・・・誘電体下地膜。
13・・・導体下地膜、 15・・・導体下地パター
ン。
16・・・中間誘電体膜、 18・・・導体配線。FIG. 1 is a manufacturing process diagram of an embodiment, and FIG. 2 is a manufacturing process diagram of a conventional example. 11... Wiring board, 12... Dielectric base film. 13... Conductor base film, 15... Conductor base pattern. 16... Intermediate dielectric film, 18... Conductor wiring.
Claims (1)
膜の表面処理を行い、続いて真空成膜法により前記誘電
体下地膜上に導体下地膜を形成する工程と、 前記導体下地膜で配線下地パターンを形成する工程と、 前記配線下地パターン側の全面に中間誘電体膜を形成し
、その後前記中間誘電体膜の表面処理を行う工程と、 前記配線下地パターン上の前記中間誘電体膜を除去する
工程と、 前記中間誘電体膜を除去した部分に無電解メッキ法によ
り導体配線を形成する工程とにより構成されたことを特
徴とする高周波用配線基板の製造方法。[Claims] A step of forming a dielectric base film on a substrate, then performing surface treatment on the dielectric base film, and then forming a conductive base film on the dielectric base film by a vacuum film forming method. forming a wiring base pattern using the conductive base film; forming an intermediate dielectric film on the entire surface of the wiring base pattern, and then subjecting the intermediate dielectric film to surface treatment; and forming the wiring base pattern. Manufacturing a high-frequency wiring board characterized by comprising: a step of removing the intermediate dielectric film above; and a step of forming conductor wiring by electroless plating on the portion from which the intermediate dielectric film has been removed. Method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24919690A JPH04127596A (en) | 1990-09-19 | 1990-09-19 | Manufacture of high frequency wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP24919690A JPH04127596A (en) | 1990-09-19 | 1990-09-19 | Manufacture of high frequency wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04127596A true JPH04127596A (en) | 1992-04-28 |
Family
ID=17189336
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP24919690A Pending JPH04127596A (en) | 1990-09-19 | 1990-09-19 | Manufacture of high frequency wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04127596A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002063814A (en) * | 2000-08-15 | 2002-02-28 | Nippon Shokubai Co Ltd | Printed circuit board for high-frequency |
| WO2025243971A1 (en) * | 2024-05-21 | 2025-11-27 | 株式会社 潤工社 | Wiring board, electronic device including wiring board, and method for manufacturing wiring board |
-
1990
- 1990-09-19 JP JP24919690A patent/JPH04127596A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002063814A (en) * | 2000-08-15 | 2002-02-28 | Nippon Shokubai Co Ltd | Printed circuit board for high-frequency |
| WO2025243971A1 (en) * | 2024-05-21 | 2025-11-27 | 株式会社 潤工社 | Wiring board, electronic device including wiring board, and method for manufacturing wiring board |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3935309B2 (en) | Wiring circuit board and manufacturing method thereof | |
| US6606792B1 (en) | Process to manufacturing tight tolerance embedded elements for printed circuit boards | |
| JPH05502138A (en) | Interconnects in multilayer wiring and methods of forming them | |
| JP3699334B2 (en) | Wiring circuit board manufacturing method and photomask | |
| JPH06302936A (en) | Formation of conductor pattern for glass substrate | |
| JP2005217250A (en) | Method for manufacturing suspension board with circuit | |
| JPH07273458A (en) | Manufacturing method of multilayer-wiring board | |
| JP2003078234A (en) | Printed wiring board and method of manufacturing the same | |
| JPS63293996A (en) | Manufacture of multilayer interconnection substrate | |
| JP2002076574A (en) | Printed board and manufacturing method therefor | |
| JP3259417B2 (en) | Method for producing thin metal layer pattern, film for pattern formation, and film capacitor | |
| JPH0563340A (en) | Manufacture of wiring board provided with functional element | |
| JPS5864616A (en) | Manufacture of thin film magnetic head | |
| JP2003008170A (en) | Method of manufacturing double-sided flexible circuit board | |
| JPH03173497A (en) | Multilayer wiring board and its manufacturing method | |
| JP2002076573A (en) | Printed board and manufacturing method therefor | |
| JP4252227B2 (en) | Manufacturing method of double-sided flexible circuit board | |
| JP4140757B2 (en) | Substrate manufacturing method | |
| JPH03203393A (en) | Manufacture of wiring board | |
| JPS6378552A (en) | Formation of throughhole | |
| JPH02187099A (en) | Multilayer interconnection substrate | |
| JPS6343396A (en) | Manufacture of wiring board | |
| JPS59147430A (en) | Formation of fine pattern | |
| JP2849163B2 (en) | Manufacturing method of electronic circuit board | |
| JPS6141445B2 (en) |