JPH0412761U

JPH0412761U -

Info

Publication number: JPH0412761U
Application number: JP5399290U
Authority: JP
Priority date: 1990-05-23
Filing date: 1990-05-23
Publication date: 1992-01-31

Description

[Brief explanation of the drawing]

第１図は本考案の映像表示装置のブロツク図、
第２図は論理和回路および映像出力回路の具体例
の回路図である。図中、１０は入力映像信号、１１はアナログ／
デジタル変換器、１２はデジタル信号処理回路、
１３はデジタル／アナログ変換器、１４はタイミ
ング回路、１５は同期分離および同期発振回路、
１６は水平および垂直同期信号、１７は制御信号
、１８は垂直帰線期間パルス、１９はブランキン
グパルス、２０は論理和回路、２１は映像信号処
理回路、２２は映像信号、２３は映像出力回路、
２４は受像管、２５〜２６および４１〜４２はダ
イオード、２７〜２９および４３はトランジスタ
、３０〜３６および４４〜４５は抵抗、３７は直
流電源である。 Figure 1 is a block diagram of the video display device of the present invention.
FIG. 2 is a circuit diagram of a specific example of the OR circuit and the video output circuit. In the figure, 10 is the input video signal, 11 is the analog/
a digital converter; 12 is a digital signal processing circuit;
13 is a digital/analog converter, 14 is a timing circuit, 15 is a synchronous separation and synchronous oscillation circuit,
16 is a horizontal and vertical synchronizing signal, 17 is a control signal, 18 is a vertical blanking period pulse, 19 is a blanking pulse, 20 is an OR circuit, 21 is a video signal processing circuit, 22 is a video signal, 23 is a video output circuit ,
24 is a picture tube, 25-26 and 41-42 are diodes, 27-29 and 43 are transistors, 30-36 and 44-45 are resistors, and 37 is a DC power supply.

Claims

[Claims for Utility Model Registration] (1) A circuit that digitizes and processes an input video signal, and outputs horizontal and vertical deflection pulses synchronized with a synchronization signal separated from the input video signal, and In a video display device equipped with a synchronization separation and oscillation circuit that outputs a blanking pulse that synchronizes with the synchronization signal and cuts off the video signal supplied to the picture tube during the vertical retrace period, the input of the digital signal processing circuit synchronizes with the synchronization signal. The output of the scanning line counter of the timing circuit that generates the output control signal is decoded, and the logical sum of the vertical retrace pulse of the period in which the output video signal is not superimposed and the blanking pulse is used as a video output to drive the picture tube. A vertical blanking circuit for a video display device, characterized in that the video signal applied to the circuit is cut off from the video signal output from the video output circuit during the duration of the OR output. (2) The vertical blanking period pulse width output by the timing circuit is set to be the vertical blanking period excluding the white balance adjustment period that the video signal processing circuit performs during the last two scanning line periods of the vertical blanking period. A vertical blanking circuit for a video display device according to claim (1).