JPH04127737A - Clock signal generating circuit - Google Patents

Abstract

PURPOSE:To output a correct output clock signal even when an input clock signal is interrupted by detecting the interruption of the clock signal, masking a reset signal to reset a frequency divider circuit according to the output and self-running the frequency divider circuit. CONSTITUTION:A frequency divider circuit 30 executes frequency division by repeating an operation to count the number of pulses to be inputted and to return to an initial state for continuing the count according to the reset signal from a reset signal generating circuit 40. When a clock interruption detecting circuit 50 detects the interruption of the clock signal in this state, a reset signal mask means 60 masks the reset signal, and a frequency divider circuit self- running means 30A generates a load signal synchronized with the reset signal and loads it to the frequency divider circuit 30. Thus, even when the clock signal is interrupted, the frequency divider circuit 30 is correctly operated, and the deviation of timing can be prevented from being generated.

Description

[Detailed Description of the Invention] [Summary] Regarding a clock signal generation circuit that reproduces a clock signal synchronized with a reference clock signal from a reference clock signal received from a main station, when an omission occurs in the input reference clock signal. but,
In order to provide a clock signal generation circuit that operates correctly, we have developed a clock detection circuit that detects a clock signal from an input signal, a phase-locked oscillator that oscillates in phase with the clock detection circuit, and a phase-locked oscillator that separates the output of the phase-locked oscillator. In a clock signal generation circuit consisting of a frequency divider circuit that rotates the clock and a reset signal generation circuit that generates a signal to reset the frequency divider circuit from the clock signal detected by the clock detection circuit, the clock signal is detected by the clock detection circuit. clock disconnection detection means for detecting disconnection of the clock; and clock disconnection detection means for masking the output of the reset signal generation circuit from the output of the clock disconnection detection means; A circuit self-propelled means is installed and constituted.

[Industrial application field]

The present invention relates to a clock signal generation circuit that reproduces a clock signal synchronized with a reference clock signal from a reference clock signal received from a main station.

In digital communication systems, a cesium atomic oscillator with high frequency stability installed at the main station
A clock signal of the same frequency is supplied to the digital private branch exchange, synchronous terminal equipment, etc. that make up the system to achieve synchronization and perform digital communication.

For example, a master station supplies a plurality of clock signals to a slave station using a bipolar code, and the slave station reproduces a plurality of clock signals from the bipolar code.

At this time, if a gap occurs in the reference clock signal f1, the output phase of the output clock signal f2 may be delayed.

There is a need for such a clock signal generation circuit that can correctly reproduce a clock signal even when a reference clock signal received from a transmission line is missing.

[Prior Art] FIG. 4 is a block diagram illustrating a conventional example, and FIG. 5 is a diagram illustrating delay of a clock signal in the conventional example.

In the conventional example shown in Figure 4, the main station transmits 64 Kbps and 8 Kb.
This is an example in which three types of signals of ps, 0.4 Kbps, and 7 signals are sent from a transmission line in bipolar codes.

The bipolar signal receiving circuit 11 receives the received 64Kbps
Three types of clock signals are separated from the bipolar signal.

That is, 64 Kbps is transmitted as a normal bipolar signal, 8 Kbps is identified based on the position where the violation signal occurs, and 0.4 Kbps is identified based on the signal that does not cause a violation at the 8 Kbps violation signal position. Generates three types of clock signals.

The phase-locked oscillator 20 is a 8Mbps synchronized to 8Kbps.
The frequency divider circuit 30 divides the 8Mbps into 64Kb.
ps, 8 Kbps and 0.4 Kbps clock signals.

A reset signal generated by the reset signal generating circuit 40 resets the frequency dividing circuit 30 at a specified timing, thereby performing a frequency dividing operation and generating a necessary clock signal.

[Problems to be Solved by the Invention] In the conventional example described above, when a gap occurs in the 64 Kbps clock signal, as shown in the diagram illustrating the delay of the clock signal in the conventional example in FIG. This causes a delay in the output clock signal.

■ Showing a 64Kbps clock signal, at the position of the dashed line,
This shows a state where one clock of the 64 Kbps clock signal is missing.

■ It is a 0.4 Kbps clock signal and indicates a signal with the correct phase.

■ Indicates a 0.4 Kbps clock signal with a delay, and one clock of the 64Kbps clock signal is missing, so the 0.4Kbps clock signal becomes the 64Kbps clock signal. Indicates a state delayed by one clock.

If such a lock delay occurs, problems such as data loss or noise superimposed on the audio signal may occur.

SUMMARY OF THE INVENTION An object of the present invention is to provide a clock signal generation circuit that operates correctly even when a clock signal in an input signal is missing.

[Means to solve the problem]

FIG. 1 shows a block diagram illustrating the invention in detail.

The principle block diagram of the present invention shown in FIG. 1 shows a clock signal generation circuit, 10 in the figure is a clock detection circuit that detects a clock signal from an input signal, and 20 oscillates in phase synchronization with the clock detection circuit 10. 30 is a frequency dividing circuit that divides the output of the phase synchronized oscillator 20, and 40 is a reset circuit that generates a signal to reset the frequency dividing circuit 30 from the clock signal detected by the clock detection circuit 10. This is a signal generation circuit 40.

Further, 50 is a clock interruption detection means for detecting an interruption of the clock signal detected by the clock detection circuit IO provided in the clock signal generation circuit, and 60 is a clock interruption detection means 50.
A reset signal masking means masks the output of the reset signal generation circuit 40 from the output of the reset signal generating circuit 40, and 30A is a frequency dividing circuit free running means that causes the frequency dividing circuit 30 to run freely when the reset signal is masked. This is a means to solve this problem by providing a means.

[For production]

The clock detection circuit 10 detects a clock signal from the signal received from the transmission line and inputs it to the phase synchronized oscillator 20.
Oscillates in synchronization with the clock signal detected by By dividing this output by a frequency dividing circuit 30, a clock signal of a predetermined frequency is output.

The frequency dividing circuit 30 performs frequency division by counting the number of input pulses, returning to the initial state in response to a cent signal from the reset signal generating circuit 40, and repeating the operation of continuing counting.

When the clock loss detection circuit 50 detects a missing clock signal in this state, the reset signal masking means 60 masks the reset signal, and the frequency dividing circuit self-running means 30
By generating a load signal synchronized with the reset signal using A and loading it into the frequency divider circuit 30, even when the clock signal is missing, the frequency divider circuit 30 can be operated correctly and timing deviations can be prevented. It becomes possible.

[Example] The gist of the present invention will be specifically explained below with reference to the example shown in FIGS. 2 and 3.

FIG. 2 is a block diagram explaining the present invention in detail, and FIG. 3 is a diagram explaining the clearing operation of the frequency divider circuit according to the embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

The embodiment of the present invention shown in FIG. 2 includes the same bipolar signal receiving circuit 11, phase synchronized oscillator 20, frequency dividing circuit 30, and reset signal generating circuit 40 as explained in the conventional example, and the clock disconnection circuit explained in FIG. As the detection means 10, 64
A clock disconnection detection circuit 51, a clear signal mask circuit 61 as a reset signal masking means 60, and a rotary signal generation circuit 3 as a frequency dividing circuit free-running means 30A.
This is an example configured from 0a.

FIG. 3 is a diagram explaining the clearing operation of the embodiment of the present invention, in which the frequency dividing circuit includes two 1/256 counters 31, 32, and a load signal generating circuit 30. Inverter 31 as a
In this example, the decoder 32B decodes the output of the 1/256 counter 32 and outputs a 0°4 Kbps clock signal.

The 1/256 counter 31 has a counter period controlled by a clear signal, and the 8
It divides Mbps and outputs a 64Kbps clock.

This 64 Kbps clock is divided by 1/256 counter 32 to output 8 Kbps clock, and this clock is decoded by decoder 32B to 0.4 K b
ps clock is output.

When the clock detection circuit 51 detects a clock disconnection at 64, the clear signal is masked, so a load signal is loaded into the 1/256 counter 31 using a rotary signal synchronized with the clear signal generated by the 1/256 counter 31. . At this time, the masking of the clear signal is canceled after two frames.

That is, the 1/256 counter 31 is connected to the reset signal generation circuit 4.
It is possible to operate with either a clear signal generated from 0 or a load signal generated from the 1/256 counter 31.

Since the 1/256 counter 32 decodes its own output and generates a load signal, there will be no timing deviation if the 1/256 counter 31 is operating normally.

With the above configuration, even if there is a gap in the clock 64, the clock signal 64 supplied from the clock signal generation circuit is
There is no delay in the clock at 4, the clock at 8, or the clock at 0.4.

〔Effect of the invention〕

According to the present invention as described above, by detecting the disconnection of the clock signal, masking the reset signal for resetting the frequency dividing circuit by its output, and causing the frequency dividing circuit to run freely,
It is possible to provide a clock generation circuit that outputs a correct output clock signal even if an input clock signal is missing.

[Brief explanation of drawings]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a block diagram explaining the present invention in detail, FIG. 3 is a diagram explaining the clearing operation of the frequency divider circuit according to the embodiment of the present invention, FIG. 4 is a block diagram for explaining the conventional example, and FIG. 5 is a diagram for explaining the delay of the clock signal in the conventional example. In the figure, 10 is a clock detection circuit, 11 is a bipolar signal receiving circuit, 20 is a phase synchronized oscillator, 30 is a frequency dividing circuit, 31.32 is a 1/256 counter, 30A is a frequency dividing circuit free-running means, and 30a is a load signal 31A is an inverter, 32A and 32B are decoders, 40 is a reset signal generation circuit, 50 is a clock loss detection means, 51 is a clock loss detection circuit 64, 60 is a reset signal mask means, 61 is a clear signal mask circuit, are shown respectively. FIG. 1 is a detailed block diagram explaining the present invention. A block diagram explaining the conventional example. FIG. 4 is a diagram explaining the delay of the clock signal in the conventional example.

Claims (1)

[Scope of Claims] A clock signal generation circuit that reproduces a clock signal synchronized with the reference clock signal from a reference clock signal received from a main station, the clock signal generation circuit comprising: a clock detection circuit (10) that detects the clock signal from an input signal; , a phase synchronized oscillator (20) that oscillates in phase synchronization with the clock detection circuit (10), a frequency dividing circuit (30) that frequency divides the output of the phase synchronized oscillator (20), and the clock detection circuit (10). ), the clock signal generation circuit includes a reset signal generation circuit (40) that generates a signal for resetting the frequency dividing circuit (30) from the clock signal detected by the clock detection circuit (10). clock interruption detection means (50) for detecting a clock interruption; reset signal masking means (60) for masking the output of the reset signal generation circuit (40) from the output of the clock interruption detection means (50); A clock signal generation circuit characterized in that a frequency dividing circuit free-running means (30A) is provided for causing the frequency dividing circuit (30) to run freely when masked.