JPH04130470U - semiconductor equipment - Google Patents
semiconductor equipmentInfo
- Publication number
- JPH04130470U JPH04130470U JP3560191U JP3560191U JPH04130470U JP H04130470 U JPH04130470 U JP H04130470U JP 3560191 U JP3560191 U JP 3560191U JP 3560191 U JP3560191 U JP 3560191U JP H04130470 U JPH04130470 U JP H04130470U
- Authority
- JP
- Japan
- Prior art keywords
- pwb
- semiconductor
- pwbs
- semiconductor element
- semiconductor elements
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Combinations Of Printed Boards (AREA)
- Wire Bonding (AREA)
Abstract
(57)【要約】
【構成】 半導体素子２が実装された２枚のＰＷＢ１，
１間を、半導体素子５が実装され、且つ、必要に応じて
上記２枚のＰＷＢ間の接続用配線が形成されたＴＣＰ４
を介して電気的・機械的に接続する。
【効果】 ＰＷＢ上に実装する半導体素子数を減少させ
ることができ、これによってＰＷＢの面積縮小を図るこ
とができる。したがって、半導体装置の小型化を達成す
ることができるものである。
(57) [Summary] [Configuration] Two PWBs 1 on which semiconductor elements 2 are mounted,
1, a TCP 4 on which a semiconductor element 5 is mounted, and where wiring for connection between the two PWBs is formed as necessary.
Connect electrically and mechanically via [Effect] The number of semiconductor elements mounted on the PWB can be reduced, thereby reducing the area of the PWB. Therefore, it is possible to achieve miniaturization of the semiconductor device.
Description
【０００１】0001
本考案は、半導体素子が実装された２枚のプリント配線基板（以下「ＰＷＢ」 という）間を電気的・機械的に接続して構成した半導体装置に関するものである 。 This invention uses two printed wiring boards (hereinafter referred to as "PWB") on which semiconductor elements are mounted. It relates to semiconductor devices configured by electrically and mechanically connecting .
【０００２】0002
従来、ＰＷＢとＰＷＢを接続する際には、ソケット、ＦＰＣ（フレキシブル 回路基板）、リード線等を使用していた。ＦＰＣを使用した場合の構成を図２に 示す。図に於いて、１は、半導体素子２が実装されたＰＷＢ、３は接続用のＦＰ Ｃである。 Conventionally, when connecting PWBs, sockets and FPCs (flexible circuit boards), lead wires, etc. Figure 2 shows the configuration when using FPC. show. In the figure, 1 is a PWB on which a semiconductor element 2 is mounted, and 3 is an FP for connection. It is C.
【０００３】0003
本考案の目的は、半導体装置の小型化にある。 The purpose of the present invention is to miniaturize a semiconductor device.
【０００４】0004
本考案の半導体装置は、半導体素子が実装された２枚のＰＷＢ間を、半導体素 子が実装され、且つ、必要に応じて上記２枚のＰＷＢ間の接続用配線が形成され たテープキャリアパッケージを介して接続する構成としたことを特徴とするもの である。 The semiconductor device of the present invention connects the semiconductor element between two PWBs on which the semiconductor element is mounted. The child is mounted, and wiring for connection between the two PWBs is formed as necessary. The device is characterized in that it is configured to be connected via a tape carrier package. It is.
【０００５】[0005]
ＰＷＢ上に実装する半導体素子数を減少させることができ、これによってＰＷ Ｂの面積縮小を図ることができる。 The number of semiconductor elements mounted on the PWB can be reduced. The area of B can be reduced.
【０００６】[0006]
以下、実施例に基づいて本考案を詳細に説明する。 Hereinafter, the present invention will be described in detail based on examples.
【０００７】 図１は、本考案の一実施例の構成図である。[0007] FIG. 1 is a block diagram of an embodiment of the present invention.
【０００８】 図に於いて、１は、半導体素子２が実装されたＰＷＢ、４は、半導体素子５が 実装され、且つ、必要に応じて上記２枚のＰＷＢ１，１間の接続用配線が形成さ れたテープキャリアパッケージ（ＴＣＰ）であり、該ＴＣＰ４を介して２枚のＰ ＷＢ１，１間が電気的・機械的に接続された構成となっている。ＴＣＰの利点と して、ある程度自由に曲げることができるために、ＦＰＣやリード線と比べて接 続上問題はない。[0008] In the figure, 1 is a PWB on which a semiconductor element 2 is mounted, and 4 is a PWB on which a semiconductor element 5 is mounted. mounted, and wiring for connection between the two PWBs 1 and 1 is formed as necessary. It is a tape carrier package (TCP) with two P The configuration is such that the WBs 1 and 1 are electrically and mechanically connected. Advantages of TCP and Because it can be bent to a certain degree freely, it is easier to connect than FPC or lead wires. There is no problem in continuing.
【０００９】[0009]
以上詳細に説明したように、本考案によれば、ＰＷＢの縮小を図ることができ 、これによって半導体装置の小型化を達成することができるものである。 As explained in detail above, according to the present invention, it is possible to reduce the PWB. , thereby making it possible to downsize the semiconductor device.
【図１】本考案の一実施例の構成図である。FIG. 1 is a configuration diagram of an embodiment of the present invention.
【図２】従来の半導体装置の構成図である。FIG. 2 is a configuration diagram of a conventional semiconductor device.
１ ＰＷＢ ２ 半導体素子 ３ ＦＰＣ ４ ＴＣＰ ５ 半導体素子 1 PWB 2 Semiconductor element 3 FPC 4 TCP 5 Semiconductor element
Claims (1)
配線基板間を、半導体素子が実装されたテープキャリア
パッケージを介して接続する構成としたことを特徴とす
る半導体装置。1. A semiconductor device characterized in that two printed wiring boards on which semiconductor elements are mounted are connected via a tape carrier package on which semiconductor elements are mounted.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3560191U JPH04130470U (en) | 1991-05-21 | 1991-05-21 | semiconductor equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3560191U JPH04130470U (en) | 1991-05-21 | 1991-05-21 | semiconductor equipment |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04130470U true JPH04130470U (en) | 1992-11-30 |
Family
ID=31917717
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3560191U Pending JPH04130470U (en) | 1991-05-21 | 1991-05-21 | semiconductor equipment |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04130470U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1995008189A1 (en) * | 1993-09-14 | 1995-03-23 | Kabushiki Kaisha Toshiba | Multi-chip module |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5630718A (en) * | 1979-08-22 | 1981-03-27 | Kck Co Ltd | Method of manufacturing porcelain condenser |
| JPS6095091A (en) * | 1983-05-19 | 1985-05-28 | 株式会社ニチベイ | Remote controller of electromotive blind |
-
1991
- 1991-05-21 JP JP3560191U patent/JPH04130470U/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5630718A (en) * | 1979-08-22 | 1981-03-27 | Kck Co Ltd | Method of manufacturing porcelain condenser |
| JPS6095091A (en) * | 1983-05-19 | 1985-05-28 | 株式会社ニチベイ | Remote controller of electromotive blind |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1995008189A1 (en) * | 1993-09-14 | 1995-03-23 | Kabushiki Kaisha Toshiba | Multi-chip module |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JPH04130470U (en) | semiconductor equipment | |
| JPS6077264U (en) | motor actuator | |
| JPH0611524Y2 (en) | Connection structure between circuit board and mother circuit board | |
| JPS605085U (en) | connector | |
| JPS6027468U (en) | Printed circuit board connection device | |
| JPS6078172U (en) | Flexible board connection structure | |
| JPS5856471U (en) | Chip parts mounting device | |
| JPH0534690U (en) | Board connection device | |
| JPH0453179A (en) | Flexible printed board and manufacture thereof | |
| JPS58131635U (en) | Hybrid integrated circuit device | |
| JPS59170978U (en) | Lead wire connection device with incorrect wiring prevention | |
| JPS5877074U (en) | circuit board connection device | |
| JPS6022764U (en) | Connector for printed circuit board mounting | |
| JPS63314857A (en) | printed circuit board flexible board | |
| JPS6361177U (en) | ||
| JPH0672244U (en) | Electronic circuit device | |
| JPS58155788U (en) | Terminal structure of electronic equipment | |
| JPS5944030U (en) | Chip-shaped electronic components | |
| JPH04133359U (en) | Flexible connector for automatic mounting | |
| JPS5820573U (en) | electronic equipment | |
| JPS5827947U (en) | Hybrid integrated circuit device | |
| JPS6180780A (en) | Printed circuit board connection device | |
| JPS5925484U (en) | Electronic component mounted card inspection jig | |
| JPS6254494A (en) | Package of circuit part | |
| JPS59159877U (en) | Printed wiring board connector |