JPH04130809A - Parallel amplifier circuit - Google Patents
Parallel amplifier circuitInfo
- Publication number
- JPH04130809A JPH04130809A JP2252615A JP25261590A JPH04130809A JP H04130809 A JPH04130809 A JP H04130809A JP 2252615 A JP2252615 A JP 2252615A JP 25261590 A JP25261590 A JP 25261590A JP H04130809 A JPH04130809 A JP H04130809A
- Authority
- JP
- Japan
- Prior art keywords
- amplifiers
- voltage
- output
- outputs
- amplifier
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000005856 abnormality Effects 0.000 claims abstract description 9
- 238000001514 detection method Methods 0.000 claims description 8
- 230000002159 abnormal effect Effects 0.000 description 7
- 238000010586 diagram Methods 0.000 description 4
- 238000004891 communication Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 230000003321 amplification Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
Landscapes
- Amplifiers (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は並列増幅回路に関し、特にマイクロ波通信装置
に用いられ、異常検出機能を有する並列増幅回路に関す
る。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a parallel amplifier circuit, and more particularly to a parallel amplifier circuit that is used in a microwave communication device and has an abnormality detection function.
従来、マイクロ波無線通信回線において、複数の搬送波
信号を分波器にて合成して送信し、受信側では各搬送波
信号に分離する分波器の前に共通の低雑音増幅器を設け
て雑音指数を改善している。この低雑音増幅器は受信信
号を２分岐して２つの増幅器で並列増幅した後に、出力
信号を合成器で合成している。したがって、片側の低雑
音増幅器が障害となっても回線が断とならないように、
もう一つの増幅器を備えている。したがって異常時には
２つの並列増幅回路の合成出力レベルが約６ｄｂ低下の
出力レベルとなっていた。Conventionally, in microwave wireless communication lines, multiple carrier signals are combined using a demultiplexer and transmitted, and on the receiving side, a common low-noise amplifier is installed in front of the demultiplexer that separates each carrier signal to improve the noise figure. are improving. This low-noise amplifier branches a received signal into two, amplifies them in parallel with two amplifiers, and then combines the output signals with a combiner. Therefore, even if the low noise amplifier on one side becomes a problem, the line will not be disconnected.
It has another amplifier. Therefore, in the event of an abnormality, the combined output level of the two parallel amplifier circuits was reduced by about 6 db.
しかしながら上述した従来の並列増幅回路は、受信され
る入力信号レベルが、伝搬特性の変動により、大きく変
化するので、二つの増幅器の合成出力レベルで正常、異
常の検出を判定するのは困難である。したがって全く監
視しないか、又は各増幅デバイスのバイアスのみの監視
程度した行っておらず、したがって個別の増幅器単独で
障害を検出できない欠点があった。However, in the conventional parallel amplifier circuit described above, the level of the received input signal changes greatly due to fluctuations in the propagation characteristics, so it is difficult to determine whether the detection is normal or abnormal based on the combined output level of the two amplifiers. . Therefore, there is no monitoring at all, or only the bias of each amplification device is monitored, and therefore there is a drawback that failures cannot be detected in individual amplifiers alone.
本発明の並列増幅回路は、入力信号を２つに分配する分
配器と、２分配されたそれぞれの信号を増幅する２つの
増幅器と、前記２つの増幅器の出力信号を合成する合成
器とを有する並列増幅回路において、前記２つの増幅器
の出力部に接続されそれぞれの出力信号を検出する２つ
の検波器と、それぞれの検波器出力を入力し、この差電
圧に対応する差動電圧を出力する差動増幅器と、所定の
しきい値の基準電圧より高くなったことを検出するため
の第１の電圧比較器と、所定のしきい値の基準電圧より
低くなったことを検出するための第２の電圧比較器とを
有する。The parallel amplifier circuit of the present invention includes a divider that divides an input signal into two, two amplifiers that amplify each of the divided signals, and a combiner that combines the output signals of the two amplifiers. In a parallel amplifier circuit, there are two detectors connected to the output parts of the two amplifiers to detect their respective output signals, and a differential circuit that inputs the outputs of the respective detectors and outputs a differential voltage corresponding to the differential voltage. a dynamic amplifier, a first voltage comparator for detecting that the reference voltage has become higher than a predetermined threshold value, and a second voltage comparator for detecting that the reference voltage has become lower than a predetermined threshold value. voltage comparator.
次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図は本発明の一実施例のブロック図、第２図および
第３図は、本実施例の動作説明図である。第１図におい
て、入力信号は分配器１で２分岐され、それぞれ増幅器
２，３で増幅される。FIG. 1 is a block diagram of an embodiment of the present invention, and FIGS. 2 and 3 are explanatory diagrams of the operation of this embodiment. In FIG. 1, an input signal is split into two by a divider 1 and amplified by amplifiers 2 and 3, respectively.
この２つの増幅信号は合成器４にて合成され、出力端か
ら出力される。本発明の実施例では増幅器２，３の出力
端に検波器５，６が接続されている。第２図はこれらの
検波特性の例を示しているが、第２図かられかるように
、入力レベルが高い場合は検波出力が大きいが、入力レ
ベルが低い場合は検波出力が低いか、もしくは全く変化
しなくなり、出力レベルの大きさは判定できなくなる。These two amplified signals are combined by a combiner 4 and output from the output terminal. In the embodiment of the present invention, detectors 5 and 6 are connected to the output ends of the amplifiers 2 and 3. Figure 2 shows an example of these detection characteristics.As can be seen from Figure 2, when the input level is high, the detection output is large, but when the input level is low, the detection output is low or There is no change at all, and the magnitude of the output level cannot be determined.
通常のマイクロ波通信においては入力レベルは大幅に変
化し、低入力レベル時には、出力レベルの大きさは判定
できなくなる。従ってこの時は増幅器が異常か伝搬状態
が悪いのかの判定は不可能となる。In normal microwave communication, the input level changes significantly, and when the input level is low, the magnitude of the output level cannot be determined. Therefore, at this time, it is impossible to determine whether the amplifier is abnormal or the propagation condition is poor.
受信入力が正常時には、同じ設計の増幅器はほぼ同じレ
ベルを出力するので、検波器５，６の出力を、差動増幅
器７に入力すると、２個の増幅器出力の差の有無がわか
る。差動増幅器７の入出力特性は第３図に示すように、
横軸の差動入力が原点から右側又は左側に大きくなるに
つれて、増幅器２，３の出力レベルに対応する差動増幅
器７の出力電圧が縦軸に示す値で示される。実際には検
波特性にバラツキがあるため、この出力電圧がＯＶでな
くても必ずしも２個の増幅器の出力レベルに差があると
は限らない。またある程度の出力レベル誤差は許容され
る。これらの幅を考慮して、２つのスレシｄ−ルド電圧
Ｖ８と−Ｖ２とを定め、これを２つの電圧比較器８，９
に入力し、一方ではＶ、より高いことを検出することに
より、増幅器２の異常を知り、−Ｖ２より低いことを検
出することにより、増幅器３の異常を知ることができる
。また、ｖｌと−７２間にあることを検出することによ
り、両方が正常であることを知ることができる。When the reception input is normal, amplifiers of the same design output approximately the same level, so by inputting the outputs of the detectors 5 and 6 to the differential amplifier 7, it is possible to determine whether there is a difference between the outputs of the two amplifiers. The input/output characteristics of the differential amplifier 7 are as shown in FIG.
As the differential input on the horizontal axis increases to the right or left from the origin, the output voltage of the differential amplifier 7 corresponding to the output level of the amplifiers 2 and 3 is indicated by the value shown on the vertical axis. In reality, since there are variations in the detection characteristics, even if this output voltage is not OV, there is not necessarily a difference in the output levels of the two amplifiers. Also, a certain amount of output level error is allowed. Taking these widths into consideration, two threshold voltages V8 and -V2 are determined, and these are applied to the two voltage comparators 8 and 9.
On the other hand, by detecting that the voltage is higher than V2, it is possible to know whether there is an abnormality in the amplifier 2, and by detecting that the voltage is lower than -V2, it is possible to know whether the amplifier 3 is abnormal. Further, by detecting that the value is between vl and -72, it can be known that both are normal.
信号の入力レベルが相当に低い場合には、検波器出力に
出力されず片方の増幅器の異常検出が不可能となる。し
かし、受信入力レベルは長時間連続で低下していること
は、まれなので、この時間のみ正常を示していても問題
は無い。受信入力レベルが高くなれば、ただちに異常が
正常かの判定がなされる。また、電圧比較器８，９の出
力に異常状態のラッチ回路を付加すれば、異常状態を検
出した時点で、その異常検出を保持できる。If the input level of the signal is considerably low, it will not be output to the detector output, making it impossible to detect an abnormality in one of the amplifiers. However, since it is rare for the received input level to continue to drop for a long time, there is no problem even if it shows normality only during this time. When the received input level becomes high, it is immediately determined whether the abnormality is normal. Further, if an abnormal state latch circuit is added to the outputs of the voltage comparators 8 and 9, the abnormal state detection can be held at the time when an abnormal state is detected.
また、２個の増幅器を２個のＡＧＣ増幅器に置換し、そ
の２つのＡＧＣ制御電圧を差動増幅しても、同じ結果が
得られる。The same result can also be obtained by replacing the two amplifiers with two AGC amplifiers and differentially amplifying the two AGC control voltages.
［発明の効果〕
以上述べたように本発明は、並列増幅器のそれぞれの増
幅器の出力に設けた検波器の出力を差動増幅し、その出
力をしきい値を設けた電圧比較器にて電圧比較すること
により、この受信機のような入力レベルの変化の大きい
場合でも、それぞれ増幅器の正常、異常の検出ができる
効果がある。[Effects of the Invention] As described above, the present invention differentially amplifies the output of a detector provided at the output of each amplifier of a parallel amplifier, and converts the output into a voltage comparator with a threshold value. Comparison has the effect of detecting whether the amplifier is normal or abnormal, even in cases where the input level changes greatly, such as in this receiver.
第１図は本発明の一実施例のブロック図、第２図および
第３図は本実施例の動作説明図である。
１・・・分配器、２，３・・・増幅器、４・・・合成器
、５．６・・・検波器、７・・・差動増幅器、８，９・
・・電圧比較器。FIG. 1 is a block diagram of an embodiment of the present invention, and FIGS. 2 and 3 are diagrams illustrating the operation of this embodiment. DESCRIPTION OF SYMBOLS 1... Distributor, 2, 3... Amplifier, 4... Combiner, 5.6... Detector, 7... Differential amplifier, 8, 9...
...Voltage comparator.
Claims (1)
それぞれの信号を増幅する２つの増幅器と、前記２つの
増幅器の出力信号を合成する合成器とを有する並列増幅
回路において、前記２つの増幅器の出力部に接続されそ
れぞれの出力信号を検出する２つの検波器と、それぞれ
の検波器出力を入力し、この差電圧に対応する差動電圧
を出力する差動増幅器と、所定のしきい値の基準電圧よ
り高くなったことを検出するための第１の電圧比較器と
、所定のしきい値の基準電圧より低くなったことを検出
するための第２の電圧比較器とを有することを特徴とす
る並列増幅回路。 ２、前記２つの増幅器が入力信号の変化に対し出力レベ
ルを一定にするＡＧＣ増幅器であり、前記ＡＧＣ増幅器
のそれぞれのＡＧＣ制御信号出力を前記差動増幅器の２
つの入力とすることを特徴とする請求項１記載の並列増
幅回路。 ３、前記第１および第２の電圧比較器の出力にラッチ回
路を有し、異常検出信号を保持することを特徴とする請
求項１記載の並列増幅回路。[Claims] 1. It has a divider that divides an input signal into two, two amplifiers that amplify each of the two divided signals, and a combiner that combines the output signals of the two amplifiers. In a parallel amplifier circuit, there are two detectors connected to the output parts of the two amplifiers to detect their respective output signals, and a differential circuit that inputs the outputs of the respective detectors and outputs a differential voltage corresponding to the differential voltage. a dynamic amplifier, a first voltage comparator for detecting that the reference voltage has become higher than a predetermined threshold value, and a second voltage comparator for detecting that the reference voltage has become lower than a predetermined threshold value. A parallel amplifier circuit comprising a voltage comparator. 2. The two amplifiers are AGC amplifiers that keep the output level constant against changes in the input signal, and the AGC control signal output of each of the AGC amplifiers is connected to the two amplifiers of the differential amplifier.
2. The parallel amplifier circuit according to claim 1, wherein the parallel amplifier circuit has two inputs. 3. The parallel amplifier circuit according to claim 1, further comprising a latch circuit at the outputs of the first and second voltage comparators to hold an abnormality detection signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2252615A JPH04130809A (en) | 1990-09-21 | 1990-09-21 | Parallel amplifier circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2252615A JPH04130809A (en) | 1990-09-21 | 1990-09-21 | Parallel amplifier circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH04130809A true JPH04130809A (en) | 1992-05-01 |
Family
ID=17239832
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2252615A Pending JPH04130809A (en) | 1990-09-21 | 1990-09-21 | Parallel amplifier circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH04130809A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012049953A (en) * | 2010-08-30 | 2012-03-08 | Fujitsu Ltd | Signal amplification device and method |
| JP2024014166A (en) * | 2022-07-22 | 2024-02-01 | 株式会社日立国際電気 | Broadcast transmitter abnormality detection system |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4845113A (en) * | 1971-05-24 | 1973-06-28 | ||
| JPS59149409A (en) * | 1983-02-16 | 1984-08-27 | Nec Corp | Amplifying device |
-
1990
- 1990-09-21 JP JP2252615A patent/JPH04130809A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4845113A (en) * | 1971-05-24 | 1973-06-28 | ||
| JPS59149409A (en) * | 1983-02-16 | 1984-08-27 | Nec Corp | Amplifying device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2012049953A (en) * | 2010-08-30 | 2012-03-08 | Fujitsu Ltd | Signal amplification device and method |
| JP2024014166A (en) * | 2022-07-22 | 2024-02-01 | 株式会社日立国際電気 | Broadcast transmitter abnormality detection system |
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