JPH04137735A - Semiconductor device and its manufacturing method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a gate-drain overlap structure and a method of manufacturing the same.

(b) Conventional technology A recent report has reported that injection of hot carriers significantly deteriorates the characteristics of, for example, an LDD tM transistor.
”A 5elf Aligned Inverse
T Gate Fully 0verlappecl
LDD Device for Sub-Half
There is Micron CMO5'.

As shown in the second diagram, this transistor is a transistor whose gate has an inverted T shape (hereinafter referred to as an inverse transistor).As shown in diagram 0, the gate and drain are
Since they overlap, the drain electric field is relaxed,
It also has the effect of improving drain breakdown voltage and hot carrier resistance.

Further, an electric field is applied perpendicularly to the n- layer from the overlamp gate, the surface becomes n+, the resistance is lowered, and gl and channel current are increased compared to the LDD structure.

The manufacturing method is as shown in FIG.
A first polysilicon layer (12) of 0 and a thermal oxide film (13) of 40 are laminated.

Next, the second polysilicon (14) is
Form the gate with IE. Here, the thermal oxide film acts as a stopper during selective etching by RIE, and the remaining oxide film (13) is removed with HF6.Next, as shown in Figure 2B, for example, using a photoresist or gate as a mask, , ion-implanted phosphorus, low concentration source,
Drains (15) and (16) are formed.

Next, as shown in FIG.
8) is formed on the entire surface.

Finally, the insulating film (18) is etched to form a sidewall spacer shape, and as shown in FIG. Regions (19) and (20) are formed.

An inverse transistor is generally formed by the method described above.

(c) Problems to be solved by the invention First, the gate, gate oxide film, and
There is a problem in that a capacitance is formed in a low concentration source and a low concentration drain, resulting in a decrease in speed.

Further, as miniaturization progresses, it becomes necessary to make the insulating film under the gate electrode thinner, and tunnel current occurs particularly between the drain and the substrate, which is observed as leakage current.

(d) Means for Solving the Problems The present invention has been made in view of the above-mentioned problems. The second game H36)
The problem is solved by forming the bottom surface of the second gate (36) above the bottom surface of the first gate (35).

Also, a first gate insulating film (31) formed under the second gate (36), a first polysilicon (32) that substantially defines the thickness of the second gate (36), and a first gate projecting upward from the second gate (36);
The first insulating film (35) substantially defines the thickness of the first insulating film (35).
3) on the entire surface of the semiconductor substrate (3o), the first insulating film (33), the first polysilicon (32) and the first gate insulating film (31) corresponding to the gate;
The problem is solved by at least the steps of: forming brim-shaped recesses (34), (38) by etching; and filling the recesses (34), (38) with a conductive material constituting the gate. It is.

(E) Effect According to the present invention, by forming the bottom surface of the second gate (36) above the first gate (H35), the low concentration source (
41) The insulating film on the drain (42) can be formed thickly, and the capacitance generated thereby can be reduced.

Further, according to the present invention, the lower part of the second game (36) is connected to the first
The thickness of the lower first gate insulating film (31) decreases the electric field strength in the substrate near the 5lO2 and Si interface in the drain region. The tunnel current flowing between the substrates (30) can be reduced.

Furthermore, the first gate insulating film (31) formed below is set to a predetermined value, and the subsequent steps, that is, the recesses (34) and (38) In the step of forming the gate insulating film (31) by etching, the gate insulating film (31) corresponding to the first gate [35] is completely etched and a thin film is reattached, or the gate insulating film is slightly etched. By forming the film thickness to be thinner than the first gate insulating film, the gate insulating films (39) and (31) formed under the first gate and the second gate can have any value. Since it can be set, the reduction in capacitance and reduction in leakage current can be set to the most preferable value.

(F) EXAMPLE A method of manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings.

First, a P-type semiconductor substrate (30) is prepared, and a first gate insulating film (31) is formed to a thickness of about 500 by thermal oxidation.
), and then the first polysilicone/(32) is formed into L
It is formed to a thickness of approximately 600 mm using the PCVD method. Subsequently, oxidation is carried out at about 950°C in a diluted oxygen atmosphere.
About 100 8102 on the surface of polysilicon (32)
Forms a film.

Furthermore, arsenic As ions are applied at approximately 30 KeV, 1.0×10 ”
The polysilicon is implanted under cm-' conditions to set the polysilicon to a predetermined value.

Furthermore, a first insulating film (33) made of SiO2 is formed by approximately 4,000 layers (7) by the LPCVD method as shown in FIG. 1A.

Next, create a recess for embedding the gate as shown in the first diagram (
There is an etching process (34).

Here, the gate is the main thick first gate (35).
and a second gate (36) formed thinly into a brim shape.

First, a photoresist (37) is formed on the semiconductor substrate, and the photoresist corresponding to the first gate (35) is removed to form the semiconductor substrate as shown in FIG. 1B.

Subsequently, the first insulating film (33) is removed through this opening by complete anisotropic etching.

Furthermore, the first polysilicon (32) is etched by isotropic etching such as chemical dry etching to form a structure as shown in FIG. 1C.

In the former anisotropic etching, a first gate portion formed above the second gate is defined. In addition, due to the latter isotropic etching, a further concave portion (38
) is formed and a second gate portion is defined.

Subsequently, the first gate insulating film (31) is completely etched by anisotropic etching as shown in the first diagram.

Therefore, here, the surface of the semiconductor substrate (30) is exposed, and the second gate (35) is formed in a brim shape around the first gate (35).
(36) portion will be formed.

Thereafter, there is a step of removing the photoresist (37) and thermally oxidizing the semiconductor substrate (30) again to a thickness of about 150 nm. Therefore, the gate insulating film region under the first gate has a second gate insulating film (31) thinner than the first gate insulating film (31).
A gate insulating film (39) is formed. Also, a thermal oxide film is simultaneously formed on the exposed region of the first polysilicon (32) in the recess (38) formed in the horizontal direction.

Next, there is a step of embedding the second polysilicon (40) as shown in FIG. to make the surface uniform, and then etch back to make the surface flat as shown in Figure 1E.Furthermore, P
OCl, doped with phosphorus at about 900°C,
0Ω/mouth.

Further, the first insulating film (33) was removed by completely anisotropic etching, and phosphorus ions were etched at about 120 KeV and about 3. OX
10I3cm-” condition, the low concentration first
is implanted into the source (41) and drain regions (42).

Next, there is a step of forming a 5in2 sidewall spacer on the flange.

First, approximately 2,500 people were treated with 5i using the LPCVD method.
A ft film is formed on the entire surface, and the 5iOz film is etched by completely anisotropic etching to form sidewall spacers (43) as shown in FIG. 1F.

Furthermore, the first polysilicon (32) is etched to expose the first insulating film (33).

At this time, the upper surface of the first gate (35) made of the first polysilicon (32) is also etched, but in order to prevent this, an etching-resistant film may be formed on the upper surface.

Finally, as shown in Figure 1F, approximately 12 arsenic (As) ions are added to the
0KeV, 5. A second source (44) and a drain region (45) having a higher concentration than the first source (41) and drain region (42) are formed by implantation under the condition of OX 10"cm-", and then placed in a nitrogen gas atmosphere. Anneal at 900°C for 930 minutes.

Finally, although not shown on the drawing, there is a source.

Lead lines for the drain electrode and gate electrode are formed by a conventional method.

As can be seen from the figure, in the above series of manufacturing methods, the second
The first gate insulating film (31) under the first gate (36) is formed 6 times thicker than the second gate oxide film (39) under the first gate (35). In other words, the second gate (36)
The bottom surface of the first gate (35) is formed above the bottom surface of the first gate (35).

Furthermore, the first gate insulating film (31) and the second gate insulating film (39) can each be formed to have an arbitrary thickness using a two-layer manufacturing method.

Therefore, the oxide film of the present invention can be formed thicker than the oxide film of the gate and drain overlap portions in FIG.
43), the capacitance generated in the gate and oxide film can be reduced.

(G) Effects of the Invention As is clear from the above explanation, since the gate and drain overlap structure, it has a structure with excellent hot carrier resistance similar to the conventional inverse T transistor, and has a low concentration source. .

Capacitance generated in the drain, gate, and oxide film can be reduced.

Therefore, the speed of the transistor can be improved without impairing the characteristics of the conventional inverse T transistor.

In addition, by forming a first gate insulating film that is thicker than the second gate insulating film on the second gate electrode and its surrounding area, the electrolytic strength in the substrate near the interface between SiO□ and Si in the drain region is increased. As a result, the field strength is reduced, and the tunnel current flowing between the highly doped drain and the substrate can be reduced.

Furthermore, at one end, the first gate insulating film formed under the second gate is set to a predetermined value, and in the subsequent step, that is, the step of forming the recessed portion by etching, the first gate insulating film is etched to correspond to the first gate. By etching all the gate insulating films and reattaching a thin film, the gate insulating films formed under the first and second gates can be set as desired, thereby reducing capacitance and leakage. The current reduction can be set to the most preferable value.

[Brief explanation of the drawing]

1A to 1F are cross-sectional views illustrating a method of manufacturing a semiconductor device according to the present invention, and FIGS. 2A to 2E are sectional views illustrating a conventional method of manufacturing a semiconductor device. .

Claims (5)

[Claims] (1) A semiconductor device in which a gate is configured via a gate insulating film on a semiconductor substrate of one conductivity type, and the gate is
It has a main first gate and a second gate integrally formed around the first gate in a brim shape, and the bottom surface of the second gate is above the bottom surface of the first gate. A semiconductor device characterized in that it is formed in. (2) having a lightly doped source and drain that are substantially self-aligned with the first gate and a highly doped second source and drain that are substantially self-aligned with the second gate; The semiconductor device according to claim 1, characterized in that: (3) It has a gate composed of a first gate and a second gate integrally formed in a brim shape around the first gate via a gate insulating film on a semiconductor substrate of one conductivity type. A method for manufacturing a semiconductor device, comprising: a first gate insulating film formed under the second gate;
a first polysilicon film that substantially defines the thickness of the second gate; and a first insulating film that substantially defines the thickness of the first gate that protrudes above the second gate. forming a flange-shaped recess by etching the first insulating film, first polysilicon, and first gate insulating film corresponding to the gate; and forming a flange-shaped recess in the recess. A method of manufacturing a semiconductor device, comprising at least the step of embedding a conductive material constituting the gate. (4) In the step of forming a brim-shaped recess, removing all of the first gate insulating film corresponding to the gate and forming another insulating film thinner than the first gate insulating film. 4. The method of manufacturing a semiconductor device according to claim 3, characterized in that: (5) A method for manufacturing a semiconductor device having a first gate and a second gate integrally formed around the first gate via a gate insulating film on a semiconductor substrate of one conductivity type. The first gate insulating film to be formed under the second gate, the first polysilicon that substantially defines the thickness of the second gate, and the thickness of the first gate are substantially controlled. a step of sequentially forming a first insulating film defined in the above on the entire surface of the semiconductor substrate; a step of anisotropically etching the first insulating film corresponding to the first gate; a step of isotropically etching the first gate insulating film; and a second gate thinner than the first gate insulating film in the etched region of the first gate insulating film. forming an insulating film, the first gate insulating film, the first polysilicon, and the first gate insulating film;
a step of embedding a second polysilicon in an etched region of an insulating film; a step of selectively removing the first insulating film; and a step of ion-implanting an impurity of an opposite conductivity type into the semiconductor substrate to remove the first insulating film. a step of forming a source and a drain; a step of forming a sidewall spacer on a sidewall of the first gate; and a step of etching the first polysilicon so that the first gate insulating film does not overlap with the second gate. and ion-implanting impurities of opposite conductivity type into the semiconductor substrate,
A method of manufacturing a semiconductor device, comprising the step of forming a second source and a second drain.