JPH0413794B2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to n-bit parallel data processing and
2n bits refers to the number of parallel output bits of a random access memory (RAM) used in a system where 2n bit parallel data processing is mixed, and whose 2n bit output ends are connected to 2n data output lines. Regarding the RAM control circuit for switching to n-bit and using it, for example, in an electronic desktop calculator where 4-bit arithmetic processing and 8-bit arithmetic processing are mixed, the RAM that stores operands.
This is suitable for switching the number of output bits between 4 bits and 8 bits.

[Technical background of the invention and its problems]

In general, writing and reading data to and from RAM requires, for example, 4 bits in a 4-bit system.
In an n-bit system, n bits are processed in parallel. Figure 1 shows a RAM with 8-bit input/output and a capacity of 1024 bits. In the figure, 11 is RAM, IN ₁ to IN ₈ are write data to RAM 11, in 1 to in 8 are data input lines, OUT ₁ to OUT ₈ are read data from RAM 11, out 1 to out ₈ are data output lines, X ₁ ，
X ₂ , X ₄ , and X ₈ are column selection signals, and Y ₁ , Y ₂ , Y ₄ , and Y ₈ are row selection signals.

In the above configuration, when writing data to the RAM 11, the write data IN ₁ to _{IN 8}
are column selection signals X ₁ , X ₂ , X ₄ , X ₈ and row selection signals
RAM11 selected by Y ₁ , Y ₂ , Y ₄ , Y ₈
is stored at a predetermined address. Furthermore, when reading data, the read data OUT ₁ to OUT is read from the address selected by the column selection signals X ₁ , X ₂ , X ₄ , and X ₈ and the row selection signals Y ₁ , Y ₂ , Y ₄ , and Y ₈ . ₈
is read out.

In the above configuration, RAM 11 to 8
When reading bit data in parallel, there is no problem because all data output lines out1 to out8 are selected. However, for example, when reading 4 bit data in parallel, data output lines out1 to out8 are selected.
-out8, four are in the selected state and the other four are in the non-selected state. Normally, a latch circuit, clocked inverter, etc. is provided between the output terminal of each bit of the RAM 11 and each data output line out1 to out8, and the circuit is configured to adjust the timing of parallel data output. Therefore, in order to change the number of bits output from RAM 11, one of the selected latch circuits and clocked inverters must be used.
It is conceivable to supply a clock to the bits and stop supplying the clock to the four non-selected bits. However, the output terminals of latch circuits and locked inverters whose clock supply is stopped become in a high impedance state.
The book's data output line also goes into a high impedance state. This high impedance state of the data output line is undesirable from a system and circuit perspective because the state of the data line becomes unstable.

By the way, in order to perform high-speed data processing,
Although 8-bit processing is more advantageous than 4-bit processing, 4-bit processing may be easier depending on the content of data processing (for example, four arithmetic operations).
However, as mentioned above, the 8-bit parallel output configuration
When trying to obtain 4-bit parallel output from RAM, the read data line of the RAM goes into a high impedance state, so even if the data is suitable for 4-bit processing, it can be handled as 8-bit data by, for example, the upper 4 bits. “0” as the data of
It is necessary to input and perform 8-bit processing.
Performing such processing has the disadvantage that RAM is used inefficiently, data processing in the ALU or peripheral circuits that exchange data with the RAM becomes complicated, and power consumption increases.

[Purpose of the invention]

This invention was made in view of the above circumstances, and its purpose is to be used in a system where n-bit parallel data processing and 2n-bit parallel data processing coexist. To provide a RAM control circuit capable of switching the number of parallel output bits from 2n bits to n bits in a stable state in a RAM whose 2n bit output ends are connected to 2n data output lines.

[Summary of the invention] That is, in order to achieve the above object, the present invention utilizes n-bit parallel data processing and
It is used in a system where 2n-bit parallel data processing is mixed, and the 2n-bit output ends are connected to 2n data output lines, respectively, and 2n-bit parallel data readout and n-bit parallel data processing are performed. selective data reading is performed.
In the RAM, a first group of n MOS transistors whose conduction is controlled by an addressing signal is provided between each of the lower n data output lines and a ground point, and connected to each of the remaining upper n data output lines. A second group of n MOS transistors whose conduction is controlled by a control signal that controls switching of the number of output bits of this RAM is provided between the points, and the lower n bits or upper n bits of data from the RAM are processed in parallel. At the time of reading, the upper n or lower n data output lines that are not used are connected to the second group or the first group.
The structure is such that the MOS transistor is made conductive and set to the ground potential.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings. Figure 2 shows its configuration.
As output selection means for data output lines out1 to out8, MOS transistors _Tr1 to _Tr4 and
Tr ₅ to Tr ₈ are provided for address designation (row selection) signals.
The conduction is controlled by a control signal for controlling Y ₁ and the peripheral circuits of the memory cell array, that is, a control signal Y ₁ ' for switching the number of bits of the RAM.

The operation in the above configuration will be explained.
When "Y ₁ = 0, Y ₁ ' = 0", the transistor Tr ₁ ~
Since all Tr ₈ are turned off, data output lines out1 to out8 are selected and 8-bit read data _OUT1 to _OUT8 are read out. Also,
When "Y ₁ = 0, Y ₁ '= 1", the transistor Tr ₁ ~
Since Tr ₄ is in an off state and transistors Tr ₅ to _{Tr 8} are in an on state, data output lines out5 to out8 are grounded. Therefore, read data OUT ₁ ~
OUT ₄ is selected, OUT ₅ to _{OUT 8} are unselected, and 4 bits of data OUT ₁ to OUT ₄ are read out. When “Y ₁ = 1, Y ₁ ′ = 0”, transistors Tr ₁ to _{Tr 4} are in the on state;
Since Tr ₅ to _{Tr 8} are in the off state, the data output lines out1 to out4 are grounded and the read data is
OUT ₁ to OUT ₄ are unselected, OUT ₅ to OUT ₈ are selected, and 4 bits of data OUT ₅ to OUT ₈ are read out.

The relationship between the levels of the above-mentioned addressing signal Y ₁ and control signal Y ₁ ' and output selection/non-selection is collectively shown in FIG.

As mentioned above, 8-bit parallel data reading and parallel data reading of upper 4 bits or lower 4 bits are performed using the addressing signal.
It can be freely selected according to the levels of Y ₁ and the control signal Y ₁ ', and unselected data output lines can be fixed to the ground potential. Therefore, in a RAM with an 8-bit data output line, 4-bit data can be read out in a stable state, so it is possible to input "0" into the upper 4 bits of data suitable for 4-bit processing. to 8 bits, 8
There is no need to process it as bit data.

Note that in the above embodiment, the 8-bit parallel output configuration is
Although the case where 4-bit parallel output is obtained from the RAM has been described, it goes without saying that the present invention is not limited to the above-mentioned number of bits.

[Effects of the Invention] As explained above, according to the present invention, it can be used in a system where n-bit parallel data processing and 2n-bit parallel data processing coexist.
In a RAM in which 2n bit output ends are respectively connected to 2n data output lines, a RAM control circuit that can be used by switching the number of parallel output bits from 2n bits in a stable state can be obtained.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a conventional RAM, FIG. 2 is a diagram showing a RAM control circuit according to an embodiment of the present invention,
FIG. 3 is a diagram for explaining the operation of the RAM control circuit shown in FIG. 2. 11...RAM, IN ₁ to IN ₈ ...Write data, in1 to in8...Data input line, OUT ₁ to
OUT ₈ ...read data, out1-out8...data output line, Tr1 _{- Tr8} ...transistor.

Claims (1)

[Claims] It is used in a system where 1n-bit parallel data processing and 2n-bit parallel data processing are mixed, and the 2n-bit output terminals are connected to 2n data output lines, respectively, and 2n-bit parallel data processing is performed. In a RAM in which read-out of parallel data and read-out of n-bit parallel data are selectively performed, a first group of n data output lines whose conduction is controlled by an addressing signal between each of the lower n data output lines and a ground point are used. a second group of n MOS transistors whose conduction is controlled by a control signal that controls switching of the number of output bits of this RAM between each of the remaining upper n data output lines and the ground point. are established respectively,
When reading the lower n bits or upper n bits of data from the RAM in parallel, the MOS transistors of the second group or the first group are made conductive to the unused upper n or lower n data output lines. A RAM control circuit characterized in that the RAM control circuit is configured to set the ground potential to the ground potential.