JPH041397B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a switch capacitor integrator suitable for large-scale integration of an analog-digital mixed type using MOS device technology.

(Background Art) A conventional integrator is the CR integrator shown in FIG. 1, and the characteristics of the integrator are as shown in equation (1).

V _OUT /V _IN =-1/jωC _A R _B (1) Figure 2 shows a switched capacitor integrator equivalent to the integrator in Figure 1. However, C _B =1/fR _B (f
=1/T, T; sampling period). Second
In the figure, SW ₁ to _{SW 4} are MOS transistors, and timings SW ₁ and SW ₃ shown in Figure 6 are conductive when timing φ _B is high level, and SW ₂ and SW ₄ are conductive when _B is high level. By repeating the switching operation, the sampling capacitance C _B is
charges the input signal charge to and transfers the charge to the integral capacitor C _A. For convenience of explanation, Figure 3 shows an equivalent switch of the MOS transistor in Figure 2.
This is a diagram in which SW ₁ to _{SW 4} have been replaced, and shows the case in which φ _B is at a high level and _B is at a low level in FIG. (Also in Figures 4 and 5, the MOS transistors are replaced with equivalent switches.) In recent years.
As the degree of integration of LSIs improves, when attempting to implement large-scale filter banks using conventional switched capacitor integration on-chip, power consumption and chip size increase due to increases in operational amplifiers and capacitance area, and further chip size also increases. Many difficulties have arisen as a result of this, including a decline in yield and an increase in price.

(Problem of the Invention) The present invention is intended to improve these drawbacks and will be described in detail below.

(Structure and operation of the invention) A time division multiplex integrator according to the invention is shown in FIG. 4, and a switch timing diagram is shown in FIG. 7. In Figure 4, C _B is a sampling capacitor, C ₁ to _{C N} are N individual integral capacitors, C _c is a common integral capacitor, OPO is an operational amplifier, SW ₁₀ to SW ₈₀ , SW ₁ C to SW ₂ NC are switching FIG. 7 is a switch timing diagram of the changeover switch. In Fig. 4, the switches SW ₁₀ to SW ₄₀ at both ends of the sampling capacitor C _B are set to 1/N of the period T at the timing of φ _b and _b in Fig. 7.
Sampling capacity with repeated switching at regular intervals
The charge of C _B is transferred to the individual integral capacitor C ₁ ~ connected between the output terminal of the operational amplifier OPO and the negative polarity input terminal through the changeover switch SW ₁ C ~ SW ₂ NC at the timing of φ 1 ~ _φ N in Figure ₇ . to C _N , and Fig. 7 φ _b , _b
Switches SW ₅₀ , SW ₇₀ , which operate at the timing of
φ _a , switch SW ₆₀ that operates at the timing of _a ,
Transfer to the common integral capacitor C _c with SW ₈₀ at both ends.
The common integral capacitor C _c is connected in parallel with the N individual integral capacitors C ₁ to C _N to form N integral capacitors. Now, to explain in detail the operation at the timing of φ ₁ (1ch) in Fig. 7, within the timing of φ _b , the sampling capacitor C _B connects SW ₂₀ and SW ₄₀ to ground, and the charge charged in the sampling capacitor C _B is discharged and becomes the initial state. The individual integral capacitor _C1 turns ON at timing _φ1 . Connected to the output terminal and negative polarity terminal of the operational amplifier OPO through SW ₁ C and SW ₂ C, and the individual integral capacitor
The output voltage of the operational amplifier is restored to the voltage of one cycle ago by the capacitance voltage due to the charge held by _C1 from one cycle (T seconds) ago. For the common integral capacitor C _c , the input terminal side of the common integral capacitor is grounded by turning SW ₇₀ ON and SW ₅₀ OFF at the timing of φ _b , and the output terminal side is grounded by turning ON SW ₈₀ and SW ₆₀ at the timing of φ _a . of
Turn OFF and ground, discharge the charge charged at the previous timing φ _N , and at the time T _c (Figure 7) from φ _a to φ _b , switch SW ₈₀ OFF and SW ₆₀ ON to turn on the operational amplifier. The output voltage of the OPO is charged and becomes the same voltage as the individual integral capacitor _C1 . At the next timing _b , the input terminal side of the common integral capacitor C _c is switched at timing _b .
Turn on SW ₅₀ and turn off SW ₇₀ to set individual integral capacitance C ₁
Integral capacitance C _T1 one period (T seconds) ago is connected in parallel with
(C _T1 = C ₁ + C _c ) is restored. Here, since the negative terminal of the operational amplifier is a virtual ground input, the potential on the input terminal side of the common integral capacitor is the same as when grounded.
Sampling capacitance C _B is at timing _B
SW ₁₀ and SW ₃₀ are turned ON and SW ₂₀ and SW ₄₀ are turned OFF to transfer the sampling charge of the input signal to the integration capacitor C _T1 and complete the integration operation at the timing of φ ₁ . Thereafter, by repeating the above-described operation every T/N time, N integral characteristics can be realized. Here, the common integral capacitance C _c is set below the minimum value of the integral capacitances C _T1 to C _TN that realize N integral characteristics, and the difference is assigned to the individual integral capacitances (C _TN −C _c =C _N , N=1, 2,
..., N), the individual integral capacity can be minimized.
FIG. 5 shows an embodiment of a four-time multiplex bandpass filter using an integrator according to the present invention, which operates at the timing shown in FIG. 7, and outputs the four bandpass filters as shown in FIG. Output. The transfer function for one channel of this bandpass filter is as shown in equation (2). Since bandpass filters whose center frequencies are close to each other have a small deviation in integrated capacity, the capacity reduction effect of the present invention is very large.

V _OUT /V _IN =-K ₁ (1-Z ^-1 ) /Z ^-2 + (K ₂ K
₃ −K ₁ −2) Z ⁻¹ + (1+K ₁ )……(2) K ₁ =C _B1 /C _N1 , K ₂ =C _O2 /C _N1 , K ₃ =C _B2 /C _N2 (N=1 , 2,..., 4) Z = cosωT + jsiNωT (ω = 2π, = 1/T, T: sampling period) (Effects of the invention) According to the present invention, calculations are performed using time division multiplexing of conventional switched capacitor integrators. Amplifier Reduction Effect In addition to the accompanying reduction in power consumption and chip size, by sharing the integral capacity of a switched capacitor integrator that occupies a large chip size, it is possible to significantly reduce the chip size. The chip size can be reduced, and the resulting improvement in yield and cost can be realized, and the effects are very large.

[Brief explanation of drawings]

Figure 1 shows a conventional CR integrator circuit, Figure 2 shows a switched capacitor integrator circuit that replaces the one shown in Figure 1 with a switched capacitor, and Figure 3 shows a symbol of the MOS transistor switch in Figure 2. 4 shows a switched capacitor time-division multiplex integrator according to the present invention, FIG. 5 shows a 4-multiband bandpass filter as an embodiment of the invention, and FIG. 6 shows the switch timing of the device of FIGS. 2 and 3. 7 are switch timing diagrams of the devices shown in FIGS. 4 and 5, and FIG. 8 is a diagram showing the waveforms and frequency characteristics of the input signal and output signal of the four-band pass filter of FIG. 5. C _B ...sampling capacitor, _C1 to C _N ...individual integral capacitor, C _c ...common integral capacitor, OPO...operational amplifier, SW...MOS transistor switch.

Claims (1)

[Claims] 1. In a switched capacitor integrator configured by combining multiple switch capacitors and operational amplifiers, a sampling capacitor that samples signal charges at 1/N times the sampling period (N is the multiplicity) and a sampling capacitor that samples signal charges at 1/N times the sampling period N hold capacitors that serve as coefficients that determine the integral characteristic that performs integral calculations with a pulse width of N, and N hold capacitors that charge and discharge with a pulse width that is 1/N of the sampling period. 1. A time division multiplexed switched capacitor integrator, characterized in that it has a common coefficient capacitor having a capacitance, and obtains an integral characteristic by the sum of the common capacitor and a hold capacitor.