JPH04140876A - Data processing system - Google Patents

Abstract

PURPOSE:To enable a command fetch at a high speed by assigning a transferring a transferring request to one bit corresponding to each host computer in a parallel I/F, and transmitting it. CONSTITUTION:A host computer(HC) 20 assigns the transfer request to one bit in a parallel I/F 50 by a transfer request assigning part 90 to a parallel I/F, based on a device number uniquely set by a device number setting part 80 towards the HC 20, when a data transfer request 70 is generated. An idle state signal 60 indicating the idle state of the I/F 50 is transmitted to the entire HC such as HC 20-40 connected with the I/F 50. The HC 20 checks whether the I/F 50 is used or not by the signal 60, selects the output of the assigning part 90 by a selection circuit 110 when the I/F 50 is not used, and transmits the output to he I/F 50. An arbitration part 120 of an input/output controller 10 fetches the transfer request assigned to the bit of the I/F 50 at the time of the idle state, and arbitrate it. Thus, the HC command fetch can be attained at the high speed without providing an exclusive arbitrating signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing system, and more particularly to a data processing system configured with a plurality of host computers and one processor that processes commands from these host computers. Regarding.

[Conventional technology]

In such a conventional data processing system, the processing processor has a dedicated data transfer request line for each host computer in order to check whether there are processing requests from multiple hosts/computers, and the processing processor receives these data transfer requests. Arbitration was being conducted for the processing request c: from the line.

[Problem to be solved by the invention]

The above-described conventional data processing system has the disadvantage that as the number of host computers connected to the disjoint interface increases, the number of data transfer request lines C for arbitration increases.

Another method is to use the parallel interface from the input/output control device of the processor to inquire of each host computer about the existence of a processing request and arbitrate, but this method requires This has the problem of adding time to transfer requests and reducing processing performance.

An object of the present invention is to provide a data processing system that does not require a transfer request line for each host computer and can still receive commands from the host computer at high speed.

[Means to solve the problem]

In the data processing system of the present invention, a plurality of host computers and one processing processor are connected by one input/output control device through a parallel interface, and commands from the host computers are received under the arbitration of the input/output control device. In a data processing system that takes over the processing processor and performs processing, a first means for giving a unique device number to each of the host computers connected by the parallel interface, and a data transfer request from the host computer to the processing processor. a second means for assigning an instruction to one bit corresponding to the device number of the data bus of the parallel interface; and a second means for assigning the data transfer request instruction assigned to the data bus when the data bus is not in a data transfer state to the processing processor. and third means for transferring.

The third means may be a selection circuit that selects and sends the data to be transferred by the host computer to the processor or the data transfer request instruction assigned to the data bus by the second means. .

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

N host computers 20.30. ... 40 are connected to the input/output control device 10 of the processing processor through a parallel interface 50, and each of them is about to send transfer data 100 from the host computer.

When a data transfer request 70 is generated, the host computer 2o uses the transfer request allocation unit 90 of the parallel interface to allocate the transfer request to the parallel interface 50 based on the device number uniquely set for the host computer 20 by the device number setting unit 8o. Assign to a certain bit.

Whether or not the parallel interface 50 is currently in use (transferring data) is managed by the input/output control device 10 of the processor.
An idle state signal 60 indicating an idle state of 0 is sent to all the host computers 20, 30, . . . , 40, etc. connected to the parallel interface 5o.

The host computer 20 checks whether the parallel interface 5o is in use based on the idle state signal 60, and when it is not in use, selects the output of the transfer request allocation section 90 using the selection circuit 11.0, and selects the parallel Send to interface 5o.

The arbitration unit 120 of the input/output control device 10 of the processor takes in transfer requests assigned to bits of the parallel interface 50 during an idle state and performs arbitration.

〔Effect of the invention〕

As explained above, the present invention allocates and sends a transfer request to one bit corresponding to each host computer in the parallel interface, thereby providing a dedicated request line for data transfer requests from each host computer. This has the effect of speeding up command reception from the host computer without providing a dedicated arbitration signal.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention. 10... Processor input/output control device, 20.3
0.40...Host computer, 50...Parallel interface, 60...Idle state signal, 70...
...Data transfer request, 80...Device number setting section, 90
... Transfer request allocation unit, 100... Transfer data,
110... Selection circuit, 120... Arbitration section.

Claims (1)

[Scope of Claims] 1. A plurality of host computers and one processing processor are connected by one input/output control device through a parallel interface, and commands from the host computers are received under the arbitration of the input/output control device. In a data processing system that the processing processor receives and processes,
a first means for assigning a unique device number to each of the host computers connected by the parallel interface; and a first means for assigning a unique device number to each of the host computers connected to the parallel interface; and third means for transmitting the data transfer request instruction assigned to the data bus to the processor when the data bus is not in a data transfer state. Characteristic data processing system. 2. The third means is a selection circuit that selects and sends the data to be transferred by the host computer to the processor or the data transfer request instruction assigned to the data bus by the second means. The data processing system according to claim 1, characterized in that: