JPH0414095A - Image processor - Google Patents

Abstract

PURPOSE:To simultaneously access 1st and 2nd memories and to improve a processing speed by providing a memory control circuit which discriminates memory access requests, prioritizes them and divides the areas of the 1st and the 2nd memories to perform access. CONSTITUTION:When the memory access requests are respectively outputted from a host computer 1, a CPU 2 and a character data development circuit 3, a request selection control part in the memory control circuit 8 discriminates them, a memory access mediation part prioritizes them and generates and transmits a memory access signal to a memory bank control part, which selects the address condition of a request origin and transmits a memory control signal to an image RAM 4 or/and a font RAM 5 in accordance with the condition. Thus, the access areas of the RAMs 4 and 5 are divided and the request origins can access at the same time, then the processing speed is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing device that generates image data and transfers the image data to an image output device.

[Conventional technology]

FIG. 3 is a block diagram showing the configuration of this type of conventional image processing device. In the figure, 1 is a host computer that issues commands to generate image data, and 2 is a host computer that issues commands to generate image data. A RAM which stores data is a central processing unit that executes a program for generation, 3 is a character expansion circuit that expands outline font data into character data, and 4 is a RAM in which commands from the host computer 1 are written. An image RAM 5 serves as a first memory in which image data generated by the CPU 2 and the character data expansion circuit 3 is stored, and 5 is an outline memory for the character data expansion circuit 3 to expand into character data (raster image data). A font RAM serves as a second memory for storing font data, a font ROM 6 stores outline font data to be expanded into character data by the character data expansion circuit 3, and an image RAM 7.
This is a printer device that outputs the image data generated in step 4.

Next, the operation of this conventional example will be explained. First, the host computer 1 writes a command for generating image data into the image RAM 4. CPU2 is program ROM2
-1 and the program execution RAM 2-2 to interpret the command on the image RAM 4, and in the case of a command to generate characters, write the command on the image RAM 4 in order to cause the character data expansion circuit 3 to generate character data,
The character data expansion circuit 3 is activated for expansion into character data. When the character data expansion circuit 3 is activated by the CPU 2, it loads the font RAM 5 or font R.
Read outline font data from OM6,
The character data is expanded and generated in the form of a raster image on the image RAMJ, and the completion of generation is reported to the CPU 2. The CPU 2 thereby reports the completion of command execution to the host computer 1.

When the image data for one page is generated by repeating such operations, the host computer 1 issues a command to the CPU 2 to output image data.

The CPU 2 thereby transfers the image data for one page to the printer device 7 and ends the process.

[Problem to be solved by the invention]

In a conventional image processing device, the host computer 1, CPU 2, and character data expansion circuit 3 can only access the image RAM 4 and font RAM 5 exclusively and independently, and when others are accessing, the access is interrupted. There was a problem in that the processing speed was slow because the process had to wait until the process finished.

This invention has been made to solve the above-mentioned problems, and provides an image processing device that enables a host computer, a central processing unit, and a character data expansion circuit to simultaneously access memory and improves processing speed. The purpose is to

[Means to solve the problem]

The image processing device according to the present invention distinguishes each memory access request from the computer 1, the central processing unit 2, and the character data expansion circuit 3, prioritizes the memory access requests, and stores them in at least the first memory (image RAM 4). ) or/and a memory control circuit 8 that controls the area of the second memory (font RAM 5) to be divided and accessed.
It is characterized by having the following.

[Effect]

The memory control circuit 8 distinguishes each memory access request from the computer 1, the central processing unit 2, and the character data expansion circuit 3, prioritizes the memory access requests, and sends them to at least the first memory (image RAM 4) or / and the control unit so as to divide and access the area of the second memory (font RAM 5).

(Embodiment) Fig. 1 is a block diagram showing the configuration of an image processing device according to an embodiment of the present invention.In Fig. 1, components corresponding to those shown in Fig. 3 have the same reference numerals. 1, and a description thereof will be omitted. In FIG. This is a memory control circuit that controls the RAM 4 and/or font RAM 5 to be divided and accessed.

FIG. 2 is a block diagram showing the configuration of the memory control circuit 8. As shown in FIG. In FIG. 2, 9 is at least the image RA
10 is a memory bank control unit for dividing and controlling the area of M4 and/or font RAM 5; A request selection control unit 11 is a host computer 1. C.P.
Arbitrates memory access requests from U2 and character data development circuit 3 and DRAM element paste refresh requests, prioritizes memory accesses to image RAM 4 and/or font RAM 5, and responds to each access request. Acknowledge signal (ACK signal)
host computer 1, CPU 2 and character data expansion circuit 3
This is a memory access arbitration unit that performs processing to return data to This memory control circuit 8 is connected to the host computer 1. The configuration is such that it can mediate different memory access requests from three directions, the CPU 2 and the character data expansion circuit 3, and can also mediate refresh specific to DRAM.

Next, the operation of this embodiment will be explained. Host computer 1. When there is a memory access request from each of the CPU 2 and the character data expansion circuit 3, the request select control section 10 distinguishes these memory access requests and sends them to the memory access arbitration section 11. The memory access arbitration unit 11 prioritizes these memory access requests, creates a memory access signal, sends it to the memory bank control unit 9, and returns an ACK signal indicating completion of the memory access to the request source. Note that the priority order is not necessary when there is only one memory access request. The memory bank control unit 9 selects the address condition of the selected request source and stores the memory (image RAM 4 or/and) and ont RAM according to the address condition of the selected request source.
5) Sends a memory control signal to. Through such processing, image RAM 4 and/or phono 1-RAM
The access area of 5 is divided into host computer 1, CPU
2. The character data expansion circuit 3 can access the image RAM 4 and/or the font RAM 5 at the same time. By providing the memory control circuit 8 as described above, the control circuits around the memory may also be configured to accept and receive memory access requests in one direction.

In the above embodiment, arbitration of memory access request sources in three directions has been described, but the same effect can be achieved for a larger number of requests. Further, although the above embodiment does not explain access to the font ROM 6, this access can be performed in a similar manner.

〔Effect of the invention〕

As described above, according to the present invention, a computer, a central processing unit,
and a memory that distinguishes each memory access request from the character data expansion circuit, prioritizes the memory access requests, and controls the areas of at least the first memory and/or the second memory to be divided and accessed. Since the configuration includes a control circuit, there is no exclusive access, and the host computer, central processing unit, and character data expansion circuit can access the first memory and/or the second memory at the same time. The effect of improving processing speed can be obtained.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a block diagram showing the configuration of an image processing apparatus according to an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of the memory control circuit in FIG. 1, and FIG. The figure is a block diagram showing the configuration of a conventional image processing device. ■...Host computer, 2...CPU (Central Processing Unit), 3...Character data expansion circuit, 4...Image RAM (first memory), 5...Font RAM
(second memory), 8... memory control unit circuit.

Claims (1)

[Claims] A computer that issues commands to generate image data, a central processing unit that interprets the commands and generates image data, a character data expansion circuit that expands font data into character data, and a computer that issues commands to generate image data. a first image data storage device for storing image data generated by the processing of the central processing unit and the character data expansion circuit;
and a second memory storing font data for the character data rasterization circuit to rasterize into character data, the image processing apparatus comprising: A memory control circuit is provided that distinguishes each memory access request, prioritizes the memory access requests, and performs control to divide and access at least an area of the first memory and/or the second memory. An image processing device characterized by: