JPH0414157A - Channel device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a channel device that transfers data between a main storage device and an input/output device of a computer.

Optimal LSI integration of individual components that make up the channel device
The invention relates to a channel device that has been

[Conventional technology]

In the prior art, each component of a channel device was realized using an IC, an LSI, a RAM element, a printed circuit board, or the like. In recent years, advances in semiconductor integrated circuit technology and mounting technology on printed circuit boards have made it possible to mount more of the above-mentioned components on one component, and the number of components used as channel devices has decreased. There is.

Related channel devices of this type include, for example, the literature Nikkei Electronics, 1985, 11-18.
．． No.382. There is a channel device described in p p22g-288. In this channel device, the logic circuit section is configured with two CMOS-VLSIs, and the input/output interface driver and receiver circuits are configured with another LSI, and eight channel devices configured in this way are combined into one. The structure is mounted on a single printed circuit board. The channel device includes, under the control of microinstructions,
Since there is no means to access the main memory and a means to retain all the information of the channel command word, there is no means to access the main memory and to retain all the information of the channel command word, so input/output command processing, input/output interrupt processing, retrieval processing of the channel command word from the main memory, chain processing of the channel command word could not be executed on a channel device. These processes were executed by a separate device called a channel control device. The prior art channel control device centrally controls 16 channel devices.

[Problem to be solved by the invention]

The above conventional technology required two VLSIs and a separate channel control device to realize the channel device.

It is an object of the present invention to provide a highly functional channel device that does not require a channel control device, and further to provide a small and economical channel device.

Another object of the invention is to provide a high speed channel device.

Another object of the invention is to provide a highly reliable channel device.

Another object of the present invention is to provide a channel device with low power consumption.

[Means to solve the problem]

In order to achieve the above object, the channel device includes a control memory for storing microinstructions, a means for accessing the main memory according to instructions from the microinstructions, a means for holding information on channel command words, and a means for storing data to be transferred. A means for counting the number of bytes, a data transfer control unit that executes data transfer between the main storage device and the input/output device according to information in the channel command word, a data buffer unit that temporarily stores data to be transferred, and controls the input/output device. This device is equipped with an input/output interface control section that implements these functions using a single VLSI.

In order to achieve the other objects mentioned above, the driver/receiver circuit for the input quantity interface signal is not included in the above-mentioned VLSI but is realized by a separate LSI.

For the other purposes mentioned above, the VLSI is realized by CMOS.

[Effect]

By providing means for accessing the main memory according to instructions from microinstructions and means for retaining channel command word information, processing for retrieving channel command words from main memory, chaining of channel command words, and input/output interrupt processing can be performed. It is a highly functional channel device that does not require a channel control device because it can be executed by the channel device.

In addition to the above two means, all the components listed above are provided and realized by a single VLSI, so it is small and economical.

Among the above-mentioned components, the control memory that stores microinstructions generally has a large capacity, so the VLSI chip area increases and the economical effect may decrease.

Furthermore, RAMs generally tend to be less reliable than other logic gate circuits. If the reliability of the RAM section is low, use R.
If AM is built into a VLSI, the reliability of the VLSI, which is generally more expensive than an RA Li element, will be lowered.

In such cases, VLSI can be implemented by replacing the control memory with a RAM element, which is generally cheaper than VLSI, without including the control memory in VLSI, even if it means sacrificing the high speed of RAM access.
It is possible to ensure the reliability of I and achieve economic efficiency.

Since chain processing of channel command words can be executed in a distributed manner by individual channel devices, processing can be performed at high speed without generating service waiting time for the channel device in the channel control device, compared to centralized control by a conventional channel control device.

Since the channel device including the functions of a conventional channel control device is realized in one VLSI, the number of parts is reduced and high reliability can be achieved.

By implementing the VLSI with CMOS, lower power consumption can be achieved.

Since input/output interfaces are exposed to harsh electrical environments such as overvoltages and overcurrents being easily applied, circuits that directly drive and receive input/output interface signals are likely to be damaged by external causes. If a driver/receiver circuit is built into a VLSI, damage will be large if only the driver/receiver is damaged. This is the driver
This problem can be solved by not incorporating only the receiver circuit into the VLSI, but by implementing it with another generally cheaper LSI.

This ensures the reliability of the VLSI and the economic efficiency of the channel device as a whole.

Furthermore, by separating the driver/receiver circuit from the VLSI, when connecting to multiple input/output interfaces with different electrical levels, it is possible to replace only the driver/receiver circuit with a component that satisfies predetermined electrical properties. The VLSI can be used for general purposes. VL
The development cost of SI is high, and the versatility of VLSI is economical.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. CH
, 1 is the VLSI of the channel device of the present invention and is approximately 45,
000(7) Contains logic circuit (?: MOS-VLSI.RAM, 100 is a 64 kilobit RAM element, 5 are used, has a capacity of 320 kilobit, 1
The control memory stores 8 kilowords of 40-bit microinstructions. ALU 101 is an arithmetic unit,
GSDR is a microinstruction execution control unit.

102, under the control of DEC, IO24. :111RO
,104,1ilR1,105 data is calculated and 1t1
Output to OR,106. NAR, 107, BR.

108, GSAR, and 109 are also microinstruction execution control units that determine the address in the control memory of the microinstruction to be executed next. IBS, 110, GR, 111 are temporary memory and general purpose registers used by microinstructions;
BS 110 is a RAM with a capacity of 256 bytes.

Line, 11. ! l (XBSDH) is an interface with the main storage device, FOR, 112, SDR, 113,
MMRK, 114, BMRK, 115, MAR, 116
, BAR, 117 are means for accessing the main memory, and MAR, 114 is a store mark when accessing the main memory from a microinstruction.

MAR, 116 is a main memory address when main memory is accessed from a microinstruction. When accessing the main memory from a microinstruction, a store mark is set in MMR, 114, and a main memory address is set in MAR,116. Data stored in the main memory is sent from the GR, 111 to the main memory via the SDR, 113.

Data read from the main memory is stored in GR, 111 via FOR, 112.

CMDR, 119, NFLG, 120, NBC, 121
, BAR, 117 is means for storing channel command word information.

FIG. 4 shows an example of a channel command word (hereinafter abbreviated as CCW). CCL4 consists of 64 bits, command CMD, 401, control flag FLG, 402
, data byte count BC, 403, and data main memory address ADH, 404. CMD; 401 is CMD
R, 119, FLG.

402 is NFLG, 120 is BC, 403 is NBC
, 121 and ADR, 404 are stored and held in BAR, 117, respectively.

IBC, 122 is a counter that counts the number of data bytes transferred between the input/output device and the channel device;
123 is a counter that counts the number of data bytes transferred between the channel device and the main memory.

BIR, 124, CBS, 125, BOR, 126, F
DR, 112, SDR.

113, BMRK, 115, BAR, 117 are data transfer control units that execute data transfer between the input/output device and the main storage device according to CCW information. CBS 125 is a data buffer section for temporarily storing data to be transferred, and is a RAM having a capacity of 512 bytes. BMRK, 115 is used as a store mark for main memory access, and BAR, 117 is used as a data address in the main memory.

1TAG, 127.0TAG, and 128 are input/output interface control units that control input/output devices.

CLC 129 and ITC 130 are startup and interrupt interface control units between the instruction processing unit in the central processing unit and the channel device.

CH,1 has the above configuration, and can execute CCW retrieval processing from main memory, CCW chain processing, and input/output interrupt processing under the control of microinstructions.

FIGS. 2 and 3 show an LSI for driver/receiver circuits, which is the second component of the channel device of the present invention. There are two types: DRl, 2, and DR2, 3. DRl,2 has 14 interface drivers, 201, 8 interface receivers, 202, and 12 bidirectional interface driver/receivers, 203. The other circuits are TTL driver receivers. DR2
, 3 are 12 interface receivers, 202 and 18
bidirectional interface driver/receiver, 203
and the other circuits are TTL driver/receivers. LSIDRl.

2 and DR2, 3 have a total of 92 circuits and 96 circuits for the interface driver/receiver and TTL driver/receiver, respectively, and are realized with a small LSI, and the V
It is sufficiently inexpensive compared to L S I CHl,1. In this embodiment, the input/output interface signals are 26 tag signals and 18 hash signals.
One each of Rl,2 and DR2,3 are used, and signals are assigned as shown in FIGS. 2 and 3.

According to this embodiment, the control memory is realized by five RAM elements and is separated from the VLSI CH,1.
The chip area can be reduced, the yield of LSI production can be improved, and the cost of channel devices can be reduced, resulting in an economical effect. RAM elements are significantly cheaper than VLSI.

〔Effect of the invention〕

Since the present invention is configured as described above, it produces the effects described below.

Since only one VLSI is used, it is small, economical, and highly reliable. Furthermore, CCW retrieval processing, CC
Since the channel device itself can execute W chain processing and input/output interrupt processing, it is highly functional and fast. Since a channel control device is not required, the overall structure is small, economical, and highly reliable. Furthermore, since the input 8-input interface driver/receiver circuit is constructed from a separate small and inexpensive LSI, the reliability of the VLSI is improved and the VLSI is made more versatile, resulting in economical results. Furthermore, VLSI is
Since it is implemented using MO8, it has the effect of low power consumption. Furthermore, when using a large amount of control memory, VLS
It is economical because it can lower the manufacturing cost of I and increase reliability.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the logical configuration of a channel device as an embodiment of the present invention, and FIGS. 2 and 3 are block diagrams showing the logical configuration of a driver/receiver circuit LSI as an embodiment of the present invention. , FIG. 4 is a diagram showing the bit structure of the channel command word used in this embodiment. 1.VLSI, 2-LSI, 100... RAM for control storage, 101... Arithmetic unit, 111-118... Main memory access means, 117.1
19-121...Registers for storing channel command word information. 201 to 203 - Triber/receiver for input/output interface.

Claims (1)

[Claims] 1. A control memory for storing microinstructions, an arithmetic unit, a microinstruction execution control unit, means for accessing the main memory according to instructions from the microinstructions, and holding information on channel command words. a data transfer control unit that includes means for counting the number of bytes of data to be transferred and executes data transfer between the main storage device and the input/output device according to information in the channel command word; and a data buffer unit that temporarily stores data to be transferred. and an input/output interface control unit that controls the input/output device as components, all the components are realized by one VLSI, and a driver that transmits signals on the input/output interface and a receiver circuit that receives the signals. A channel device characterized in that the VLSI and the LSI realize one channel device. 2. The channel device according to claim 1, wherein among the constituent elements, a control memory for storing microinstructions is replaced with a RAM element, and other constituent elements are realized by one VLSI. 3. The channel device according to claim 1, wherein the VLSI is CMOS.