JPH0414159A - Data bus switching circuit - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data bus switching circuit, and more particularly to a data bus switching circuit that switches between upper and lower bytes of data.

[Conventional technology]

For the allocation of memory byte addresses, see Figure 4 (a).
), the upper byte of DI5 to D8 is assigned an even address, and the lower byte of D7 to DO is assigned an odd address, and as shown in (b) of the same figure, the upper byte is assigned an odd address and the lower byte is an even address. There are two types of assignments. Therefore, when connecting a terminal to a control device that has a memory to which byte addresses are allocated as shown in Figure 4 (a), the byte address allocation of the terminal's memory should be selected as shown in Figure 4 (a). is normal.

This is because, in the above case, if a terminal with memory allocated to the byte addresses shown in Figure 4(b) is connected, a byte-by-byte DMA (direct memory access) transfer from the terminal to the control device would result. , the fifth on the terminal
The data in the memory that is allocated as shown in Figure (b) is allocated in the memory of the control device as shown in Figure 5 (a), and the upper byte/lower byte of the data is reversed. It is from. Therefore, if the control device adopts the memory byte address allocation shown in FIG. 4(a), the terminal should also adopt the same memory byte address allocation shown in FIG. 4(a). That's usually how it works.

[Problem to be solved by the invention]

However, after constructing a system consisting of a control device and a terminal, it may become necessary to use a different type of memory address allocation for the control device than the previous control device due to changes in various conditions or other reasons. There is. In that case, if a byte-by-byte DMA transfer is performed from the terminal to the control device as described above, the data from the terminal will be stored in the control device's memory with the upper and lower bytes reversed. Conventionally, it has been necessary for the control device to exchange the upper and lower bytes of all received data through software processing, resulting in a problem in that the burden on the software is heavy.

The present invention was made in view of the above points, and an object of the present invention is to provide a data bus switching circuit capable of DMA transfer without increasing the burden on software.

[Means to solve the problem]

FIG. 1 shows a basic configuration diagram of the present invention. In the figure, 11 is a register that sets the correspondence between odd/even addresses and upper/lower n bits. A gate circuit 12 generates a control signal based on the output signal of the register 11 and the address signal. Reference numeral 13 denotes a first selection circuit which selects data of n bits or less on the 2n bit data bus 15 based on a control signal.

Output to the input/output interface. A second selection circuit 14 selectively outputs input data of n bits or less to a data signal of n bits or less in the data bus 15 based on a control signal.

[Effect]

The gate circuit 12 controls the first selection circuit 13 in response to the address signal and the signal indicating the correspondence between odd/even addresses and upper/lower n bits from the register 11 to selectively output data of n bits or less. , first selection circuit 13
From there, upper or lower n bits of data are extracted depending on the correspondence between odd/even addresses and upper/lower n bits.

Similarly, the second selection circuit 14 selects the upper or lower n bits of input data from among the 2n bits of data on the data bus 15 based on the output control signal of the gate circuit 12.
The data is sent to the data bus 15 as data of bits or less. Therefore, in the present invention, the data bus can be switched to allocate data of n bits or less to the upper or lower n bits using the hardware configuration.

〔Example〕

FIG. 2 shows a circuit diagram of an embodiment of the present invention.

In the figure, the same components as in FIG. 1 are denoted by the same reference numerals, and their explanations will be omitted. The data node switching circuit shown in FIG. 2 is an input/output control section (1/,
In this example, the value of n is "8", it has a 16-bit data bus 15, a 16-bit wide register 11°, and a DMA transfer function, and has an 8-bit width, that is, a byte unit. Controls input/output data of Ilo.

In FIG. 2, the gate circuit 12 is a two-man exclusive OR circuit 21. The exclusive OR circuit 21 has a type of address allocation in which the upper byte of data is specified by an even number address from the register 11 that sets the memory space. In this case, "1" is input, and when the address allocation is of type where the upper byte is specified by an odd number address, "0" is input, and the least significant bit AO of the address signal is input. As a matter of course, the least significant bit AO of this address signal is "1" when the address signal is an odd address, and "0" when the address signal is an even address.

Therefore, the relationship between the output of the register 11, the value of AO, and the output of the exclusive OR circuit 21 is as shown in the following table.

Each of the AND circuits 23 and 24 has "" only during reception operation.
Since the signal S/R of 1" is applied to one input terminal, the gates of the AND circuits 23 and 24 are kept open only during reception operation. The other input terminal of the AND circuit 23 has an exclusive OR While the output signal of the circuit 21 is input via the inverter 22, it is directly supplied to the other input terminal of the AND circuit 24 without passing through the inverter 22. Therefore, during reception operation, the output signal of the AND circuit 23 is inputted via the inverter 22. The output signal G1 and the output signal G2 of the AND circuit 24 have different logical values, and the signal G1 is output from the tri-state buffer 25.
The signal G2 is applied to the tri-state buffer 26 as a control signal.

The tri-state buffer 25 is a circuit that sends 8-bit ■/○ input data as byte data to the data bus 15, and is turned on only when the signal G1 is "1".

In addition, the dry state output 26 is an 8-bit I1
This circuit sends 0 input data to the data bus 15 as upper node data, and is turned on only when the signal G2 is "L".

These tristate buffers 25 and 26 constitute the second selection circuit 14.

Further, the output signal of the exclusive OR circuit 21 is applied to the A/B terminal of the multiplexer 27, and when the logic is "0", the system bus 1 is input to the terminal A of the multiplexer 27.
The lower byte data of 5 is output to the I10 interface, and when the logic is "1", the upper byte data input to terminal B of the multiplexer 27 are output. multiplexer 2
7 constitutes the first selection circuit 13.

Therefore, as can be seen from the above table and the above operation, in the case of address allocation where the upper byte of data is specified as an even number address, the lowest bit AO of the address signal is “
When AO is "0", the multiplexer 27 selects the lower byte data input to the terminal 2, the tri-state buffer 25 is turned on and selects the lower byte of the input data, and when AO is "0", the multiplexer 27 selects the lower byte data input to the terminal. The input upper byte data of B is selected, and the tri-state buffer 26 is turned on to select the upper byte of the input data.

On the other hand, in the case of address assignment specified by the upper byte of data or an odd number address, contrary to the above, AO or “1”
”, the upper byte data is selected, and when AO or “0”, the lower byte data is selected.

Therefore, as shown in FIG. 3, when a terminal or a control device has a microprocessor unit (MPU) 3 and a ■/○ control circuit section 32, and the I10 control circuit section 32 has the above embodiment circuit, is as shown in FIG. 3(A).
Upper byte data D8-D1 at odd address to U31
5 can also be transmitted as shown in FIG. 3(B).
It is also possible to transmit data at a higher address using an even number address to the device 1, depending on the device, without placing any burden on the software. As a result, even if the memory address configuration differs between the terminal and the control device, DMA transfer can be performed without increasing the burden on the software.

In FIG. 2, the I10 output is always output, but control is required until it is actually output to Ilo, but this is not related to the gist of the present invention, so the explanation will be omitted.

It should be noted that the present invention is not limited to the above-described embodiments, and even when expanded to a 32-bit data bus, a 64-bit data bus, etc., the present invention can be similarly implemented with only a slight increase in the number of gates. There is no problem even if the data width at that time becomes 16 bits or 32 bits.

〔Effect of the invention〕

As described above, according to the present invention, it is possible to switch the data bus to distribute data of n bits or less to the upper or lower n bits depending on the hardware configuration, so even when connecting to a device with a different memory address configuration, It has features such as being able to perform DMA transfer without increasing the burden on software.

[Brief explanation of the drawing]

Figure 1 is a diagram of the principle of the present invention; Figure 2 is a circuit diagram of an embodiment of the present invention; Figure 3 is a diagram of an example of a device to which the present invention is applied; Figure 4 is a memory byte diagram. FIG. 5 is an explanatory diagram of address allocation. FIG. 5 is an explanatory diagram of data on the memory when data is transferred from the terminal to the control device. In the figure, 11 is a register, 12 is a gate circuit, 13 is a first selection circuit, 14 is a second selection circuit, 15 is a data bus, 25 and 26 are tri-state buffers, and 27 is a multiplexer. Patent applicant Fujitsu ITZU Co., Ltd.

Claims (1)

[Claims] A register (11) that sets the correspondence between odd/even addresses and upper/lower n bits, and a gate circuit (12) that generates a control signal based on the output signal of the register (11) and the address signal. ), a first selection circuit (13) that selects n-bit or less data on the 2n-bit data bus (15) based on the control signal and outputs it to the input/output interface; A data bus switching circuit comprising: a second selection circuit (14) that selectively outputs data signals of n bits or less in the data bus (15) based on the control signal.