JPH041421B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an electronic still camera that records instantaneous images of a subject on a magnetic medium such as a video floppy.

BACKGROUND ART A conventional electronic still camera is disclosed in, for example, Japanese Patent Laid-Open No. 163106/1983.

The motor control device that rotates the video floppy in this conventional electronic still camera requires high control accuracy in order to record video signals, and the signal must always be recorded from a specific position on the video floppy. Therefore, it is necessary to always maintain a constant relationship between the rotational phase of the video floppy and the phase of the vertical synchronization signal of the video signal, so a phase control loop is provided in addition to the speed control loop as a control loop for motor rotation. . Phase control in this electronic still camera requires making the response frequency to disturbances as high as possible.
In addition, since it is necessary to make the phase acquisition time as fast as possible, rather than using a so-called PG signal that generates one pulse signal per rotation of the video floppy and provides rotational phase information of the video floppy, it is necessary to make the comparison frequency as high as possible. The phase of the so-called FG signal, which is proportional to the rotational speed of the motor used for control, is divided by N (N≧1) and the phase of a reference clock signal having the same frequency as this N-divided signal is compared to determine the phase of both. I try to keep the relationship constant. However, as it is, the phase relationship between the rotational phase of the video floppy and the vertical synchronization signal is not considered at all, and the phase relationship between the two cannot be uniquely determined. Furthermore, the vertical synchronization signal is not always recorded at a fixed position on the video floppy. Therefore, after detecting the pull-in of the phase control loop, the vertical synchronization signal is reset at least once using the PG signal described above so that it has a predetermined phase relationship with an allowable range for a certain center value. , which defines this phase relationship. An embodiment of a conventional electronic still camera will be described below with reference to the drawings.

FIG. 4 shows a block diagram of the main parts for controlling the motor and resetting the vertical synchronization signal in a conventional electronic still camera, in which 101 is a video floppy which is a disc-shaped magnetic medium, and 102 is the center core of the video floppy 101. To pick up the magnetic flux from the PG pin installed at one location.
PG sensor; 103 is a motor that rotationally drives the video floppy; 104 is a frequency generator (hereinafter referred to as FG) that generates a plurality of pulses for each rotation of the motor 103 to detect the rotation speed; 105 is a frequency generator (hereinafter referred to as FG);
F-V converts the signal from FG (hereinafter referred to as FG signal) to voltage and outputs a voltage proportional to rotation speed
Converter, 106 is a motor drive circuit that rotates the motor 103, 107 is a frequency dividing circuit that divides the FG signal by N (N≧1), and 108 compares the phase of the N frequency dividing circuit 107 with the phase of the reference clock signal. a phase comparison circuit that outputs a phase error signal proportional to the phase difference;
109 is a reference clock signal generation circuit that provides a reference phase of the output signal of the N frequency divider circuit 107; 110 is a rotation circuit that amplifies the output of the PG sensor 102 that indicates the rotational phase of the video floppy 101 and outputs a pulse-shaped PG signal; Phase detector (hereinafter referred to as PG),
113 constantly monitors the phase error signal, and based on its output, detects phase pull-in based on whether the phase difference between the reference clock signal and the N frequency divider output falls within a predetermined range, and outputs a phase lock signal. 111 is a phase lock detection circuit; 111 is a vertical synchronization reset pulse generation circuit for generating a reset pulse from the phase lock signal and the PG signal; and 112 is a vertical synchronization signal generation circuit. Here, FG104, F-V conversion circuit 10
5. A speed control loop is configured by the motor drive circuit 106, FG104, N frequency divider circuit 107,
The phase comparison circuit 108 and the speed control loop described above constitute a phase control loop. FIG. 5 is an operational waveform diagram of the phase lock detection circuit 113. FIG. 6 is an operating waveform diagram of the conventional electronic still camera shown in FIG.
PG signal, B' is a delayed PG signal delayed by a predetermined time T ₁ ' from the rising edge of PG signal A' and whose rising edge is valid;
Vertical synchronization signal (hereinafter referred to as V _SYNC ) is output to
a reset pulse that resets the
D' is V _SYNC , and H' is a phase lock signal.

In the conventional electronic still camera configured as described above, when the motor drive circuit 106 turns NO and the motor 103 starts, the speed control loop converts the FG signal from the FG 104 to the F-V conversion circuit 105, as is well known. It converts into a voltage proportional to the rotational speed of the motor 103 and applies the voltage that should cause the motor 103 to a predetermined rotational speed to the motor drive circuit 106 to perform speed control, and the phase control loop uses the FG signal from the FG 104. N frequency divider circuit 10
A phase comparator circuit 108 compares the phase of the signal frequency-divided by N by 7 and the phase of the reference clock signal outputted from the reference clock signal generation circuit 109, so that the phase relationship between the two becomes a predetermined relationship. At this time, the rotational phase of the video floppy and the phase of V _SYNC are matched as follows. Here, matching the phases means making sure that the time relationship between the delayed PG signal B' and _VSYNC D' falls within a predetermined range. The phase lock detection circuit 113 constantly monitors the phase error signal T' output from the phase comparator circuit 108, and its voltage value is determined as Va as shown in FIG.
If the phase error signal T' is between Va and Vb, that is, if the phase control loop is stable, after a time _T5 has elapsed since the time when the phase error signal T' first crossed the range of A level phase lock signal is output to the vertical synchronization signal reset pulse generation circuit 111. (At this time, if the phase control loop is not stable, the same operation is performed after waiting T ₅ more from that point.) When the vertical synchronization signal reset pulse generation circuit 111 receives the phase lock signal ',
As shown in Figure 6, from the rising edge of PG signal A'
T ₁ 'From rising edge of delayed PG signal low'
T ₂ ' Generates a reset pulse ' at the delayed position.
Reset V _SYNC and start video floppy 101.
The phase is being adjusted with the Here, T ₁ ′ is
As is well known, the recording head (not shown) and the PG
This is to correct the mechanical position of the sensor 102 and set the recording start position of the video signal on the video floppy 101 to a predetermined position on the video floppy 101. The video signal is recorded from the rising edge of this delayed PG signal RO'.
T ₂ ' is at a fixed position on the video floppy 101.
The phase relationship between the rotational phase of the video floppy 101 and V _SYNC D' is determined so that V _SYNC D' is recorded without fail. The vertical synchronization signal generation circuit 112 is
After being reset (initialized) as shown in FIG. 6 by the reset pulse H, from then on, V _SYNC is generated at regular V cycles from this time.

Problems to be Solved by the Invention However, in the above configuration, V _SYNC
The phase adjustment of PG signal A′ by resetting D′ is as follows:
This must be done after the phases of the reference clock signal and the N-divided signal of the FG signal are reliably brought into a predetermined relationship (phase locked). By the way, the actual time it takes for the motor 103 to start up and the phase to be pulled in varies depending on the time, and the time is short.
0.2 (S), with a long-term variation of about 0.8 (S). Therefore, the time _T5 set by the phase lock detection circuit 113 is set to the longest time, and even if the phase is actually locked earlier than that, the phase lock signal will only be reached after _T5 has elapsed. It will not be output. In other words, even if the rotation of the video floppy 101 stabilizes and becomes ready for recording, it is not possible to record immediately, and this time loss means that it is not possible to quickly get to the recordable state from the standpoint of shutter stability and power consumption. This has become a major problem for the electronic still cameras that are required.

Means for Solving the Problems The present invention provides vertical synchronization signal generation means that can be initialized by a reset signal, gate pulse generation means that generates a gate pulse of a fixed period after a predetermined time delay from the vertical synchronization signal, and a magnetic A rotational phase signal detection means for detecting the rotational phase of the disk, a delay means for generating a signal delayed by a predetermined time from the rotational phase signal, and a vertical synchronization signal initialization means for outputting a reset pulse to initialize the vertical synchronization signal generation means. This is an electronic still camera having a setting means.

Effects According to the above-described configuration, when the time relationship between the delay signal of the delay means and the gate pulse is not within a predetermined range, the vertical synchronization signal initialization means outputs a reset pulse to initialize the vertical synchronization signal generation means. do.

Embodiment FIG. 1 is a block diagram showing the main parts for controlling the motor and resetting the vertical synchronization signal of an electronic still camera in an embodiment of the present invention. In Figure 1, 1 is a video floppy, 2 is a PG sensor,
3 is the motor, 4 is the FG, 5 is the F-V conversion circuit, 6
1 is a motor drive circuit, 7 is an N frequency divider circuit, 8 is a phase comparison circuit, 9 is a reference clock signal generation circuit, and 10 is a reference clock signal generation circuit.
PG and 12 are vertical synchronizing signal generating circuits, and their operations are the same as those of the conventional device described above, so a description thereof will be omitted. 11 is a vertical synchronization signal reset pulse generation circuit that generates a reset pulse from the PG signal and _VSYNC .

FIG. 2 is a block diagram for explaining the vertical synchronizing signal reset pulse generating circuit 11, and FIG. 3 is an operational waveform diagram thereof. In Figure 3, I is
The PG signal output from PG10, B is the delayed PG signal whose rising edge is delayed by a predetermined time T ₁ from the rising edge of PG signal A, and C is the delayed PG signal.
Reset pulse to reset V _SYNC , H
After a delay of a predetermined time _T3 from V _SYNC , it is output by the gate pulse generation circuit 14 and has a predetermined pulse width.
This is a gate pulse with T ₄ .

The operation of the electronic still camera of this embodiment configured as described above will be explained below based on the drawings, but the means for stabilizing the rotation of the video floppy 1 is the same as the conventional one, so the explanation will be omitted. .

When the motor 3 starts rotating, the PG signal A is input to the vertical synchronization signal reset pulse generation circuit 11.
As shown in FIG. 3, the delay circuit 15 generates a delayed PG signal L which is delayed by _T1 and whose rising edge is valid, and is input to the timing detection circuit 16. On the other hand, vertical synchronization signal reset pulse generation circuit 1
A gate pulse H having a pulse width of T ₄ is generated by the delay circuit ₁₃ and the gate pulse generation circuit 14 at a position delayed by T 3 from the V _SYNC input to the timing detection circuit 14, and is input to the timing detection circuit 16. The timing detection circuit 16 detects whether the gate pulse H exists at the time when the rising edge of the delayed PG signal LO occurs, and if it does not exist, as shown in _FIGS . A reset pulse is generated at a position delayed by _T2 from the rising edge of the delayed PG signal (b) so that the phase relationship between the two (d) and (d) becomes the desired _T2 . Here, the meanings of the respective delay times T ₁ , T ₂ , T ₃ and the pulse width T ₄ of the gate pulse ho shown in FIG. 3 will be described. T ₁ is the same as T ₁ ' explained in the conventional example, and is for correcting the mechanical positions of the recording head and PG sensor 2 and determining the start of recording the video signal on the video floppy 1. Of course, at this time, recording of the video signal is started at the timing of the rising edge of the delayed PG signal (b), as in the conventional case. T ₂ is used to determine the phase relationship between the rotational phase of the video floppy 1 and V _SYNC 2, as in the prior art, but here it is used to give the center value of this predetermined value. T ₄ is determined from the allowable range of this phase relationship. In other words, the phase range to be maintained is T ₂ ±T ₄ /2, and T ₃ is given by equation (1).

T ₃ =V period−(T ₂ +T ₄ /2) (1) Here, the V period is the period of V _SYNC and is also the rotation period of the video floppy 1 in a steady state. Also, from the above, the time relationship between the trailing edge of gate pulse H and the leading edge of V _SYNC D, which occurs immediately after, is T ₂ −
It becomes T ₄ /2. Therefore, from the above, at the time when the rising edge of delayed PG signal A occurs,
When there is a gate pulse of pulse width T ₄ created by the previous V _SYNC , the V _SYNC and delay PG
This shows that the phase of signal A, that is, the rotational phase of video floppy 1, and V _SYNC D have a predetermined phase relationship.On the other hand, when this does not exist, the phase relationship between the two is shifted, and the reset pulse wave Tsute V _SYNC
It is necessary to reset D and change its phase.

Figure 3a shows the V _SYNC reset operation when the rotational speed of video floppy 1 is slow, that is, the period _T0 of the PG signal A is longer than the V period, and Figure 3b shows the case when it is shorter. Moreover, since T ₀ is shorter than T ₃ , this indicates a state in which no gate pulse H is generated. Figure 3c shows the next delay PG after V _SYNC is reset.
This shows the state when the gate pulse H exists at the time when the rising edge of the signal A occurs. At this time, T ₂
Since +T ₄ /2<T<T ₂ -T ₄ /2, no reset pulse is generated, and if the rotation of video floppy 1 (motor 3) is stable, this phase relationship will be maintained from now on. It will be.

Needless to say, if the polarity of the delayed PG signal (b) is opposite to that of this embodiment, its effective edge will be a falling edge.

As described above, according to the present embodiment, the phases of the delayed PG signal B and V _SYNC D, which should originally be matched, have a predetermined relationship (T ₂ + T ₄ /2<T<T ₂ −T ₄ /2). If the video floppy 1 is not connected, the V _SYNC is reset and checked again in the next V cycle. There is no longer a need to reset V _SYNC when the Therefore, it is possible to bring the signal to the video floppy 1 into a state in which it is possible to record the signal without any loss of time from when the phase is actually pulled in until when _VSYNC is reset as in the conventional case.

Effects of the Invention As explained above, according to the present invention, the rotational phase of the video floppy can be adjusted in the shortest time at any given time.
A predetermined phase alignment with V _SYNC can be performed, making it possible to significantly shorten the time from motor startup to recordable state in most cases compared to before, allowing quick response to shutter changes and lower power consumption. Its practical effects are also significant.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an electronic still camera according to an embodiment of the present invention, FIG. 2 is a block diagram of the vertical synchronization signal reset pulse generation circuit of FIG. 1, and FIG.
4 is a block diagram of a conventional electronic still camera, FIG. 5 is an operational waveform diagram of the phase lock detection circuit of FIG. 4, and FIG. 6 is a diagram of the conventional electronic still camera. FIG. 1...Video floppy, 2...PG sensor,
3...Motor, 4...Frequency generator (FG), 5...
...F-V conversion circuit, 6... Motor drive circuit, 7...
...1/N frequency divider circuit, 8...phase comparison circuit, 9...
Reference clock generation circuit, 10... Rotation phase detector (PG), 11... Vertical synchronization signal reset pulse generation circuit, 12... Vertical synchronization signal generation circuit, 13.
15... Delay circuit, 14... Gate pulse generation circuit, 16... Timing generation circuit.

Claims (1)

[Claims] 1. Means for generating a signal proportional to the rotational speed of a motor that drives a magnetic disk such as a video floppy, and means for dividing this output by N (N≧1);
A reference phase signal generation means serving as a phase reference for this N-divided output, a motor control means for controlling the rotation of the motor so that the reference phase signal and the N-divided output have a predetermined phase relationship, and a reset signal. vertical synchronization signal generation means that can be initialized by a vertical synchronization signal, gate pulse generation means that generates a gate pulse of a fixed period after a predetermined time delay from the vertical synchronization signal, and rotational phase signal detection means that detects the rotational phase of the magnetic disk; A delay means generates a signal delayed by a predetermined time from the rotational phase signal, and detects whether the time relationship between the delayed signal and the gate pulse is within a predetermined range, and outputs a reset pulse when it is outside the range. An electronic still camera comprising vertical synchronization signal initial setting means for initializing the vertical synchronization signal generation means. 2. The electronic still camera according to claim 1, wherein the vertical synchronization signal initial setting means is configured so that the reset pulse is generated after a predetermined time has elapsed from the output signal of the delay means. 3. Detecting whether the time relationship between the delay means and the gate pulse is within a predetermined range is performed by determining whether the gate pulse is present at the time when the leading edge or trailing edge of the delayed signal occurs. The electronic still camera according to claim 1, wherein the vertical synchronization signal initial setting means is configured as follows.