JPH04142795A - Multilayer wiring board - Google Patents

Multilayer wiring board

Info

Publication number
JPH04142795A
JPH04142795A JP26675090A JP26675090A JPH04142795A JP H04142795 A JPH04142795 A JP H04142795A JP 26675090 A JP26675090 A JP 26675090A JP 26675090 A JP26675090 A JP 26675090A JP H04142795 A JPH04142795 A JP H04142795A
Authority
JP
Japan
Prior art keywords
signal
layer
pattern
wiring board
multilayer wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP26675090A
Other languages
Japanese (ja)
Inventor
Tatsuo Sato
達夫 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP26675090A priority Critical patent/JPH04142795A/en
Publication of JPH04142795A publication Critical patent/JPH04142795A/en
Pending legal-status Critical Current

Links

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)

Abstract

PURPOSE:To reduce noises induced by an electromagnetic coupling between signal patterns to a minimum so as to enable a multilayer wiring board to transmit signals well by a method wherein a conductor is provided on both the sides of the signal patterns along the direction of the pattern. CONSTITUTION:A signal pattern 5 is arranged in a signal layer 3, the same ground layers 2 and 4 are provided adjacent to both the sides of the pattern 5 along the direction of the pattern 5, the same power supply layers 8 and 9 are provided, and conductors 7 are provided to connect the ground layers 2 and 4 together or the power supply layers 8 and 9 together. That is, the signal layer 3 is sandwiched between the ground layers 2 and 4 through the intermediary of an interlaminar insulating layer 1, and signal patterns 5 and 7 are provided to the signal layer 3. The conductors 7 connected to the ground layers 2 and 4 are provided on both the sides of the signal pattern 5. The conductors 7 are provided along the direction of the signal pattern 5.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は多層配線基板に関し、特に高速信号の伝送に適
用される多層配線基板に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a multilayer wiring board, and particularly to a multilayer wiring board applied to high-speed signal transmission.

〔従来の技術〕[Conventional technology]

従来、この種の多層配線基板は、第2図(a)に断面図
で示すように、信号層13の上下に層間絶縁層11を介
してグランド層12及び電源層18がそれぞれ積層配置
されている。さらに第2図(b)に平面図で示すように
、信号層13には多数の信号パターン15.16があり
、それら相互の電磁結合によるノイズを避けるため、信
号パターン15に沿ってGNDパターン17を設けてい
た。GNDパターン17はスルーホール21を介してグ
ランド層12に接続され、またこの多層配線基板20に
は他にグランド層14.電源層19が設けられていた。
Conventionally, in this type of multilayer wiring board, a ground layer 12 and a power supply layer 18 are laminated above and below a signal layer 13 with an interlayer insulating layer 11 in between, as shown in a cross-sectional view in FIG. 2(a). There is. Further, as shown in a plan view in FIG. 2(b), the signal layer 13 has a large number of signal patterns 15 and 16, and in order to avoid noise due to mutual electromagnetic coupling, a GND pattern 17 is placed along the signal pattern 15. was established. The GND pattern 17 is connected to the ground layer 12 via a through hole 21, and the multilayer wiring board 20 also has a ground layer 14. A power supply layer 19 was provided.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の多層配線基板は、当該信号線にグランド
に接続されたパターンを沿わせることだけにより他の信
号線との電磁結合によるノイズを避けるという構造をと
っていたため、この電磁結合の遮蔽効果が弱いという欠
点がある。
The conventional multilayer wiring board mentioned above has a structure that avoids noise caused by electromagnetic coupling with other signal lines by simply placing a pattern connected to the ground along the signal line, so the effect of shielding this electromagnetic coupling is The disadvantage is that it is weak.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は信号層と、この信号層の上下に層間絶縁層を介
して積層配置された同一グランド層又は同一電源層を有
する多層配線基板において、前記信号層内に配置された
信号パターンと、この信号パターンの両側近傍にパター
ン方向に沿って設けられ且つ前記信号層の上下に設けら
れた前記同一グランド層又は前記同一電源層同志を接続
する少なくとも1個の導体とを備えている。
The present invention provides a multilayer wiring board having a signal layer and the same ground layer or the same power layer layered above and below the signal layer with an interlayer insulating layer in between. At least one conductor is provided near both sides of the signal pattern along the pattern direction and connects the same ground layer or the same power layer provided above and below the signal layer.

〔実施例〕〔Example〕

次に、本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図(a)は本発明の一実施例の断面図、第1図(b
)は本実施例における信号層の平面図である。
FIG. 1(a) is a sectional view of one embodiment of the present invention, FIG. 1(b)
) is a plan view of the signal layer in this example.

本実施例は信号層3と、この信号層3の上下に層間絶縁
層1を介して積層配置された同一のグランド層2,4又
は同一の電源層8,9を有する多層配線基板10におい
て、信号層3内に配置された信号パターン5と、この信
号パターン5の両側近傍にパターン方向に沿って設けら
れ且つ同一のグランド層2.4又は同一の電源層8.9
同志を接続する複数の導体7とを有してなる。
In this embodiment, a multilayer wiring board 10 has a signal layer 3 and the same ground layers 2 and 4 or the same power supply layers 8 and 9 which are laminated above and below the signal layer 3 with an interlayer insulating layer 1 in between. A signal pattern 5 arranged in the signal layer 3, and the same ground layer 2.4 or the same power supply layer 8.9 provided along the pattern direction near both sides of the signal pattern 5.
It has a plurality of conductors 7 that connect the conductors.

即ち、信号層3は層間絶縁層1を介してグランド層2.
4に挟まれており、この信号層3には当該の信号パター
ン5及び他の信号パターン6が設けられている。信号パ
ターン5の両側にはグランド層2,4に接続された複数
の導体7がある。第1図(b)に示す信号層3の平面図
で明らかなように、導体7は信号パターン5のパターン
方向に沿って設けられている。
That is, the signal layer 3 is connected to the ground layer 2 through the interlayer insulating layer 1.
4, and this signal layer 3 is provided with the corresponding signal pattern 5 and other signal patterns 6. On both sides of the signal pattern 5 are a plurality of conductors 7 connected to the ground layers 2 and 4. As is clear from the plan view of the signal layer 3 shown in FIG. 1(b), the conductor 7 is provided along the pattern direction of the signal pattern 5.

このような本実施例によれば、複数の導体7によって信
号パターン5,6相互の電磁結合が弱められ、信号パタ
ーン5は信号パターン6からのノイズを最小にすること
ができる。
According to this embodiment, the electromagnetic coupling between the signal patterns 5 and 6 is weakened by the plurality of conductors 7, and the signal pattern 5 can minimize noise from the signal pattern 6.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、信号パターンの両側にパ
ターン方向に沿って導体を設けることにより、信号パタ
ーン間の電磁結合を極端に弱めることができ、遮蔽効果
が得られる。したがって信号パターン相互の電磁結合に
よるノイズを最小にすることができ、良好な信号伝送が
可能となる効果がある。
As described above, in the present invention, by providing conductors along the pattern direction on both sides of the signal pattern, electromagnetic coupling between the signal patterns can be extremely weakened, and a shielding effect can be obtained. Therefore, noise due to electromagnetic coupling between signal patterns can be minimized, and there is an effect that good signal transmission is possible.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(a)は本発明の一実施例の断面図、第1図(b
)は本実施例における信号層の平面図、第2図(a)は
従来技術による多層配線基板の一例の断面図、第2図(
b)は従来例における信号層の平面図である。 1.11・・・層間絶縁層、2,4,12.14・・・
グランド層、3.13・・・信号層、5.6.15゜1
6・・・信号パターン、7・・・導体、8,9,18゜
19・・・電源層、10.20・・・多層配線基板、1
7・・・GNDパターン、21・・・スルーホール。
FIG. 1(a) is a sectional view of one embodiment of the present invention, FIG. 1(b)
) is a plan view of the signal layer in this embodiment, FIG. 2(a) is a cross-sectional view of an example of a multilayer wiring board according to the prior art, and FIG.
b) is a plan view of a signal layer in a conventional example. 1.11... interlayer insulating layer, 2, 4, 12.14...
Ground layer, 3.13...Signal layer, 5.6.15゜1
6...Signal pattern, 7...Conductor, 8,9,18°19...Power supply layer, 10.20...Multilayer wiring board, 1
7...GND pattern, 21...Through hole.

Claims (1)

【特許請求の範囲】[Claims]  信号層と、この信号層の上下に層間絶縁層を介して積
層配置された同一グランド層又は同一電源層を有する多
層配線基板において、前記信号層内に配置された信号パ
ターンと、この信号パターンの両側近傍にパターン方向
に沿つて設けられ且つ前記信号層の上下に設けられた前
記同一グランド層又は前記同一電源層同志を接続する少
なくとも1個の導体とを備えることを特徴とする多層配
線基板。
In a multilayer wiring board having a signal layer and the same ground layer or the same power layer layered above and below the signal layer via an interlayer insulating layer, a signal pattern arranged in the signal layer and a signal pattern of this signal pattern are provided. A multilayer wiring board, comprising: at least one conductor provided along the pattern direction near both sides and connecting the same ground layer or the same power supply layer provided above and below the signal layer.
JP26675090A 1990-10-04 1990-10-04 Multilayer wiring board Pending JPH04142795A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP26675090A JPH04142795A (en) 1990-10-04 1990-10-04 Multilayer wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP26675090A JPH04142795A (en) 1990-10-04 1990-10-04 Multilayer wiring board

Publications (1)

Publication Number Publication Date
JPH04142795A true JPH04142795A (en) 1992-05-15

Family

ID=17435192

Family Applications (1)

Application Number Title Priority Date Filing Date
JP26675090A Pending JPH04142795A (en) 1990-10-04 1990-10-04 Multilayer wiring board

Country Status (1)

Country Link
JP (1) JPH04142795A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000216503A (en) * 1998-11-20 2000-08-04 Alps Electric Co Ltd High frequency module and manufacture thereof
JP2016159018A (en) * 2015-03-04 2016-09-05 株式会社三共 Game machine

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2000216503A (en) * 1998-11-20 2000-08-04 Alps Electric Co Ltd High frequency module and manufacture thereof
JP2016159018A (en) * 2015-03-04 2016-09-05 株式会社三共 Game machine

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