JPH0414430B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a clock regeneration device having a phase-locked loop PLL.

Conventional configuration and its problems When processing a video signal reproduced from a VTR or the like, it often happens that a clock synchronized with a horizontal synchronization signal included in the video signal is required. For example, a PLL like the one shown in Figure 1 is used to generate this clock.
circuits are commonly used. In Figure 1, the horizontal synchronizing signal applied from input terminal 1 is input to the phase comparator.
Inputs into one input terminal of PC2. A signal F _H having a frequency equal to the frequency of the horizontal synchronizing signal is input from the 1/N frequency divider 1/N5 to the other input terminal. In PC2, the phase error between the horizontal synchronization signal and the signal _F
Controls the oscillation frequency of VCO4. The clock from VCO 4 is applied to output terminal 6 and 1/N frequency divider 5.

The 1/N frequency divider 5 divides the clock from the VCO 4 by 1/N to generate the signal _FH . That is, the clock frequency fc from the output terminal becomes N× _fH , where fH is _the horizontal synchronization frequency.

Next, a recording/reproducing method for magnetic tape in a VTR will be explained. For convenience, a helical scan type VTR will be explained here. Figure 2 shows
FIG. 2 is a top view of a rotating cylinder used in a helical scan VTR. 7 is a circuit cylinder, and 8 and 9 are magnetic heads A and B, respectively, which are mounted at positions facing each other by 180 degrees on the circumference of the rotary cylinder 7. 10 is a magnetic tape that is wound around the rotating cylinder 7 by more than 180 degrees. Also, arrow 1
1 and 12 indicate the rotational direction of the rotating cylinder 7 and the tape running direction, respectively.

Either magnetic head A8 or magnetic head B9 is always in contact with magnetic tape 10.
That is, the recording pattern on the magnetic tape 10 is as shown in FIG.

Recording tracks 13, 14, 15, and 16 are written on the magnetic tape 10. For example, recording tracks 13 and 15 are trajectories written by the magnetic head A8. 17 indicates the running direction of the magnetic head.

By the way, although the video signal to be recorded on the VTR is a continuous signal, in such a recording method, a switching point occurs in the video signal, for example, at the transition from recording track 13 to track 14. For example, NTSC
If the rotating cylinder is rotated 30 times per second when recording a video signal using this method, the video signal will be recorded in pieces on 60 recording tracks per second, and there will be 60 switching points as described above. Become. In such a case, one recording track contains
Video signals for 265.5 horizontal scanning lines (one field) are recorded. Next, when performing normal reproduction from the magnetic tape 10 recorded as described above, for example, the magnetic heads 8 and 9 are switched alternately to reproduce the signals written on the recording tracks 13, 14, 15, and 16 one after another. Naturally, the video signal obtained as a playback signal has
There are 60 switching points per second. However, because the magnetic tape 10 expands and contracts due to differences in the environment during recording and playback (for example, temperature, humidity, tape tension applied to the magnetic tape 10, etc.), the video signal at this switching point is It is unavoidable that parts are omitted or overlapped (this is called a skew error). PLL when applying to input terminal 1 in the figure
The state will be explained using FIG.

In the figure, 18 is the horizontal synchronization signal applied to input terminal 1, and 19 is the LPF in Figure 1.
3 shows the error voltage waveform of the output line 7, and 20 shows the output waveform of the 1/N frequency divider 5 when the VCO 4 is controlled by the error voltage.

Numbers 1 to 15 written within the waveform 18 indicate examples of horizontal scanning line numbers. Further, the waveform 20 is also numbered to correspond to the horizontal scanning line number. In a state where no skew error occurs and the PLL is operating stably (for example, in the first and second horizontal scanning lines), the falling edges of the waveform 18 and the waveform 20 coincide. However, depending on the configuration of PC2, the falling edges of these waveforms may be stabilized at different positions, but for the sake of simplicity, they are made to match as shown in the figure.

By the way, at the point indicated by arrow 21 in the figure, switching of the magnetic head (head switch) occurs, and 3
Assume that a skew error occurs in the third horizontal scanning line and, for example, as shown in the figure, the time interval of the third horizontal scanning line is extended compared to the other horizontal scanning lines.
Assuming for convenience that the phase comparison operation of PC2 is performed at the falling edge of waveform 18, the skew error that occurs in this third horizontal scanning line will be caused by the PLL until the falling edge at the end of the third horizontal scanning line. The error voltage 19 does not change from point A to point B as shown in the figure. That is, from point A to point B, the VCO 4 repeats oscillation at a constant frequency, so the intervals between the waveforms 20 in this section also occur at the same period. However, at the beginning of the fourth horizontal scanning line, the falling edge of waveform 20 occurs earlier than the falling edge of waveform 18, resulting in a sudden phase advance, and the PLL eliminates this phase error. Therefore, an error voltage 19 from point B to point C in the figure is generated, the frequency of the VCO 4 is controlled to be lowered, the period of the waveform 20 is controlled to be lengthened, and the phase of the waveform 20 is controlled to be delayed.
However, from point C to point E, the PLL is overcontrolled and a phase lag occurs, resulting in VCO4
An error voltage is generated as the frequency increases. After that, this phase advance and phase delay are repeated several times, gradually approaching a stable state.

Generally, the time required for the PLL to settle into a stable state varies depending on the amount of skew and the transfer function of the PLL, but for example, if a skew occurs within 5% of the horizontal synchronization signal interval in the normal state. It takes several tens of hours to several tens of hours to settle down to a steady state (assuming the time interval of one horizontal synchronization signal is 1H).
is necessary.

Therefore, during the period until the steady state is reached, the clock frequency does not become N×f _H.
At the same time as the number of clocks in 1H is no longer N,
Since the output phase of the frequency divider fluctuates greatly with respect to the external horizontal synchronization signal, for example, with this clock, it may be impossible to extract the pixels of the video signal from the VTR and perform image processing. You may not be able to process certain things. For example, in a time axis correction device configured to write a video signal into a sample memory using this clock as a write clock, and read out from the memory using the clock of another oscillation circuit that generates a clock of n×f _H with a stable frequency. is a constant frequency n because when the PLL is in a vibration state, the number of samples within 1H period when writing to the memory increases and decreases around N pieces.
When read from the memory using the xf _H clock, the output video signal of this time axis correction device will expand or contract, causing the image on the TV screen to sway horizontally. (This phenomenon is called skew distortion.) In short, the problems with conventional PLLs are:
The problem was that the response to sudden phase shifts in the external synchronization signal was extremely slow and frequency fluctuations occurred.

Purpose of the Invention The present invention provides a system in which the phase of the PLL instantly responds to sudden phase shifts such as skew errors that occur in external synchronization signals, and the oscillation frequency does not fluctuate.
It is intended to provide PLL configuration.

Structure of the Invention As shown in Fig. 4, in the conventional PLL, after a skew error occurs, there is an oscillation period in the error voltage, the phase of the output of the frequency divider, and the oscillation frequency of the VCO4 until the stable region is reached. The reason why it takes a considerable amount of time is that the 1/N frequency divider 5 overcounts (or undercounts) the VCO 4 clock during the third horizontal scanning period in FIG. The PLL operates in an attempt to eliminate the problem (in the long run (the period from when the error voltage occurs until it reaches stability) by varying the frequency of VCO4 (the period when the error voltage reaches stability), so the error voltage oscillates, and this oscillation occurs over time. The main reason is thought to be that it requires

In the present invention, this over-counting or under-counting in the horizontal scanning line where the skew error has occurred is avoided until the next phase comparison is performed (for example, at the falling edge of waveform 18 in the fourth horizontal scanning period in FIG. 4). The amount corresponding to the above-mentioned overcount or undercount is corrected by correcting the 1/N frequency divider 5, and stable phase comparison is performed even after the skew error occurs, and VCO4
To provide a PLL that does not cause fluctuations in oscillation frequency.

Of course, it is not necessary to correct the 1/N frequency divider 5 within the third horizontal scanning period using FIG. 4 as an example. The above correction may be performed after several tens of hours have passed. However, in this case, the phase comparison operation in the PC 2 is prohibited from the time when the skew occurs until the time when the above correction is performed.

Description of examples An embodiment of the invention is shown in FIG.

Parts common to those in Figure 1 are given the same numbers.
Generally, the 1/N frequency divider 5 is composed of an M-stage binary counter. Here, the integer M is 2 to the M power 2 ^M
is selected so that it is a number greater than or equal to the integer N. By the way, the M-stage binary counter consists of flip-flops (FF ₁ to FF _M ) 21, 22, 23 shown in FIG.
It consists of M flip-flops in total. That is, the internal state of the 1/N frequency divider 5 is M-bit binary data D=(d ₁ , d ₂ . . .
d _M ). Control of the 1/N frequency divider 5 when a skew error occurs as described in the configuration of the present invention is performed by controlling the internal states of M flip-flops in the binary counter. Furthermore, in this embodiment, the control circuit (CONTROL) is activated based on the skew error occurrence detection signal (e.g., head switching signal) applied to the input terminal 24 and the synchronization signal (e.g., horizontal synchronization signal) of the input terminal 1.
25 controls the PC 2, the 1/N frequency divider 5, and the memory element (MEMORY) 26, thereby controlling the phase shift due to the skew error. Fifth
The detailed operation of the figure will be explained using FIG.

Waveform 1 is an external synchronization signal with a skew error applied to input terminal 1, and pulse waveform 24 is a skew error occurrence detection signal applied to input terminal 24. A pulse is generated at the location where head switching occurs.

Further, in order to simplify the explanation of the embodiment, in this embodiment, a sawtooth wave 27 is generated on the signal line 27,
Moreover, this sawtooth wave 27 has an internal state D=(0,
It is a sawtooth wave that starts from 0, 0...0), and it is assumed that the PC2 samples the sawtooth wave 27 at the falling edge of the horizontal synchronization signal applied to the input terminal 1, and controls the VCO4 with this sample voltage. are doing. However, the sawtooth wave 2
7, the horizontal axis is the time axis and the vertical axis is the voltage, and the slope of the sawtooth wave 27 is constant. Also, the internal state D of the 1/N frequency divider 5 is the final state D = (N ₁ ...N _M )
(During internal state 28...explained later), the next state D = (0 ₁ ...0) (starting state of frequency divider)
It is assumed that the sawtooth wave 27 rapidly falls to a certain predetermined voltage.

Furthermore, the internal state 28 indicates the internal state D of the M flip-flops constituting the 1/N frequency divider 5, and represents the internal state D at the time corresponding to the time axis, which is the horizontal axis in FIG. There is.

Reference numeral 29 is a control signal on the signal line 29 in FIG. 5, which is used by CONTROL 25 to inhibit the phase comparison operation of the PC 2, and as shown in the figure, the L period is the period in which the phase comparison operation is prohibited. be. This L period is at least from the time when a pulse is generated in the signal 24 to the phase comparison operation time point (in this example, the sample point) included in the time point (the time point when the internal state of the 1/N frequency divider 5 is changed), which will be described later. It is sufficient if it is L only for the period. 30 is a pulse waveform on the signal line 30 in FIG. The internal state D of the frequency generator 5 (if you refer to the internal state 28, D = (a ₁ ... a _M )) is transmitted via the bidirectional data bus 31.
This is a control signal taken into the MEMORY 26. Naturally, in the stable region before skew occurs, the data in the MEMORY 26 is rewritten every time this pulse is input.

32 is a signal on the signal line 32, and data D=(a ₁ . . . inside the MEMORY 26) is input to the internal state D of the 1/N frequency divider 5 via the bidirectional data bus 31.
a _M ) and rewrites the internal state D.

In this example, a pulse is generated in the signal 32 at the time when the synchronization signal 1 first comes in after the pulse of the signal waveform 24 is generated. The details of the generation position of this pulse are as follows: The time relationship between the pulses of synchronizing signal 1 and signal 30 when no skew occurs is the same as that of the synchronizing signal immediately after skew occurs and the pulse of signal 3.
The time position is set so that the second pulse and the second pulse have the same time relationship.

Looking at the internal state 28 in FIG. 6, the internal state D=(a ₁ ...a _M ) is repeated twice from the time the skew occurs until the control signal 32 is input to the 1/N frequency divider 5. I understand. In other words, from the initial internal state D = (a ₁ ...a _M ) that is repeated twice, 2
The time interval required for the second internal state D=(a ₁ . . . a _M ) is the time width in which the skew error occurs.
In this manner, the structure of the present invention compensates for excessive clock counting.

By performing this compensation, even if skew occurs, the phase relationship between the output phase of the 1/N frequency divider 5 (internal state D) and the external synchronization signal 1 will be the same as when the PLL is operating safely. This matches the above two phase relationships, only the phase shift due to the skew error is compensated, and the subsequent phase of the sawtooth wave 27 and the phase of the synchronization signal 1 are at a stable position, and the inside of the 1/N frequency divider 5 Even if sampling is performed on PC2 after state correction, the steady state error voltage remains and VCO4
Since there is no effect on the oscillation frequency of the PLL, the unstable region of the PLL as shown in FIG. 4 does not occur.

In the explanation of this embodiment, for the sake of simplicity,
For convenience, the position of the write pulse to the MEMORY 26 and the position of the control pulse to the 1/N frequency divider 5 are
It is aligned with the sample point position of PC2, but
In particular, the two pulses mentioned above do not have to be at the sample point; for example, it is easy to shift these two pulses to a position that is shifted by a certain time interval from the external synchronization signal, and the same effect can be obtained.

Also, when setting these two pulses in different positional relationships with respect to the external synchronization signal, the amount of time difference between these pulses should be taken into account.
By subtracting or adding from the data taken into the MEMORY 26, this calculation result may be used to control the internal state of the 1/N frequency divider 4, and similar effects can be obtained.

Furthermore, the internal state of the 1/N frequency divider 5 does not need to be changed at the next synchronization signal position after the occurrence of the skew, but may be done at a time when an appropriate number of synchronization signals have passed. However, in this case, it is necessary to prohibit the phase comparison operation included at the time of changing the internal state and the operation to address the MEMORY 26 from the time the skew occurs. This configuration is also similar to the configuration of the present invention and obtains similar effects.

In short, as shown in the configuration of the present invention, the internal state of the 1/N frequency divider 5 is maintained until the phase comparison operation prohibition period ends after a skew error occurs or until the next phase comparison operation is performed. The internal state of the 1/N frequency divider 5 at the time of the next phase comparison operation is determined by the PLL.
All of these are included in the present invention as long as they match the internal state of the 1/N frequency divider 5 during the phase comparison operation when has reached a steady state, and the same effect can be obtained. .

Effects of the Invention Even if sudden phase fluctuations such as skew errors occur in the synchronization signal, the present invention absorbs these phase fluctuations by controlling the internal state of the frequency divider, thereby reducing instability such as error voltages. to generate a stable clock. This makes it possible to stabilize processing that must be performed using a clock synchronized with a synchronization signal (eg, video signal processing, time axis correction device, etc.). For example, even if a video signal via a time axis correction device is displayed on a monitor screen,
This is an excellent patent with a wide range of applications, as it has great effects such as not causing the horizontal shaking of the screen (skew distortion) as shown in the problems of the conventional example.

[Brief explanation of drawings]

Figure 1 is a block diagram of a conventional PLL, Figure 2 is a plan view of the rotating cylinder viewed from above, Figure 3 is a diagram showing the recording pattern on the magnetic tape, and Figure 4 is a diagram of the conventional example when skew occurs. FIG. 5 is a block diagram of one embodiment of the PLL according to the present invention, and FIG. 6 is a waveform diagram explaining the operation of FIG. 5. 4... Oscillation means, 5... Frequency division means, 2... Phase comparison means, 25... Control means, 26... Storage means.

Claims (1)

[Claims] 1. An oscillation means that generates a clock, a frequency dividing means that is composed of an M-bit counter (M is an integer) and divides the frequency of the clock, and an external synchronizing signal and a frequency-divided signal of the frequency dividing means. A phase-locked loop circuit is provided with a phase comparison means for comparing the phases at timings corresponding to the phase difference, a storage means, and a control means. is detected as a phase fluctuation region of the external synchronization signal, and data corresponding to the internal state of the M-bit counter at the time of phase comparison during a period other than the phase fluctuation region is constantly updated and stored in the storage means; In the phase variation region, the operation of the phase comparison means is stopped from the start time of the phase variation region until at least the phase comparison time, and the data stored in the storage means at the phase comparison time is stored in the M
A clock recovery device that controls the bit counter to set its internal state.