JPH0414503B2 - - Google Patents

Description

[Detailed Description of the Invention] (a) Technical Field of the Invention The present invention relates to a method for manufacturing a semiconductor package,
In particular, the present invention relates to a method of manufacturing a semiconductor package with improved reliability.

(b) Prior art and problems As semiconductor devices have become ICs and LSIs, semiconductor packages have also become larger, internal wiring has become more complex, and ceramic packages have become multilayered. Normally, to produce a multilayer ceramic package, multiple green sheets are laminated and fired, and a tungsten metallization paste, for example, is applied to the surface of the green sheet by a printing method, and through holes are formed in the green sheet where necessary. Then, the paste is applied to the inside of the sheet so as to make an electrical connection between the top and bottom, and these green sheets are stacked and fired. and,
The exposed parts of the fired metallized layer include the parts to be brazed with the external leads, the die stage, and the bonding pads.After the external leads are brazed to the parts to be brazed, the bonding pads and die stages in particular are plated with gold and bonded. Formed on a surface that is easy to move.

Figure 1 illustrates a cross-sectional view of such an RGA (Pin Grid Array) type multilayer ceramic package, where 1 is a metallized layer as a lead conductor inside the multilayer ceramic package, and 2 is an installation for soldering a semiconductor chip. 3 is a bonding pad that is wire-bonded to the electrode of the semiconductor chip installed on the die stage 2, and 4 is a bonding pad that is connected to the metallized layer 1 as a lead conductor, and is connected in a vertical direction from the back surface of the multilayer ceramic package. These external leads are installed in a grid pattern at regular intervals.

By the way, the die stage 2 or the bonding pad 3, the metallized layer 1 and the external leads 4 connected thereto are individually formed into electrically insulated structures when the package is completed. However, since the plating process requires plating at the same time, a common connection part is provided before the plating process, and normally a metallized layer is provided around the four sides of the package, and the inside of the ceramic up to the connection part is A metallized layer for plating is formed on. In FIG. 1, 1' is a metallized layer for plating, and 5 is a common connection metallized layer, and the common connection metallized layer 5 is illustrated in the actual diagram shown in FIG. 2a.

However, although this common connection metallized layer 5 is removed by polishing after the plating process, the connection point with the metallized layer 1' for plating derivation remains as it is after polishing, as shown in the actual diagram shown in FIG. 2b.ゝRemain.

Therefore, even after the semiconductor element is attached and encapsulated, the metallized layer 1' is exposed on the outer surface.
If such a semiconductor device is touched by hand, the metallized layers 1' may be connected to each other, and the semiconductor device may be damaged by electrostatic discharge. For this reason, even if the metallized layer 1' for plating derivation is polished into a concave shape, under a poor environment, migration will occur in this area and the metallized layers 1' will become electrically conductive, resulting in destruction. However, such polishing is a tedious task.

(c) Purpose of the Invention The present invention solves these problems and prevents the semiconductor device from being destroyed due to the metallized layer exposed on the outer peripheral surface of the ceramic package after the semiconductor device is completed. This paper proposes a method for manufacturing a semiconductor package that does not exist before.

(d) Structure of the Invention The object of the invention is to provide a multilayer ceramic package comprising a die stage on which a semiconductor chip to be housed is installed, and a multilayer metallized layer as a lead conductor for a large number of electrodes of the semiconductor chip. A wiring structure is fired in which the stage and all metallized layers are connected around the die stage by a plating lead-out metallized layer, which is a conductor wire, and an external lead is brazed to the metallized layer as a lead conductor, and the die stage and This is achieved by a method of manufacturing a semiconductor package in which, after plating the exposed metallized layer, all metallized layers except a desired metallized layer are cut at the metallized layer connection portion around the die stage.

(e) Embodiment of the invention Hereinafter, one embodiment will be described in detail with reference to the drawings. Figure 3 shows the PGA (Pin Grid) before the plating process, in which multiple raw sheets coated with tungsten metallization paste by a printing method are laminated, fired at a high temperature of approximately 1500℃, and external leads 4 are brazed.
Arry) type package cage cross-sectional view is shown.
The plating lead-out metallized layer 11 connected to the metallized layer 1 as a lead conductor inside the ceramic package is formed up to the periphery of the die stage 2 to form a structure in which it is connected to the die stage 2. Fourth
The figure shows a plan view thereof, and this figure shows all the exposed parts of the metallized layer 11 for plating derivation.

After making such a structure, bringing the plating electrode into contact with any external lead 4, and performing gold plating,
Next, a laser beam is irradiated to melt and cut the connection portion of the gold-plated metallized layer 11 for plating.
FIG. 5 shows a plan view of the cut die stage part. For example, when connecting the die stage 2 to the external lead 4 in order to ground it, the desired metallized layer 11' is cut as shown in the figure. Leave it without. Further, instead of fusing with a laser beam, a trimmer (sandblast) used for trimming a resistor on a ceramic circuit board may be used to cut the connection portion. FIG. 6 shows a cross-sectional view of a package cut and formed by these methods.

(f) Effects of the Invention As is clear from the above embodiments, according to the method of manufacturing a semiconductor package according to the present invention, the remaining metallized layer used in the plating process on the outer surface of the package is exposed to the outside after the cap is sealed. Since it is no longer exposed, the semiconductor elements housed inside and assembled are not destroyed, which greatly contributes to improving the reliability of the semiconductor device.

It goes without saying that the present invention can also be applied to ceramic packages other than the PGA type.

[Brief explanation of drawings]

Fig. 1 is a sectional view of a conventional ceramic package, Fig. 2 a and b are actual views showing the problems thereof,
3 and 4 are a cross-sectional view and a plan view of a ceramic package according to the present invention before the plating process, and FIGS. 5 and 6 are views of the plating lead-out metallized layer cut after the plating process. FIG. 2 is a partial plan view and a sectional view according to the invention. In the figure, 1 is a metallized layer as a lead conductor;
2 is a die stage, 3 is a bonding pad, 4 is an external lead, 5 is a common connection metallization layer, 1',
Reference numeral 11 indicates a metallized layer for plating.

Claims (1)

[Scope of Claims] 1. A multilayer ceramic package comprising a die stage 2 on which a semiconductor chip to be housed is placed, and a metallized layer 1 as a lead conductor for a large number of electrodes of the semiconductor chip. 2 and all metallized layers 1
around the die stage 2 to form a wiring structure in which they are connected by a plating lead-out metallized layer 11 which is a conductor wire, the external lead 4 is brazed to the metallized layer 1, and the die stage 2 and the exposed metallized layer 1 are fired. After plating, the above die stage 2
A method for manufacturing a semiconductor package, comprising the step of cutting all metallized layers 11 except for a desired metallized layer 11' at a connecting portion of the surrounding metallized layers.