JPH0414504B2 - - Google Patents
Info
- Publication number
- JPH0414504B2 JPH0414504B2 JP59156803A JP15680384A JPH0414504B2 JP H0414504 B2 JPH0414504 B2 JP H0414504B2 JP 59156803 A JP59156803 A JP 59156803A JP 15680384 A JP15680384 A JP 15680384A JP H0414504 B2 JPH0414504 B2 JP H0414504B2
- Authority
- JP
- Japan
- Prior art keywords
- laminated substrate
- heat dissipation
- semiconductor device
- semiconductor element
- substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/69—Insulating materials thereof
- H10W70/692—Ceramics or glasses
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/071—Connecting or disconnecting
- H10W72/075—Connecting or disconnecting of bond wires
- H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/551—Materials of bond wires
- H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
- H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Ceramic Products (AREA)
- Compositions Of Oxide Ceramics (AREA)
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に放熱性に優れ
た絶縁性積層基板を有する半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having an insulating laminated substrate with excellent heat dissipation.
従来、絶縁基板の凹部内に、ICやLSI等の半導
体素子を固着し、リードを接続したのちその上部
をセラミツク板または金属板でシールする気密封
止構造の半導体装置は、樹脂封止の半導体装置と
共に広く使用されている。
Conventionally, semiconductor devices have an airtight structure in which a semiconductor element such as an IC or LSI is fixed in a recess of an insulating substrate, and after connecting leads, the top is sealed with a ceramic plate or metal plate. Widely used with equipment.
半導体素子を固着する絶縁基板には熱伝導率が
大きいことが要求されるが、この外に、絶縁性に
優れ、機械的強度が大きく、更に熱膨張係数がシ
リコンに近い等の条件が満たされることが必要で
ある。現在は、これらの条件をある程度満たすも
のとしてアルミナ基板が主に用いられている。 The insulating substrate that fixes semiconductor elements is required to have high thermal conductivity, but in addition to this, other conditions must be met, such as excellent insulation, high mechanical strength, and a coefficient of thermal expansion close to that of silicon. It is necessary. Currently, alumina substrates are mainly used as substrates that satisfy these conditions to some extent.
しかしながら、アルミナ基板は、特に放熱性が
悪いため、バイポーラICやGaAsIC等の消費電力
の大きな半導体素子の大規模化、高集積化を図る
上で大きな障害となる欠点があつた。 However, alumina substrates have a drawback in that they have particularly poor heat dissipation properties, which poses a major obstacle in increasing the scale and integration of semiconductor devices with high power consumption, such as bipolar ICs and GaAs ICs.
この半導体装置の放熱特性を改善する方法の一
つに、アルミナ基板の周囲に放熱板を取付けるこ
とが提案され実施されているが、部品点数が多く
なり、装置が大型化すると共に、組立工数が多く
なる欠点がある。従つて、放熱特性の改善された
絶縁基板の出現が望まれていた。 One method to improve the heat dissipation characteristics of semiconductor devices is to attach a heat dissipation plate around the alumina substrate, but this increases the number of parts, increases the size of the device, and increases the number of assembly steps. There are many drawbacks. Therefore, there has been a desire for an insulating substrate with improved heat dissipation characteristics.
本発明の目的は、上記欠点を除去し、放熱性の
優れた絶縁基板を有する半導体装置を提供するこ
とにある。
An object of the present invention is to eliminate the above drawbacks and provide a semiconductor device having an insulating substrate with excellent heat dissipation.
本発明の半導体装置は、窒化アルミニウムを主
成分とする絶縁性積層基板と、この積層基板の凹
部に固着された半導体素子とを含んで構成され
る。
The semiconductor device of the present invention includes an insulating laminated substrate containing aluminum nitride as a main component and a semiconductor element fixed in a recessed portion of the laminated substrate.
窒化アルミニウム(AlN)の積層基板の内部
には金属配線が形成されており、半導体素子とワ
イヤにより接続され、そしてこの金属配線は外部
リードに接続する構造となつている。 Metal wiring is formed inside the aluminum nitride (AlN) laminated substrate, and is connected to a semiconductor element by a wire, and this metal wiring is connected to an external lead.
この積層基板は、AlNの粉末に添加剤として、
Ca,Sr,Baのアセチリド化合物の1種以上を含
み、その含有量が合計で0.002〜10重量%である
ことが望ましい。 This laminated board is made by adding additives to AlN powder.
It is desirable that the composition contains at least one type of acetylide compound of Ca, Sr, and Ba, and the total content thereof is 0.002 to 10% by weight.
次に本発明の実施例を図面を用いて説明する。 Next, embodiments of the present invention will be described using the drawings.
第1図は本発明の一実施例の断面図である。 FIG. 1 is a sectional view of an embodiment of the present invention.
第1図において、AlNを主成分とする絶縁性
積層基板1の凹部には半導体素子2がソルダ等に
より固着されている。そして、半導体素子2の電
極は金線3により積層基板1内に形成された金属
配線4に接続されており、更に金属配線4は、積
層基板1の側面に形成されたメタライズ層5を介
してリード6に接続されている。そして、積層基
板1の上部には、ソルダ7により、例えば42合金
よりなる金属キヤツプ8が気密にシールされてい
る。 In FIG. 1, a semiconductor element 2 is fixed to a recessed portion of an insulating laminated substrate 1 mainly composed of AlN by solder or the like. The electrodes of the semiconductor element 2 are connected to metal wiring 4 formed in the laminated substrate 1 by gold wires 3, and the metal wiring 4 is further connected via a metallized layer 5 formed on the side surface of the laminated substrate 1. Connected to lead 6. A metal cap 8 made of, for example, a 42 alloy is hermetically sealed on the top of the laminated substrate 1 with a solder 7.
ここで用いられる積層基板1は例えば次のよう
な工程により作ることができる。 The laminated substrate 1 used here can be made, for example, by the following steps.
まず、95%以上の高純度AlN粉末(粒径10μm
以下)に、Ca,Sr,Baのアセチリド化合物の1
種以上を0.02〜10重量%と、有機ビヒクルとを加
えて混合したのちローラを通して生シートを形成
する。 First, high purity AlN powder of 95% or more (particle size 10 μm)
(below), one of the acetylide compounds of Ca, Sr, and Ba
0.02 to 10% by weight of seeds and organic vehicle are added and mixed, and then passed through a roller to form a green sheet.
次にこの生シートを100〜200℃で乾燥させたの
ち、生シート上の所定部に厚膜法により金属配線
を印刷し形成する。続いて所定枚数の生シートを
重ね、約100℃,200〜300Kg/cm2の条件で熱圧着
したのち、N2ガス等の非酸化性雰囲気で、1800
℃、2時間焼成する。 Next, this green sheet is dried at 100 to 200°C, and then metal wiring is printed and formed on a predetermined portion of the green sheet by a thick film method. Next, a predetermined number of green sheets were stacked and thermocompressed at approximately 100℃ and 200 to 300Kg/cm 2 , and then heated to 1800℃ in a non-oxidizing atmosphere such as N 2 gas.
Bake at ℃ for 2 hours.
このようにして作られたAlNの積層基板1の
特性は、熱伝導率70〜140W/mk、比抵抗1013Ω
cm、機械的強度(曲げ強度)50Kg/mm2、熱膨張率
4.3×10-6/℃であつた。これらの値を従来のア
ルミナ基板のものと比較すると、熱伝導率が4〜
6倍、機械的強度が1.5倍、熱膨張率が3/4で
あり、いずれも絶縁基板として優れた特性を示し
た。 The properties of the AlN laminated substrate 1 made in this way are a thermal conductivity of 70 to 140 W/mk and a specific resistance of 10 13 Ω.
cm, mechanical strength (bending strength) 50Kg/mm 2 , coefficient of thermal expansion
The temperature was 4.3×10 -6 /℃. Comparing these values with those of conventional alumina substrates, the thermal conductivity is 4 to 4.
The mechanical strength was 1.5 times higher, and the thermal expansion coefficient was 3/4, all of which exhibited excellent properties as an insulating substrate.
第2図は、添加剤としてのCa,Sr,Baのアセ
チリド化合物の添加量と熱伝導率との関連を示し
たものである。第2図に示されるように、CaC2
を用いた場合が最も熱伝導率は高いが、添加量と
熱伝導率との関係曲線は全て類似しており、添加
量が2〜3%の所にピークがある。第2図では各
単体のアセチリド化合物の特性について示した
が、これらが混合されて添加された場合でもほぼ
同様の加重平均的な値が得られた。 FIG. 2 shows the relationship between the amount of Ca, Sr, and Ba acetylide compounds added as additives and the thermal conductivity. As shown in Figure 2, CaC 2
The thermal conductivity is the highest when the amount of addition is used, but the relationship curves between the amount added and the thermal conductivity are all similar, and there is a peak at the amount of addition of 2 to 3%. Although FIG. 2 shows the characteristics of each individual acetylide compound, almost the same weighted average values were obtained even when a mixture of these compounds was added.
このように本発明による半導体装置は、金属配
線を印刷したAlNの生シートから絶縁基板が作
られているため、放熱特性がよく、バイポーラ
IC、GaAs IC等の電力消費量の多い半導体装置
の高集積化を可能とする。また、機械的強度も従
来のアルミナ基板以上に優れており、熱膨張率も
Siに近いため、熱サイクルに伴う半導体素子への
熱歪の発生も少く、信頼性の高い半導体装置が得
られる。 In this way, the semiconductor device according to the present invention has good heat dissipation characteristics because the insulating substrate is made from a raw AlN sheet printed with metal wiring, and is bipolar.
This enables high integration of semiconductor devices that consume a lot of power, such as ICs and GaAs ICs. In addition, its mechanical strength is superior to that of conventional alumina substrates, and its coefficient of thermal expansion is also superior to that of conventional alumina substrates.
Since it is close to Si, there is less thermal strain on the semiconductor element due to thermal cycles, and a highly reliable semiconductor device can be obtained.
以上詳細に説明したように、本発明によれば、
窒化アルミニウムからなる積層板を絶縁基板とし
て用いることにより、放熱性に優れ信頼性の高い
半導体装置が得られるのでその効果は大きい。
As explained in detail above, according to the present invention,
By using a laminate made of aluminum nitride as an insulating substrate, a semiconductor device with excellent heat dissipation and high reliability can be obtained, which is highly effective.
第1図は本発明の一実施例の断面図、第2図は
AlN中の添加剤の割合と熱伝導率との関連を示
す図である。
1……積層基板、2……半導体素子、3……金
線、4……金属配線、5……メタライズ層、6…
…リード、7……ソルダ、8……金属キヤツプ。
Fig. 1 is a sectional view of an embodiment of the present invention, and Fig. 2 is a sectional view of an embodiment of the present invention.
FIG. 3 is a diagram showing the relationship between the proportion of additives in AlN and thermal conductivity. DESCRIPTION OF SYMBOLS 1... Laminated substrate, 2... Semiconductor element, 3... Gold wire, 4... Metal wiring, 5... Metallized layer, 6...
...Lead, 7...Solder, 8...Metal cap.
Claims (1)
のアセチリド化合物の1種以上を1〜4重量%含
む絶縁性積層基板と、該積層基板の凹部に固着さ
れた半導体素子とを含むことを特徴とする半導体
装置。1 Aluminum nitride is the main component, including Ca, Sr, and Ba.
1. A semiconductor device comprising: an insulating laminated substrate containing 1 to 4% by weight of one or more acetylide compounds; and a semiconductor element fixed to a recess of the laminated substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15680384A JPS6135539A (en) | 1984-07-27 | 1984-07-27 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15680384A JPS6135539A (en) | 1984-07-27 | 1984-07-27 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6135539A JPS6135539A (en) | 1986-02-20 |
| JPH0414504B2 true JPH0414504B2 (en) | 1992-03-13 |
Family
ID=15635662
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15680384A Granted JPS6135539A (en) | 1984-07-27 | 1984-07-27 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6135539A (en) |
Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE3604075A1 (en) * | 1986-02-08 | 1987-08-13 | Bosch Gmbh Robert | PACKING OF POWER COMPONENTS |
| JPS6318648A (en) * | 1986-07-11 | 1988-01-26 | Toshiba Corp | Circuit board using aluminum nitride |
| JPS63244653A (en) * | 1987-03-31 | 1988-10-12 | Toshiba Corp | Semiconductor device |
| JPH02192198A (en) * | 1989-01-20 | 1990-07-27 | Nippon Cement Co Ltd | Multilayer interconnection board mounted with ic chip |
| JPH0344310U (en) * | 1989-08-31 | 1991-04-24 | ||
| JPH09172108A (en) * | 1996-12-24 | 1997-06-30 | Toshiba Corp | Aluminum nitride circuit board |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS50148965U (en) * | 1974-05-27 | 1975-12-10 | ||
| JPS54100410A (en) * | 1978-01-24 | 1979-08-08 | Tokyo Shibaura Electric Co | Ceramic heat conductor |
| JPS5530815A (en) * | 1978-08-25 | 1980-03-04 | Toshiba Corp | Semiconductor containing vessel |
| JPS60178647A (en) * | 1984-02-27 | 1985-09-12 | Toshiba Corp | Semiconductor device |
-
1984
- 1984-07-27 JP JP15680384A patent/JPS6135539A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6135539A (en) | 1986-02-20 |
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