JPH04145657A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a resistance element having arbitrary temperature characteristic without limiting the value of a specific resistance and to facilitate temperature compensation of a resistance value in design of a circuit by connecting resistors each having different temperature dependence in parallel. CONSTITUTION:A resistor is formed of a substrate 1 provided in a P-type silicon substrate 1, an N-type diffused layer 5 as a reverse conductivity type impurity layer and a P-type polycrystalline silicon layer 4a having reverse temperature dependency of a resistance to that of the layer 5 as a parallel resistance circuit. That is, the resistors having different temperature dependences are connected in parallel to form a resistance having small temperature dependence. The resistors having different temperature dependences are connected in parallel in a using temperature range to be an object to obtain the resistors having arbitrary temperature dependence, thereby approaching the temperature dependence to zero. Thus, since the resistor having small temperature dependence, the resistor having arbitrary temperature dependence can be formed without limit the value of the specific resistance, the temperature compensation of the resistance value can be facilitated.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a resistance element for integrated circuits, and more particularly to a resistance structure that can obtain arbitrary temperature characteristics without being influenced by the value of specific resistance.

[Conventional technology 1] Conventional semiconductor devices are described in the literature "Analysis and Design of Analog Integrated Circuits, by Gray and Meyer, 1984, published by John Wiley and Sons, pp. 112-119.
nalog Integrated C1rcuits
, PP112-119.2nd-Edi, , Gray
and Meyer, 1984. John Viley
&5ons, Inc.) and Section 5(a) of this specification.
) and FIG. 5(b), a resistor was formed using only one of an impurity diffusion layer provided in a semiconductor substrate or a polycrystalline silicon layer provided on an insulating film. For this reason, for example, in order to obtain high resistance, if the impurity concentration is lowered, the temperature dependence of the resistance value deteriorates. [Problems to be Solved by the Invention] It is known that the resistance value of resistance elements used in conventional integrated circuits changes depending on temperature. Special number. When the specific resistance is increased to obtain a high resistance value, this phenomenon becomes noticeable and becomes a major problem in circuit design. An object of the present invention is to provide a resistance element having arbitrary temperature characteristics without being limited by the specific resistance value.

[Means to solve the problem]

The above object is achieved by combining two or more types of e-resistance layers having different temperature characteristics. As shown in FIG. 1, a diffused resistor formed in a single crystal silicon layer has a positive temperature dependence above normal temperature (room temperature), and a negative temperature dependence at lower temperatures. On the other hand, a polycrystalline silicon layer with an impurity concentration of less than lXl01''/C■3 has a negative temperature dependence, and a polyguide layer (or silicide layer) has a positive temperature dependence. By connecting resistors in parallel, a resistor with little temperature dependence is realized.Furthermore, by changing the shape of both paper anti-layers depending on the layout, it is possible to form a resistor with arbitrary temperature dependence.

[Effect]

By combining two or more types of resistance layers with different temperature characteristics, it is possible to form a resistance with little temperature dependence or even a resistance with arbitrary temperature dependence. As a result, temperature compensation of the resistance value becomes easy in circuit design. Furthermore, since the resistor can be placed at any position relative to the element that generates a large amount of heat, the degree of freedom in layout is increased. This allows operation over a wider range of temperatures than in the past.

【Example】

Example 1 A first example of the present invention is shown in FIG. The resistor of this embodiment is formed by an impurity layer 5 provided in a semiconductor substrate and having a conductivity type opposite to that of the substrate, and a polycrystalline silicon layer 4 whose resistance has a temperature dependence opposite to that of the impurity layer, and is formed into a parallel resistance circuit. By using acid, the temperature dependence of resistance is improved. That is, in the conventional structure, either monocrystalline silicon or polycrystalline silicon is used as a resistor, which has the disadvantage that, for example, when the impurity concentration is lowered in order to obtain high resistance, the resistance value fluctuates greatly. As is clear from FIG. 4, in the present invention, by connecting resistors with different temperature dependencies in parallel, it is possible to form a resistor with little temperature dependence. Normally, a diffused resistor formed in a single crystal silicon layer has a positive temperature dependence above normal temperature (room temperature), and a negative temperature dependence at lower temperatures.On the other hand, when the impurity concentration is below 1 The polycrystalline silicon layer has a negative temperature dependence, and the polycide layer (or silicide layer) has a positive temperature dependence. Therefore, within the intended operating temperature range, different temperatures can be used as shown in Figure 1. By connecting dependent resistors in parallel,
It becomes possible to obtain any temperature-dependent resistance. In other words, the temperature dependence can be brought close to zero. For example, the absolute value of +100℃ is 11.2Ω, +100℃
Temperature dependence of ±50℃ +10.4%, -6.8% single crystal silicon diffused resistance, and the above value becomes 27Ω, -19.5
By connecting polycrystalline silicon resistors of % and +24.2% in parallel, it is possible to obtain a resistance with an absolute value of 7.9 Ω and a temperature dependence of +100°C ± 50°C within ±0.5%. . Furthermore, the absolute value of -1oo℃ is 10.9 kΩ, -10
0'Cf50''C(7) Temperature dependence -6.0%, +9.
6% single crystal silicon diffused resistance and the above value is 6.5Ω
By connecting polycrystalline silicide resistors of , +5.6% and -4.7% in parallel, the absolute value is 4.0 kΩ, -100℃±
It becomes possible to obtain a resistance with a temperature dependence of 50° C. within ±0.5%. 6 to 8 show the manufacturing process of the semiconductor device according to this embodiment, and show the steps up to the cross-sectional structure of FIG. 1. Furthermore, FIGS. 9 and 10 show examples of application to conventional bipolar integrated circuits. The manufacturing process and application examples will be explained below according to the drawing numbers. First, a silicon nitride film 3 is deposited on a desired portion of a P-type Si substrate l.
will be established. Thereafter, a silicon dioxide film 2 is provided using a selective oxidation method (FIG. 6).Next, a polycrystalline silicon layer 4a is formed on the surface of the semiconductor substrate. Thereafter, the polycrystalline silicon layer is doped with arsenic or phosphorus as an N-type impurity, and heat treatment is performed to form an N-type diffusion layer 5. Thereafter, the polycrystalline silicon is patterned (FIG. 7) to form a silicon dioxide layer 6 on the surface of the semiconductor substrate, and a contact hole is formed on the polycrystalline silicon layer using a well-known photoetching technique. After this,
An AQ electrode 7 is formed to cover the contact hole,
As shown in FIG. 1, a semiconductor device having arbitrary temperature dependence of resistance can be realized. Note that, of course, the same structure can be obtained even if the n-type diffusion layer 5 is formed before the polycrystalline silicon layer 4 is formed in this embodiment. 9 to 11 show examples of application of the semiconductor device of the present invention to bipolar integrated circuits. FIG. 9 shows that the present invention can be applied without a significant increase in the number of steps by using the polycrystalline silicon layer 4b also as the emitter of a bipolar transistor. In FIG. 10, the polycrystalline silicon layer 4a also serves as the base of the bipolar transistor, and in FIG. 11, the polycrystalline silicon layer 4b serves as the emitter of the bipolar transistor, and the polycrystalline silicon layer 4a serves as the bipolar transistor's base. This shows that the present invention can be applied without significantly increasing the number of steps by using it also as a base. Example 2 In the second example, the diffusion layer resistor shown in Example 1 is of the same conductivity type as the semiconductor substrate.
As is clear from the figure, a resistor of a desired conductivity type can be formed regardless of the conductivity type of the semiconductor substrate. Furthermore, P
By reducing the concentration of the N-junction isolation region, parasitic capacitance and substrate bias effects can be reduced. 12 to 14 show the manufacturing process of the semiconductor device according to this embodiment, and show the state before the cross-sectional structure of FIG. 2 is obtained. The manufacturing process will be explained below according to the drawing numbers. First, a silicon dioxide film 2 is deposited on a desired portion of a P-type Si substrate 1.
will be established. Thereafter, arsenic or phosphorus, which is an N-type impurity, is diffused from the surface of the substrate to form an N-type diffusion layer 10 (FIG. 12). Next, a polycrystalline silicon layer 4b is provided on a desired portion of the substrate surface using well-known photoetching and dry etching techniques. Thereafter, the surface of the substrate is doped with boron and heat treated to form a P-type diffusion layer 8 (FIG. 13).Furthermore, a silicon dioxide layer 6 is formed on the surface of the semiconductor substrate using a well-known photoetching technique. A contact hole is formed on the polycrystalline silicon layer and the P-type diffusion layer. After that, the AM electrode 7 is placed so as to cover the contact hole.
As shown in FIG. 2, it is possible to realize a semiconductor device that is electrically isolated from the semiconductor substrate and has arbitrary temperature dependence of resistance. Example 3 A third example is shown in FIG. In this example, in the semiconductor device shown in the first and second examples, an insulating film is provided between the impurity layer provided in the semiconductor substrate and the upper polycrystalline silicon layer. A semiconductor device characterized by having a polycrystalline silicon layer and a polycrystalline silicon layer. below,
The manufacturing process of the semiconductor device according to this embodiment will be explained in accordance with the drawing numbers using FIG. 15 and FIG. 17. First, a silicon dioxide film 2 is deposited on a desired portion of a P-type Si substrate 1.
will be established. Thereafter, arsenic or phosphorus, which is an impurity other than N, is diffused from the substrate surface to form an N-type diffusion layer 10, and a silicon dioxide layer 9 is further provided on the semiconductor surface (FIG. 15). Next, polycrystalline silicon 4b is provided on the surface of the substrate, doped with boron as a P-type diffusion layer, and subjected to heat treatment. Thereafter, using well-known photoetching and dry etching techniques, the polycrystalline silicon reservoir is processed (patterned) as shown in FIG. Furthermore, a silicon dioxide layer 6 was formed on the surface of the semiconductor substrate, and contact holes were formed on the polycrystalline silicon layer and the N-type diffusion layer. Thereafter, an AQ electrode 7 is formed to cover the contact hole, and as shown in FIG. 3, a semiconductor device having a polycrystalline silicon layer of any conductivity type and further having any temperature dependence of resistance. can be realized. Note that even if all the N-type and P-type conductivity types are reversed in the above embodiment, the polycrystalline silicon layer is further replaced by a polycide layer (
It goes without saying that the present invention is also applicable even if it is replaced with a silicide layer (or a silicide layer).

【Effect of the invention】

According to the present invention, by combining two or more types of resistance layers having different temperature characteristics, it is possible to form a resistance with little temperature dependence or even a resistance with arbitrary temperature dependence. As a result, it is possible to realize a semiconductor device whose resistance value can be easily compensated for temperature in terms of circuit design.

[Brief explanation of the drawing]

1 is a cross-sectional view of a semiconductor device according to a first embodiment, FIG. 2 is a cross-sectional view of a semiconductor device according to a second embodiment, FIG. 3 is a cross-sectional view of a semiconductor device according to a third embodiment, and FIG. Figures 5(a) and 5(b) are temperature characteristic diagrams of resistance showing the basic concept of the present invention.
The figure is a cross-sectional view of a semiconductor device showing a conventional structure, Figures 6 to 8.
The figure is a sectional view showing the manufacturing process of a semiconductor device according to the first embodiment, FIGS. 9 to 11 are sectional views showing a bipolar integrated circuit to which the first embodiment is applied, and FIGS. 12 to 14 are A cross-sectional view showing a manufacturing process of a semiconductor device according to a second embodiment,
15 to 17 are cross-sectional views showing the manufacturing process of the semiconductor device according to the third embodiment. Explanation of symbols 1...P-type silicon substrate 2.6, 9, 11...Silicon dioxide layer 3...Silicon nitride layer 4a...N-type polycrystalline silicon layer 4b...P-type polycrystalline silicon Layers 5.10, 12, 15...N-type diffusion layer 7...AQ electrode layer 8.14...P-type diffusion layer 13...N-type epitaxial layer --- Figure 4 Temperature T (℃) (a) Figure 4 Temperature (''C) (b) Figure 5 (a) (b) Figure 12 Figure 13 Figure 15 Figure 16

Claims (1)

[Claims] 1. A parallel resistance circuit formed by an impurity layer provided in a semiconductor substrate and a polycrystalline silicon layer or polycide layer having a resistance temperature dependence opposite to that of the impurity layer. semiconductor devices. 2. The semiconductor device according to claim 1, wherein a polycrystalline silicon layer or a polycide layer is provided above the impurity layer provided within the semiconductor substrate. 3. The semiconductor device according to claim 2, further comprising a polycrystalline silicon layer of a conductivity type opposite to that of the impurity layer provided in the semiconductor substrate. 4. The semiconductor device according to claim 2 or 3, further comprising an insulating film between the impurity layer provided in the semiconductor substrate and the upper polycrystalline silicon layer or polycide layer. 5. Claim 1 characterized in that it has arbitrary temperature characteristics.
5. The semiconductor device according to any one of 4 to 4.