JPH04145672A - Superconductive element and method of producing the same - Google Patents

Superconductive element and method of producing the same

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Publication number
JPH04145672A
JPH04145672A JP2270070A JP27007090A JPH04145672A JP H04145672 A JPH04145672 A JP H04145672A JP 2270070 A JP2270070 A JP 2270070A JP 27007090 A JP27007090 A JP 27007090A JP H04145672 A JPH04145672 A JP H04145672A
Authority
JP
Japan
Prior art keywords
superconducting
thin film
oxide
protrusion
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2270070A
Other languages
Japanese (ja)
Other versions
JP2641975B2 (en
Inventor
Takao Nakamura
孝夫 中村
Hiroshi Inada
博史 稲田
Michitomo Iiyama
飯山 道朝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
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Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP2270070A priority Critical patent/JP2641975B2/en
Priority to EP91402677A priority patent/EP0480814B1/en
Priority to DE69119022T priority patent/DE69119022T2/en
Priority to US07/771,986 priority patent/US5236896A/en
Priority to CA002052970A priority patent/CA2052970C/en
Publication of JPH04145672A publication Critical patent/JPH04145672A/en
Priority to US08/053,401 priority patent/US5322526A/en
Application granted granted Critical
Publication of JP2641975B2 publication Critical patent/JP2641975B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Superconductor Devices And Manufacturing Methods Thereof (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、超電導素子およびその作製方法に関する。よ
り詳細には、新規な構成の超電導素子およびその作製方
法に関する。
DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a superconducting element and a method for manufacturing the same. More specifically, the present invention relates to a superconducting element with a novel configuration and a method for manufacturing the same.

従来の技術 超電導を使用した代表的な素子に、ジョセフソン素子が
ある。ジョセフソン素子は、一対の超電導体をトンネル
障壁を介して結合した構成でありぐ高速スイッチング動
作が可能である。しかしながら、ジョセフソン素子は2
端子の素子であり、論理回路を実現するためには複雑な
回路構成になってしまう。
A Josephson device is a typical device using conventional technology superconductivity. A Josephson device has a structure in which a pair of superconductors are coupled through a tunnel barrier, and is capable of high-speed switching operation. However, the Josephson element is 2
It is a terminal element and requires a complicated circuit configuration to realize a logic circuit.

一方、超電導を利用した3端子素子としては、超電導ベ
ーストランジスタ、超電導FET等がある。第3図に、
超電導ベーストランジスタの概念図を示す。第3図の超
電導ベーストランジスタは、超電導体または常電導体で
構成されたエミッタ21、絶縁体で構成されたトンネル
障壁22、超電導体で構成されたベース23、半導体ア
イソレータ24および常電導体で構成されたコレクタ2
5を積層した構成になっている。この超電導ベーストラ
ンジスタは、トンネル障壁22を通過した高速電子を利
用した低電力消費、高速動作の素子である。
On the other hand, three-terminal elements using superconductivity include superconducting base transistors, superconducting FETs, and the like. In Figure 3,
A conceptual diagram of a superconducting base transistor is shown. The superconducting base transistor shown in FIG. 3 is composed of an emitter 21 made of a superconductor or a normal conductor, a tunnel barrier 22 made of an insulator, a base 23 made of a superconductor, a semiconductor isolator 24, and a normal conductor. collector 2
It has a structure in which 5 layers are stacked. This superconducting base transistor is a low-power consumption, high-speed operation element that utilizes high-speed electrons that have passed through the tunnel barrier 22.

第4図に、超電導FETの概念図を示す。第4図の超電
導FETは、超電導体で構成されている超電導ソース電
極41および超電導ドレイン電極42が、半導体層43
上に互いに近接して配置されている。超電導ソース電極
41および超電導ドレイン電極42の間の部分の半導体
層43は、下側が大きく削られ厚さが薄くなっている。
FIG. 4 shows a conceptual diagram of a superconducting FET. In the superconducting FET of FIG. 4, a superconducting source electrode 41 and a superconducting drain electrode 42 made of a superconductor are connected to a semiconductor layer 43
are placed close to each other on top. The semiconductor layer 43 in the portion between the superconducting source electrode 41 and the superconducting drain electrode 42 has its lower side largely shaved and has a reduced thickness.

また、半導体層43の下側表面にはゲート絶縁膜46が
形成され、ゲート絶縁膜46上にゲート電極44が設け
、られている。
Further, a gate insulating film 46 is formed on the lower surface of the semiconductor layer 43, and a gate electrode 44 is provided on the gate insulating film 46.

超電導FETは、超電導近接効果で超電導ソース電極4
1および超電導ドレイン電極42間の半導体層43を流
れる超電導電流を、ゲート電圧で制御する低電力消費、
高速動作の素子である。
A superconducting FET has a superconducting source electrode 4 due to the superconducting proximity effect.
1 and the superconducting current flowing through the semiconductor layer 43 between the superconducting drain electrode 42 by controlling the superconducting current with a gate voltage;
It is a high-speed operating element.

さらに、ソース電極、ドレイン電極間に超電導体でチャ
ネルを形成し、この超電導チャネルを流れる電流をゲー
ト電極に印加する電圧で制御する3端子の超電導素子も
発表されている。
Furthermore, a three-terminal superconducting element has been announced in which a channel is formed between a source electrode and a drain electrode using a superconductor, and the current flowing through this superconducting channel is controlled by a voltage applied to a gate electrode.

発明が解決しようとする課題 上記の超電導ベーストランジスタおよび超電導FETは
、いずれも半導体層と超電導体層とが積層された部分を
有する。ところが、近年研究が進んでいる酸化物超電導
体を使用して、半導体層と超電導体層との積層構造を作
製することは困難である。また、この構造が作製できて
も半導体層と超電導体層の間の界面の制御が難しく、素
子として満足な動作をしなかった。
Problems to be Solved by the Invention The above-described superconducting base transistor and superconducting FET both have a portion in which a semiconductor layer and a superconductor layer are laminated. However, it is difficult to fabricate a stacked structure of a semiconductor layer and a superconductor layer using oxide superconductors, which have been studied in recent years. Moreover, even if this structure could be fabricated, it was difficult to control the interface between the semiconductor layer and the superconductor layer, and the device did not operate satisfactorily.

また、超電導FETは、超電導近接効果を利用するため
、超電導ソース電極41および超電導ドレイン電極42
を、それぞれを構成する超電導体のコヒーレンス長の数
倍程度以内に近接させて作製しなければならない。特に
酸化物超電導体は、コヒーレンス長が短いので、酸化物
超電導体を使用した場合には、超電導ソース電極41お
よび超電導ドレイン電極42間の距離は、数IQnm以
下にしなければならない。このような微細加工は非常に
困難であり、従来は酸化物超電導体を使用した超電導F
ETを再現性よく作製できなかった。
Furthermore, in order to utilize the superconducting proximity effect, the superconducting FET has a superconducting source electrode 41 and a superconducting drain electrode 42.
must be made close to each other within several times the coherence length of the superconductor that constitutes each. In particular, an oxide superconductor has a short coherence length, so when an oxide superconductor is used, the distance between the superconducting source electrode 41 and the superconducting drain electrode 42 must be several IQ nm or less. Such microfabrication is extremely difficult, and conventionally superconducting F using oxide superconductors
ET could not be produced with good reproducibility.

さらに、従来の超電導チャネルを有する超電導素子は、
変調動作は確認されたが、キャリア密度が高いため、完
全なオン/オフ動作ができなかった。酸化物超電導体は
、キャリア密度が低いので、超電導チャネルに使用する
ことにより、完全なオン/オフ動作を行う上記の素子の
実現の可能性が期待されている。しかしながら、超電導
チャネルは5nm以下の厚さにしなければならず、その
ような構成の実現することは困難であった。
Furthermore, superconducting devices with conventional superconducting channels are
Although modulation operation was confirmed, complete on/off operation was not possible due to the high carrier density. Since oxide superconductors have a low carrier density, it is expected that by using them for superconducting channels, it will be possible to realize the above-mentioned devices that perform perfect on/off operation. However, the superconducting channel must have a thickness of 5 nm or less, making it difficult to realize such a configuration.

そこで本発明の目的は、上記従来技術の問題点を解決し
た、新規な構成の超電導素子およびその作製方法を提供
することにある。
SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a superconducting element having a novel configuration and a method for manufacturing the same, which solves the problems of the prior art described above.

課題を解決するための手段 本発明に従うと、基板上に成膜された酸化物超電導薄膜
に形成された超電導チャネルと、該超電導チャネルの両
端近傍に配置されて該超電導チャネルに電流を流すソー
ス電極およびドレイン電極と、前記超電導チャネル上に
配置されて該超電導チャネルに流れる電流を制御するゲ
ート電極を具備する超電導素子において、前記基板が突
出部を有し、前記酸化物超電導薄膜がC軸配向の酸化物
超電導体結晶で構成され、且つ前記突出部上の部分が薄
くされており、前記酸化物超電導薄膜の前記薄い部分が
、前記超電導チャネルであり、前記ソース電極および前
記ドレイン電極がa軸配向の酸化物超電導体結晶で構成
されていることを特徴とする超電導素子が提供される。
Means for Solving the Problems According to the present invention, there are provided a superconducting channel formed in an oxide superconducting thin film formed on a substrate, and source electrodes disposed near both ends of the superconducting channel to flow current through the superconducting channel. and a superconducting element comprising a drain electrode and a gate electrode disposed on the superconducting channel to control a current flowing through the superconducting channel, wherein the substrate has a protrusion, and the oxide superconducting thin film has a C-axis orientation. The oxide superconducting thin film is made of an oxide superconductor crystal, and a portion above the protrusion is made thin, the thin portion of the oxide superconducting thin film is the superconducting channel, and the source electrode and the drain electrode are oriented along the a-axis. Provided is a superconducting element comprising an oxide superconductor crystal of the present invention.

また、本発明では、上記の超電導素子を作製する方法と
して、突出部が形成された絶縁体基板上または突出部が
形成され、且つ絶縁膜を表面に有する半導体基板上に、
前記突出部上の厚さが5nm以下のC軸配向の酸化物超
電導薄膜を形成し、該C軸配向の酸化物超電導薄膜の前
記突出部上の両側の部分をlQnm以上エツチングし、
該エツチング部上にC軸配向の酸化物薄膜を形成する工
程を含むことを特徴とする超電導素子の作製方法が提供
される。
Further, in the present invention, as a method for manufacturing the above-mentioned superconducting element, on an insulating substrate on which a protrusion is formed or on a semiconductor substrate on which a protrusion is formed and has an insulating film on the surface,
forming a C-axis oriented oxide superconducting thin film with a thickness of 5 nm or less on the protrusion, etching portions of the C-axis oriented oxide superconducting thin film on both sides of the protrusion by 1Q nm or more;
A method for manufacturing a superconducting element is provided, which includes the step of forming a C-axis oriented oxide thin film on the etched portion.

作用 本発明の超電導素子は、C軸配向の酸化物超電導薄膜に
よる超電導チャネルと、超電導チャネルの両側に配置さ
れたC軸配向の酸化物超電導薄膜による超電導ソース電
極および超電導ドレイン電極と、超電導チャネルを流れ
る電流を制御するゲート電極とを具備する。
Function The superconducting element of the present invention has a superconducting channel made of a C-axis oriented oxide superconducting thin film, a superconducting source electrode and a superconducting drain electrode made of C-axis oriented oxide superconducting thin films disposed on both sides of the superconducting channel, and a superconducting channel. and a gate electrode that controls the flowing current.

従来の超電導FETが、超電導近接効果を利用して半導
体中に超電導電流を流すのに対し、本発明の超電導素子
では、主電流は超電導体中を流れる。従って、従来の超
電導FETを作製するときに必要な微細加工技術の制限
が緩和される。
While a conventional superconducting FET uses the superconducting proximity effect to cause a superconducting current to flow through the semiconductor, in the superconducting element of the present invention, the main current flows through the superconductor. Therefore, restrictions on microfabrication techniques required when manufacturing conventional superconducting FETs are relaxed.

超電導チャネルは、ゲート電極に印加された電圧で開閉
させるために、ゲート電極により発生される電界の方向
で、厚さが5nm以下でなければならない。本発明の超
電導素子では、突出部を設けた基板上に形成されたC軸
配向の酸化物超電導薄膜の、基板の突出部により薄くな
った部分を超電導チャネルとする。
The superconducting channel must have a thickness of 5 nm or less in the direction of the electric field generated by the gate electrode in order to be opened and closed by the voltage applied to the gate electrode. In the superconducting element of the present invention, a portion of a C-axis oriented oxide superconducting thin film formed on a substrate provided with a protrusion, which is thinned by the protrusion of the substrate, serves as a superconducting channel.

突出部を設けた基板上に単に酸化物超電導薄膜を成長さ
せただけでは、突出部上にも同じ厚さの薄膜が形成され
るので、本発明の方法では薄膜を形成後薄膜表面を平坦
にし、薄膜の基板突出部上の部分を薄くする。
If an oxide superconducting thin film is simply grown on a substrate with protrusions, a thin film of the same thickness will be formed on the protrusions, so the method of the present invention flattens the thin film surface after forming the thin film. , the portion of the thin film above the substrate protrusion is thinned;

酸化物超電導体は、一般に結晶方向により超電導特性が
異なり、特に臨界電流密度は結晶のC軸に垂直な方向が
大きい。この結果、従来のソース電極、ドレイン電極の
構造では、極薄の超電導チャネルに均一に電流を流すこ
とは難しい。本発明の超電導素子では、超電導ソース電
極および超電導ドレイン電極はC軸配向の酸化物超電導
薄膜を使用しているので、主電流が基板に垂直な方向に
流れ、超電導チャネルはC軸配向の酸化物超電導薄膜を
使用しているので、基板に平行な方向に流れる。即ち、
本発明の超電導素子は、超電導ソース電極、超電導ドレ
イン電極および超電導チャネルのいずれもが酸化物超電
導体の臨界電流密度の大きい方向に主電流が流れるよう
に構成されている。
Oxide superconductors generally have different superconducting properties depending on the crystal direction, and the critical current density is particularly large in the direction perpendicular to the C axis of the crystal. As a result, with conventional source and drain electrode structures, it is difficult to uniformly flow current through the ultrathin superconducting channel. In the superconducting device of the present invention, the superconducting source electrode and the superconducting drain electrode use a C-axis oriented oxide superconducting thin film, so the main current flows in a direction perpendicular to the substrate, and the superconducting channel is made of a C-axis oriented oxide superconducting thin film. Since a superconducting thin film is used, the flow is parallel to the substrate. That is,
In the superconducting element of the present invention, each of the superconducting source electrode, the superconducting drain electrode, and the superconducting channel is configured such that a main current flows in a direction where the critical current density of the oxide superconductor is high.

本発明の方法では、超電導チャネルのC軸配向の酸化物
超電導薄膜を成膜するのに、基板温度を約700℃とす
る。また、ソース電極およびドレイン電極のC軸配向の
酸化物超電導薄膜は、成膜時の基板温度を約650℃以
下として成膜する。どちらの場合も成膜法としては、ス
パッタリング法、MBE (分子ビームエピタキシ)法
、真空蒸着法等が使用できる。
In the method of the present invention, the substrate temperature is set at about 700° C. to deposit the oxide superconducting thin film with the C-axis orientation of the superconducting channel. Further, the C-axis oriented oxide superconducting thin films of the source electrode and the drain electrode are formed at a substrate temperature of approximately 650° C. or lower during film formation. In either case, a sputtering method, an MBE (molecular beam epitaxy) method, a vacuum evaporation method, or the like can be used as a film forming method.

本発明の超電導素子において、絶縁体基板には、MgO
1SrTi03等の酸化物単結晶基板が使用可能である
。これらの基板上には、配向性の高い酸化物超電導体結
晶からなる酸化物超電導薄膜を成長させることが可能で
あるので好ましい。また、表面に絶縁層を有する半導体
基板を使用することもできる。
In the superconducting element of the present invention, the insulator substrate includes MgO
An oxide single crystal substrate such as 1SrTi03 can be used. These substrates are preferable because it is possible to grow an oxide superconducting thin film made of highly oriented oxide superconductor crystals. Furthermore, a semiconductor substrate having an insulating layer on its surface can also be used.

本発明の超電導素子には、Y−Ba−Cu−0系酸化物
超電導体、Bi −3r −Ca−Cu−○系酸化物超
電導体、TI −Ba −Ca−Cu −0系酸化物超
電導体等任意の酸化物超電導体を使用することができる
The superconducting element of the present invention includes a Y-Ba-Cu-0 based oxide superconductor, a Bi-3r-Ca-Cu-○ based oxide superconductor, and a TI-Ba-Ca-Cu-0 based oxide superconductor. Any oxide superconductor can be used.

以下、本発明を実施例により、さらに詳しく説明するが
、以下の開示は本発明の単なる実施例に過ぎず、本発明
の技術的範囲をなんら制限するものではない。
EXAMPLES Hereinafter, the present invention will be explained in more detail with reference to Examples, but the following disclosure is merely an example of the present invention and does not limit the technical scope of the present invention in any way.

実施例 第1図に、本発明の超電導素子の断面図を示す。Example FIG. 1 shows a cross-sectional view of the superconducting element of the present invention.

第1図の超電導素子は、突出部50を有する基板5上に
形成された超電導層1を有する。超電導層1は、C軸配
向の酸化物超電導薄膜で構成され、超電導層1の基板5
の突出部50の上の部分は、厚さ5n+y+以下になっ
ており超電導チャネル10になっている。また、超電導
層1の超電導チャネル10の両側は、lQnm程度低く
なっており、C軸配向の酸化物超電導薄膜で構成された
ソース電極2およびドレイン電極3が配置されている。
The superconducting element shown in FIG. 1 has a superconducting layer 1 formed on a substrate 5 having a protrusion 50. The superconducting element shown in FIG. The superconducting layer 1 is composed of a C-axis oriented oxide superconducting thin film, and the substrate 5 of the superconducting layer 1
The upper part of the protrusion 50 has a thickness of 5n+y+ or less and forms the superconducting channel 10. Further, on both sides of the superconducting channel 10 of the superconducting layer 1, the height is lowered by about 1Q nm, and a source electrode 2 and a drain electrode 3 made of a C-axis oriented oxide superconducting thin film are arranged.

さらに、超電導チャネル10の上には絶縁膜6を介して
ゲート電極4が配置されている。
Further, a gate electrode 4 is arranged on the superconducting channel 10 with an insulating film 6 interposed therebetween.

第2図を参照して、本発明の超電導素子を本発明の方法
で作製する手順を説明する。まず、第2図(a)に示す
ような基板5に突出部を形成する。基板5としては、M
g0(100)基板、5rTi03(100)基板等の
絶縁体基板、または表面に絶縁膜を有する5i(100
)等の半導体基板が好ましい。ただし、半導体基板を使
用する場合には、後述するよう突出部を形成後、表面に
絶縁膜を形成する。
Referring to FIG. 2, the procedure for manufacturing the superconducting element of the present invention using the method of the present invention will be described. First, a protrusion is formed on the substrate 5 as shown in FIG. 2(a). As the substrate 5, M
Insulator substrates such as g0 (100) substrates, 5rTi03 (100) substrates, or 5i (100
) and the like are preferred. However, when a semiconductor substrate is used, an insulating film is formed on the surface after forming protrusions as described later.

次に、第2図ら)に示すよう、基板5の一部をフォトレ
ジスト8で被覆し、Arイオンエツチング等のドライエ
ツチング法で表面を削り、突出部50を形成する。
Next, as shown in FIG. 2 et al., a part of the substrate 5 is covered with a photoresist 8, and the surface is etched by a dry etching method such as Ar ion etching to form a protrusion 50.

半導体基板を使用する場合は、結晶方向も重要であり、
上述のように手順も多少異なる。例えば、5i(100
)基板を使用する場合、5i(100)面に対し、ゲー
ト長手方向、即ち、チャネルの電流の流れる方向に向か
って垂直方向が(110)面になるようフォトレジスト
8を形成する。このSi基板をKOHまたはAPW等の
エツチング液を使用してエツチングし、突出部50を形
成する。この基板の表面に、例えばCVD法でMgAl
2O4層およびスパッタリング法でBaT i 03層
を連続して積層する。
When using a semiconductor substrate, the crystal orientation is also important.
As mentioned above, the steps are slightly different. For example, 5i (100
) If a substrate is used, the photoresist 8 is formed so that the (110) plane is perpendicular to the 5i (100) plane in the gate longitudinal direction, that is, in the channel current flow direction. This Si substrate is etched using an etching solution such as KOH or APW to form protrusions 50. For example, MgAl is applied to the surface of this substrate by CVD method.
A 2O4 layer and a BaT i 03 layer are successively deposited by sputtering.

次に、第2図(C)に示すよう加工した基板5上にC軸
配向の酸化物超電導薄膜をオファクシススバッタリング
法、反応性蒸着法、MBE法、CVD法等の方法で成膜
し、超電導層1を形成する。酸化物超電導体としては、
Y−Ba−Cu−0系酸化物超電導体、Bi −3r 
−Ca −Cu −0系酸化物超電導体、Tl −Ba
 −Ca −Cu −0系酸化物超電導体が好ましい。
Next, a C-axis oriented oxide superconducting thin film is formed on the processed substrate 5 as shown in FIG. Then, a superconducting layer 1 is formed. As an oxide superconductor,
Y-Ba-Cu-0 based oxide superconductor, Bi-3r
-Ca -Cu -0 based oxide superconductor, Tl -Ba
-Ca-Cu-0 based oxide superconductor is preferred.

オファクシススバッタリング法でY1Ba2Cu30i
−xC軸配向の酸化物超電導薄膜を成膜する場合のスパ
ッタリング条件を以下に示す。
Y1Ba2Cu30i by offaxis battering method
The sputtering conditions for forming an oxide superconducting thin film with -xC axis orientation are shown below.

スパッタリングガス   Ar  :90%02 :1
0% 圧    力         10  Pa基板温度
  700℃ 超電導層1の突出部50上の部分の厚さが5層m以下に
なるよう、超電導層1を形成する。次いで第2図(6)
に示すよう、超電導層1上に絶縁膜16を形成する。絶
縁膜16はMgOが好ましいが、他にも酸化物超電導薄
膜との界面で大きな準位を作らない絶縁体を用いること
が好ましい。次いで第2図(e)に示すよう、絶縁膜1
6上に常電導体膜17を成膜する。常電導体膜17には
、AuまたはTi5W等の高融点金属、これらのシリサ
イドを用いることが好ましい。界面準位の抑制、汚染の
防止および機械的応力の減少等の観点から、上舵の絶縁
膜16および常電導体膜17は超電導層1に連続して形
成することが望ましい。
Sputtering gas Ar:90%02:1
0% Pressure 10 Pa Substrate temperature 700° C. The superconducting layer 1 is formed so that the thickness of the portion of the superconducting layer 1 above the protrusion 50 is 5 m or less. Next, Figure 2 (6)
As shown in FIG. 2, an insulating film 16 is formed on the superconducting layer 1. The insulating film 16 is preferably made of MgO, but it is also preferable to use other insulators that do not create a large level at the interface with the oxide superconducting thin film. Next, as shown in FIG. 2(e), the insulating film 1
A normal conductor film 17 is formed on 6. For the normal conductor film 17, it is preferable to use a high melting point metal such as Au or Ti5W, or a silicide thereof. From the viewpoint of suppressing interface states, preventing contamination, and reducing mechanical stress, it is desirable that the upper rudder insulating film 16 and normal conductor film 17 be formed continuously on the superconducting layer 1.

次いで、耐熱マスク膜9でゲート電極パターンを形成し
、反応性イオンエツチングまたはArイオンミリング等
で第2図(f)に示すようゲート電極4および絶縁層6
を形成する。耐熱マスク膜9には、例えばMo等の高融
点金属が使用でき、真空蒸着法等で形成することが可能
である。必要に応じ、サイドエッチを促進し、ゲート電
極4および絶縁層6の長さを短くする。ゲート電極4お
よび絶縁層6を形成したら、第2図(区に示すよう、超
電導層1の超電導チャネル10両側の部分12.13を
エツチングしてlQnm以上低くする。
Next, a gate electrode pattern is formed using the heat-resistant mask film 9, and the gate electrode 4 and the insulating layer 6 are etched by reactive ion etching or Ar ion milling as shown in FIG. 2(f).
form. The heat-resistant mask film 9 can be made of a high-melting point metal such as Mo, and can be formed by vacuum evaporation or the like. If necessary, side etching is promoted to shorten the lengths of the gate electrode 4 and the insulating layer 6. After forming the gate electrode 4 and the insulating layer 6, as shown in FIG.

第2図(社)に示すよう、超電導層1と同じ酸化物超電
導体のC軸配向の薄膜でソース電極2およびドレイン電
極3を形成する。ソース電極2およびドレイン電極3は
、約200 nmの厚さに形成する。
As shown in FIG. 2, a source electrode 2 and a drain electrode 3 are formed of a C-axis oriented thin film of the same oxide superconductor as the superconducting layer 1. The source electrode 2 and drain electrode 3 are formed to have a thickness of about 200 nm.

成膜方法は、オファクシススバッタリング法、反応性蒸
着法、MBE法、CVD法等任意の方法が選択できる。
Any method can be selected as the film forming method, such as an oxidative sputtering method, a reactive vapor deposition method, an MBE method, or a CVD method.

オファクシススバッタリング法でY 1Ba2Cu30
7−X C軸配向の酸化物超電導薄膜を成膜する場合の
スパッタリング条件を以下に示す。
Y 1Ba2Cu30 by ophaxis battering method
The sputtering conditions for forming a 7-X C-axis oriented oxide superconducting thin film are shown below.

スパッタリンクカス   Ar  :90%02:10
% 圧    力          10  Pa基板温
度  640℃ 同時に耐熱マスク膜9上にもa軸配向の酸化物超電導薄
膜19が堆積するが、耐熱マスク膜9としてMoを使用
すれば成膜中に昇華して、第2図(i)に示すように本
発明の超電導素子が完成する。また、耐熱マスク膜9に
耐熱レジストでなく絶縁膜を使用してゲート電極4上に
残したままでもよい。
Sputter link residue Ar:90%02:10
% Pressure 10 Pa Substrate temperature 640°C At the same time, the a-axis oriented oxide superconducting thin film 19 is deposited on the heat-resistant mask film 9, but if Mo is used as the heat-resistant mask film 9, it will sublimate during film formation and the The superconducting device of the present invention is completed as shown in FIG. 2(i). Alternatively, an insulating film may be used for the heat-resistant mask film 9 instead of a heat-resistant resist, and may be left on the gate electrode 4.

本発明の超電導素子を本発明の方法で作製すると、超電
導チャネルに一様に電流を流すことができ、超電導FE
Tの特性を向上させることが可能である。また、超電導
FETを作製する場合に要求される微細加工技術の制限
が緩和される。さらに、表面が平坦にできるので、後に
必要に応じ配線を形成することが容易になる。従って、
作製が容易であり、素子の性能も安定しており、再現性
もよい。
When the superconducting element of the present invention is manufactured by the method of the present invention, a current can be uniformly passed through the superconducting channel, and the superconducting FE
It is possible to improve the characteristics of T. Further, restrictions on microfabrication techniques required when manufacturing a superconducting FET are relaxed. Furthermore, since the surface can be made flat, it becomes easier to form wiring later as required. Therefore,
It is easy to manufacture, has stable device performance, and has good reproducibility.

発明の詳細 な説明したように、本発明の超電導素子は、超電導チャ
ネル中を流れる超電導電流をゲート電圧で制御する構成
となっている。従って、従来の超電導FETのように、
超電導近接効果を利用していないので微細加工技術の制
限が緩和される。
As described in detail, the superconducting element of the present invention has a configuration in which the superconducting current flowing in the superconducting channel is controlled by the gate voltage. Therefore, like the conventional superconducting FET,
Since the superconducting proximity effect is not used, restrictions on microfabrication technology are relaxed.

また、超電導体と半導体を積層する必要もないので、酸
化物超電導体を使用して高性能な素子が作製できる。
Furthermore, since there is no need to stack a superconductor and a semiconductor, high-performance devices can be manufactured using oxide superconductors.

本発明により、超電導技術の電子デバイスへの応用がさ
らに促進される。
The present invention further promotes the application of superconducting technology to electronic devices.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は、本発明の超電導素子の概略図であり、第2図
は、本発明の方法により本発明の超電導素子を作製する
場合の工程を示す概略図であり、第3図は、超電導ベー
ストランジスタの概略図であり、 第4図は、超電導FETの概略図である。 〔主な参照番号〕 1・・・超電導層、  2・・・ 3・・・超電導ドレイン電極、 4・・・超電導ゲート電極、 ソース電極、 ・基板
FIG. 1 is a schematic diagram of the superconducting device of the present invention, FIG. 2 is a schematic diagram showing the steps for producing the superconducting device of the present invention by the method of the present invention, and FIG. 3 is a schematic diagram of the superconducting device of the present invention. FIG. 4 is a schematic diagram of a base transistor; FIG. 4 is a schematic diagram of a superconducting FET. [Main reference numbers] 1...Superconducting layer, 2...3...Superconducting drain electrode, 4...Superconducting gate electrode, source electrode, ・Substrate

Claims (2)

【特許請求の範囲】[Claims] (1)基板上に成膜された酸化物超電導薄膜に形成され
た超電導チャネルと、該超電導チャネルの両端近傍に配
置されて該超電導チャネルに電流を流すソース電極およ
びドレイン電極と、前記超電導チャネル上に配置されて
該超電導チャネルに流れる電流を制御するゲート電極を
具備する超電導素子において、前記基板が突出部を有し
、前記酸化物超電導薄膜がc軸配向の酸化物超電導体結
晶で構成され、且つ前記突出部上の部分が薄くされてお
り、前記酸化物超電導薄膜の前記薄い部分が、前記超電
導チャネルであり、前記ソース電極および前記ドレイン
電極がa軸配向の酸化物超電導体結晶で構成されている
ことを特徴とする超電導素子。
(1) A superconducting channel formed in an oxide superconducting thin film formed on a substrate, a source electrode and a drain electrode arranged near both ends of the superconducting channel to flow a current through the superconducting channel, and a source electrode and a drain electrode arranged on the superconducting channel. A superconducting element comprising a gate electrode disposed in a gate electrode for controlling a current flowing through the superconducting channel, wherein the substrate has a protrusion, the oxide superconducting thin film is composed of a c-axis oriented oxide superconductor crystal, Further, a portion above the protrusion is made thin, the thin portion of the oxide superconducting thin film is the superconducting channel, and the source electrode and the drain electrode are made of an a-axis oriented oxide superconductor crystal. A superconducting element characterized by:
(2)請求項1に記載の超電導素子を作製する方法にお
いて、突出部が形成された絶縁体基板上または突出部が
形成され、且つ絶縁膜を表面に有する半導体基板上に、
前記突出部上の厚さが5nm以下のc軸配向の酸化物超
電導薄膜を形成し、該c軸配向の酸化物超電導薄膜の前
記突出部上の両側の部分を10nm以上エッチングし、
該エッチング部上にa軸配向の酸化物薄膜を形成する工
程を含むことを特徴とする超電導素子の作製方法。
(2) In the method for manufacturing a superconducting element according to claim 1, on an insulating substrate on which a protrusion is formed or on a semiconductor substrate on which a protrusion is formed and has an insulating film on the surface,
forming a c-axis oriented oxide superconducting thin film with a thickness of 5 nm or less on the protrusion, etching portions of the c-axis oriented oxide superconducting thin film on both sides of the protrusion by 10 nm or more;
A method for manufacturing a superconducting element, comprising the step of forming an a-axis oriented oxide thin film on the etched portion.
JP2270070A 1990-10-08 1990-10-08 Superconducting element and fabrication method Expired - Lifetime JP2641975B2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP2270070A JP2641975B2 (en) 1990-10-08 1990-10-08 Superconducting element and fabrication method
EP91402677A EP0480814B1 (en) 1990-10-08 1991-10-08 Superconducting device having an extremely thin superconducting channel formed of oxide superconductor material and method for manufacturing the same
DE69119022T DE69119022T2 (en) 1990-10-08 1991-10-08 Superconducting device with ultrathin channel made of oxidic superconducting material and method for its production
US07/771,986 US5236896A (en) 1990-10-08 1991-10-08 Superconducting device having an extremely thin superconducting channel formed of oxide superconductor material
CA002052970A CA2052970C (en) 1990-10-08 1991-10-08 Superconducting device having an extremely thin superconducting channel formed of oxide superconductor material and method for manufacturing the same
US08/053,401 US5322526A (en) 1990-10-08 1993-04-28 Method for manufacturing a superconducting device having an extremely thin superconducting channel formed of oxide superconductor material

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2270070A JP2641975B2 (en) 1990-10-08 1990-10-08 Superconducting element and fabrication method

Publications (2)

Publication Number Publication Date
JPH04145672A true JPH04145672A (en) 1992-05-19
JP2641975B2 JP2641975B2 (en) 1997-08-20

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