JPH04147645A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To perform wiring between cells on the cells and improve integration by forming first wiring layers which vertically cross each cell in first hierarchy, second wiring layers which horizontally cross each cell and a power supply wiring layer in second hierarchy and performing wiring in each cell and between the cells on the first and the second wiring layers. CONSTITUTION:Wiring layers 31, 32 and 33 are formed in first hierarchy, power supply wiring layers 10 and 20 are formed in second hierarchy so as to vertically cross a cell area 100, and wiring layers 41, 42 and 43 are formed in the second hierarchy in the direction which orthogonally intersects with such layers. The wiring layers 41 and 42 are crossing the wiring layers 31, 32 and 33 and the contact hole of connecting points (g) and (h) permits the connection of the wiring layer 41 with the wiring layer 31 and the connection of the wiring layer 42 with the wiring layer 33. The wiring layer of the first hierarchy is extended downward from a terminal point (d) and is electrically connected with the wiring layer 43 by the contact hole of a connecting point (i). Such connection allows the wiring layer 43 to be connected with the wiring layer 32. The wiring layers 41, 42 and 43 are used for the wiring with other cells.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a standard cell type semiconductor integrated circuit device.

[Conventional technology]

A standard cell method is used to efficiently manufacture a wide variety of semiconductor integrated circuit devices. In such a standard cell type semiconductor integrated circuit device, a plurality of cells constituting a unit logic unit are arranged, and necessary wiring is performed between these cells to construct a device having a desired logic function. Usually, two levels of wiring layers, a first level and a second level, are formed of aluminum or the like for wiring, and wiring within cells and wiring between cells are performed.

[Problem to be solved by the invention]

In the conventional standard cell type semiconductor integrated circuit device described above, wiring between cells is performed in a wiring area outside the cells. However, if a wiring region is provided outside the cell, an extra region area must be secured for that amount, which becomes an obstacle to improving the degree of integration.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device in which wiring between cells can be performed on the cells.

[Means to solve the problem]

In the present invention, a plurality of cells are arranged in a horizontal row, power wiring layers extending in the column direction of this cell row are arranged above and below this cell row, and a first layer and a second layer are connected for wiring. In a standard cell type semiconductor integrated circuit device having a configuration in which two levels of wiring layers are formed, a first wiring layer extends vertically across each cell, and a second wiring layer extends horizontally across each cell. layer, and the first wiring layer is formed by the wiring layer of the first layer,
The second wiring layer and the power supply wiring layer are formed by a second level wiring layer, the first wiring layer performs wiring within a cell, and the second wiring layer performs wiring between cells. This is what I did.

[For production]

Wiring within the cell is performed using a first wiring layer formed at the first level, as in the conventional device. Since this first wiring layer extends vertically across each cell, it can be electrically connected to a predetermined portion of an active element within the cell through a contact hole.

Further, since the power supply wiring layer is formed of the second level wiring layer, the first wiring layer and the power supply wiring layer can be electrically connected through the contact hole. Therefore, it is possible to supply power to active elements within the cell from the power wiring layer. On the other hand, the second wiring layer formed at the second level is formed in a direction perpendicular to the first wiring layer formed at the first level. That is, the second wiring layer extends over the cell so as to straddle the first wiring layer. For this reason,
If a contact hole is formed in a portion where the second wiring layer three-dimensionally intersects with the first wiring layer, the two can be electrically connected. Therefore, the wiring between cells, which was conventionally done in the wiring area outside the cells, can now be done on the cell area using the second wiring layer.

〔Example〕

The present invention will be described below based on illustrated embodiments. FIG. 1(a) is a diagram showing one cell constituting a basic logic unit for realizing a NAND circuit in a standard cell type semiconductor integrated circuit device. Active elements such as MOS transistors are formed in the cell region 100 indicated by broken lines. In this figure, for convenience of explanation,
The NAND circuit 105 is represented by a symbol. Furthermore, although a large number of cells are actually arranged in the horizontal direction of the figure, only one cell area 100 is shown here. Power supply wiring layers 10 and 20 are formed above and below the cell rows arranged in the horizontal direction, respectively. In this way, the power wiring layer 10.
20 extends in the horizontal direction of the figure and supplies power to each cell.

Wiring layers 31, 32 and 33 are formed vertically across the cell region 100. That is, the wiring layer 31 is located at a position connecting terminal points a and b, and the wiring layer 31 is located at a position connecting terminal points a and b.
A wiring layer 32 is formed at a position connecting terminal points d, and a wiring layer 33 is formed at a position connecting terminal points e and f. In this embodiment, the power supply wiring layers 10, 20 and the wiring layers 31, 32, 33 are all made of aluminum wiring layers.

Moreover, since the - wiring layers 31, 32, and 33 are formed on the first level, and the power supply wiring layers 10, 20 are formed on the second level, they can overlap each other in a plan view. In the actual layout pattern, the terminal points a to f are hidden under the power supply wiring layer 10.20.

In the figure, the second layer wiring layer is indicated by a thick line.

FIG. 1(b) is a diagram showing a state in which wiring layers 41, 42, and 43 are formed for the cell shown in FIG. 1(a).

The wiring layers 41, 42.43 are the wiring layers 31.32.3.
It extends in a direction perpendicular to 3, that is, across each cell from side to side, and is parallel to the power supply wiring layers 10 and 20. The wiring layers 41, 42, and 43 are formed at the second level. Therefore, the wiring layers 41 and 42 cross over the wiring layers 31, 32, and 33 formed in the first layer, and the contact holes formed at the connection points g and h connect the wiring layers 41 and 31, the wiring layer 42 and 33 are electrically connected. Also, from terminal point d,
The first layer wiring layer extends downward in the figure and is electrically connected to the wiring layer 43 through a contact hole formed at the connection point i. With this connection, the wiring layer 43 is connected to the wiring layer 3.
It will be connected to 2. The wiring layers 41, 42, and 43 extend to the left and right in the figure, and can be electrically connected to other cells arranged in the left and right directions in the figure. In other words, the wiring layers 31, 32, 33 are
The wiring layers 41, 42, and 43 are used for wiring between cells with other cells.

What should be noted in the above configuration is that the wiring layer 43 is formed outside the cell area (wiring area), but the wiring layers 41 and 42 are formed on the cell area. As described above, according to the present invention, wiring between cells can be performed in a wiring region outside the cell region (wiring layer 43) or can be wired on the cell region (wiring layers 41, 42). In conventional devices, all wiring between cells was performed in a wiring area outside the cell area, which caused the problem of difficulty in integration as described above. However, according to the present invention, the required wiring between cells It is also possible to perform all of the wiring on the cell region, and the degree of integration can be further improved.

The basic idea of the present invention has been described above with respect to one embodiment.Next, this embodiment will be explained in more detail based on a specific layout pattern.

FIG. 2 is a diagram showing a specific layout pattern corresponding to the circuit configuration shown in FIG. 1(a). Note that the same components as in FIG. 1(a) are designated by the same reference numerals. As described above, this device uses two wiring layers, the first layer and the second layer, both of which are made of aluminum. In Figure 2, the first
The wiring layers of the hierarchy are shown by hatching with dots,
The wiring layer of the second level is shown hatched with diagonal lines downward to the right. Furthermore, the polysilicon gate layer is hatched with diagonal lines slanting downward to the left. The power supply wiring layers 10 and 20 are both second-level wiring layers, and are formed to extend horizontally upward and downward in the figure. Wiring layers 31, 32, and 33 for wiring within the cell are formed to extend vertically between the upper power supply wiring layer 1° and the lower power supply wiring layer 20. This wiring layer 31, 32.3
Reference numeral 3 denotes a first-level wiring layer, which is configured such that upper and lower terminal points a to f go under the power supply wiring layer 10.20. Impurity diffusion regions 50 and 60 are provided within the cell, and a MOS transistor is formed here. Further, first layer wiring layers 81, 82 and 83 are provided for wiring within the cell. The upper ends of wiring layers 81 and 82 are connected to power supply wiring layer 10 through contact holes 11 and 12, and the lower ends are connected to impurity diffusion region 50 through contact holes 51 and 52. Further, the lower end of the wiring layer 83 is connected to the power supply wiring layer 20 through the contact hole 21.
The upper end is formed into an impurity diffusion region 6 by a contact hole 61.
Connected to 0. In this way, a predetermined power is supplied to impurity diffusion regions 50 and 60. Polysilicon gate electrodes 70 and 75 both extend in the vertical direction of the figure so as to span impurity diffusion regions 50 and 6o. The gate electrode 7o is connected to the contact hole 71.
is connected to the wiring layer 32 via the gate electrode 75.
is connected to the wiring layer 31 via a contact hole 76. Furthermore, the wiring layer 33 is connected to the impurity diffusion region 50 through a contact hole 53 and to the impurity diffusion region 60 through a contact hole 62, respectively.

In this way, a NAND circuit is constructed in which the wiring layers 31 and 32 serve as two input terminals, and the wiring layer 33 serves as one output terminal.

As mentioned above, FIG. 2 is a specific layout pattern corresponding to the configuration shown in FIG. 1(a).

In reality, a semiconductor integrated circuit device that performs complex logical operations is assembled by connecting a plurality of cells constituting a single logic unit. Therefore, as shown in FIG. 1(b), a wiring layer 41 for wiring between cells,
42.43 will be further formed. This figure 1 (
A specific layout pattern corresponding to the configuration shown in b) is shown in FIG. Here, in order to avoid complicating the diagram, only the second level wiring layer is hatched. In FIG. 3, second layer wiring layers 41, 42, and 43 are further added to the configuration shown in FIG. 2. Also, terminal point d
A first layer wiring layer 90 is also added so as to extend downward from the figure. The wiring layer 41 is connected to the wiring layer 31 through a contact hole 46, and the wiring layer 42 is connected to the wiring layer 33 through a contact hole 47. Further, the wiring layer 43 is connected to the wiring layer 9 through the contact hole 48.
0, and this wiring layer 90 is connected to the wiring layer 32 via the terminal point d. After all, this NAND circuit can operate with the wiring layers 41 and 43 serving as two input terminals and the wiring layer 42 serving as one output terminal. The wiring layers 41, 42 and 43 extend from left to right in the figure and are connected to predetermined in-cell wiring layers of other predetermined cells.

Finally, the merits of the present invention will be concretely illustrated by comparing a specific logic circuit realized by the device according to the present invention with a case realized by a conventional device. Now, consider the case of realizing a logic circuit as shown in FIG. This logic circuit consists of four AND circuits 115, 125, 145, 17
5, two inverter circuits 155 and 165, and one NOR circuit 135.

It has a function of outputting a predetermined logic output of 0 based on B, C, Sl, and S2. FIG. 5 shows a configuration in which this logic circuit is implemented using a device according to the present invention, and FIG. 6 shows a configuration in which this logic circuit is implemented using a conventional device.

In both cases, each logic circuit 115, 125, 135°145
．． 155, 165, 175, cell area 110.120
, 130, 140, 150, 160, and 170. The broken lines in the figure indicate the boundaries of each cell area, and the solid lines indicate the 1111th! The wiring layer within the cell consisting of the 'layer' and the thick line indicate the wiring layer between the cells consisting of the second layer. In the conventional device shown in FIG. 6, it is necessary to perform all wiring between cells in a wiring area provided outside the cell area, which requires a considerable area of the wiring area. In contrast, in the device of the present invention shown in FIG. 5, most of the wiring between cells is performed on the cell region, and the area of the wiring region to be formed outside the cell region can be reduced. That is, according to the present invention, it is possible to achieve higher integration than the conventional device.

The present invention has been described above based on the illustrated embodiments, but
The present invention is not limited to the configuration of the embodiment shown here, but can be widely applied to standard cell type semiconductor integrated circuit devices.

〔Effect of the invention〕

As described above, according to the semiconductor integrated circuit device according to the present invention, since the inter-cell wiring layer is formed in the second layer so as to intersect with the intra-cell wiring layer formed in the first layer,
Wiring between cells can now be done on the cell area, making it possible to achieve greater integration.

[Brief explanation of the drawing]

FIG. 1(a) is a diagram showing one cell constituting a basic logic unit for realizing a NAND circuit in a semiconductor integrated circuit device according to the present invention, and FIG.
), FIG. 2 is a diagram showing a specific layout pattern corresponding to the structure shown in FIG. 1(a), and FIG. Figure 1 (
It is a diagram showing the configuration shown in b). 10... Power wiring layer, 11.12... Contact hole, 20... Power wiring layer, 21... Contact hole, 31, 32. 33... First wiring layer (intra-cell wiring layer) ), 41, 42.43... second wiring layer (intercell wiring layer), 46, 47.48... contact hole, 50... impurity diffusion region, 51.52.53...
・Contact hole, 60... Impurity diffusion region, 61
゜62... Contact hole, 70... Gate electrode layer, 71... Contact hole, 75... Gate electrode layer, 76... Contact hole, 81, 82, 83
゜90...first wiring layer (intracell wiring layer), 100゜110.120, 130, 140, 150, 160.1
70... Cell area, 115, 125, 135° 145
．． 155, 165, 175...logic circuit, a - f
...terminal point, g-i...connection point. Patent applicant Dai Nippon Printing Co., Ltd. Applicant agent Patent attorney Hiroshi Shimura Figure 1 Figure 2 Figure 4

Claims (1)

[Claims] A plurality of cells are arranged in a horizontal row, and above and below this cell row,
In a standard cell type semiconductor integrated circuit device having a configuration in which a power wiring layer extending in the column direction of the cell row is arranged and two wiring layers, a first layer and a second layer, are formed for wiring, A first wiring layer extending vertically across each cell and a second wiring layer extending horizontally across each cell are provided, and the first wiring layer is connected to the first wiring layer by the wiring layer of the first layer. The second wiring layer and the power supply wiring layer are formed by the wiring layer of the second hierarchy, the wiring within the cell is performed by the first wiring layer, and the wiring between cells is formed by the second wiring layer. A semiconductor integrated circuit device characterized in that wiring is performed.