JPH04148351A - Disk cache controller - Google Patents

Abstract

PURPOSE:To write the data of a cache memory which is written at a high speed in a partial writing form, in a disk device by writing the data from the disk device transferred by a logical sector unit, in a logical sector part which is not updated in a physical sector to which the partial writing is operated. CONSTITUTION:The data of the logical sector unit from a disk device 3, which are transferred from a cache logical sector data transferring circuit 16, are written in the logical sector part which is not updated in the physical sector to which the partial writing is operated, by the control of a subprocessor 15, towards the data which is written in a cash memory 18 at a high speed in the partial writing form. Therefore, the data which are written in the cache memory 18 at high speed in the partial writing form can be handled by the physical sector unit even when the data of the cache memory 18 can be recorded in the disk device 3 only by the physical sector unit. Thus, the data which are written in the cache memory 18 in the partial writing form can be recorded in the disk device 3.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to a disk cache control device, and more particularly to a disk cache control device V that stores data to be written in a cache memory.

BACKGROUND ART Conventionally, in a disk cache control device, as shown in FIG. The read data is transferred to the host processor 2 via the host interface 50 by the read data transfer circuit 52.

When data is transferred from the disk device 3 to the host processor 2, the data read from the disk device 3 by the disk device data reading circuit 58 is transferred to the host processor 2 by the read data transfer circuit 52 via the host interface 50.

When data is transferred from the disk device 3 to the cache memory 56, the data read from the disk device 3 by the disk device data reading circuit 58 is transferred to the cache data writing circuit 55 via the read data transfer circuit 52 and the write data transfer circuit 53. The data is then written into the cache memory 56 by the cache data write circuit 55.

In this case, since the data of the disk device 3 is stored in physical sector units made up of multiple logical sectors, the data of the disk device 3 is stored in the cache memory 56 in physical sector units or cache block units for each logical sector. Ru.

Data from host processor 2 is transferred to cache memory 5
6, data transferred from the host processor 2 via the host interface 50 is transferred to the cache data write circuit 55 via the write data transfer circuit 53, and the data is transferred to the cache memory by the cache data write circuit 55. 56.

Furthermore, even when a high-speed write command is output to write data from the host processor 2 only to the cache memory 56, the host processor 2 is written to cache memory 56.

Further, when partially writing data from the host processor 2 to the cache memory 56, the data read from the disk device 3 by the disk device data reading circuit 58 is transferred to the write data transfer circuit 53 via the read data transfer circuit 52. , the data and the data transferred from the host processor 2 via the host interface 50 are merged by the write data transfer circuit 53 and transferred to the cache data write circuit 55, and the merged data is transferred to the cache data write circuit 55. The data is written to the cache memory 56 by the following.

When writing data from the host processor 2 to the disk device 3, the data transferred from the host processor 2 via the host interface 50 is transferred to the disk device data write circuit 59 via the write data transfer circuit 53.
The data is written to the disk unit W3 by the disk unit data writing circuit 59.

When writing data stored in the cache memory 56 to the disk device 3, the cache data reading circuit 5
7 transfers the data read from the cache memory 56 to the disk device data writing circuit 59, and the data is written to the disk device 3 by the disk device data writing circuit 59.

In this case, since data is stored in the cache memory 56 in units of logical sectors, the data in units of logical sectors read from the cache memory 56 by the cache data reading circuit 57 is converted into units of physical sectors by the disk device data writing circuit 59. The data is written to the disk device 3.

Data transfer between the host processor 2, disk device 3, and cache memory 56 is managed by the microprocessor 51, and the cache memory 56 is managed based on management information stored in the directory memory 54.

In such a conventional disk cache control device 5,
Since data in units of logical sectors from the cache memory 56 is written in units of physical sectors to the disk device 3, when data is written to the cache memory 56 at high speed in the form of partial writing, the logical sector rewritten by this high-speed writing Since the contents of the other logical sectors become undefined, there is a drawback that data in the cache memory 56 that has been rewritten by high-speed writing cannot be written to the disk device 3.

OBJECTS OF THE INVENTION The present invention has been made to eliminate the drawbacks of the conventional devices as described above, and provides a disk cache control device that can write cache memory data written at high speed in the form of partial writing to a disk device. For the purpose of providing.

Composition of the Invention A disk cache control device according to the present invention connects a disk device that stores data in physical sector units consisting of a plurality of logical sectors and a host device, and stores part of the data stored in the disk device in a logical manner. A disk cache control device having a cache memory held in sector units, which stores update information when a part of the plurality of logical sectors held in the cache memory is updated by data from the host device. storage means for
a transfer unit that transfers data read from the disk device to the cache memory in units of logical sectors; and a transfer unit that transfers data in units of logical sectors transferred by the transfer unit based on the update information of the storage unit to the cache memory. The invention is characterized in that it is provided with a control means for controlling writing to.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, a host interface 10 in a disk cache control device 1 transfers data transferred from a host processor 2 via a bus 102 to a write data transfer circuit 13 via a bus lit, and transfers read data via a bus 112. By transferring the data transferred from the transfer circuit 12 to the host processor 2 via the bus 102, data transfer between the host processor 2, the disk device 3, and the cache memory 18 is performed. lll, 114-1
20, a host interface 10, a read data transfer circuit 12, a write data transfer circuit 13, a sub-processor 15, a cache data write circuit 17, a cache data read circuit 19, a disk device data read circuit 20, By controlling the disk device data writing circuit 21, the host processor 2
It manages data transfer between the disk drive 3 and the cache memory 18, and exchanges response signals such as completion reports with the host processor via the bus 111, host interface 10, and bus 101.

The read data transfer circuit 12 transfers data transferred from the cache data read circuit 19 and the disk device data read circuit 20 via buses 123 and 124, respectively, to the host interface 10 via buses 112 and 122.
and the write data transfer circuit 13, the data read from the disk device 3 is transferred to the host processor 2 and the cache memory 18, and the data read from the cache memory 18 is transferred to the host processor 2.
Transfer to.

The write data transfer circuit 13 transfers the data transferred from the host interface 10 via the bus 113 to the cache data write circuit 1 via buses 125 and 128.
7 and the disk device data writing circuit 21, the data from the host processor 2 is transferred to the disk device 3 and the cache memory 18, and the data read from the disk device 3 is transferred to the cache memory 18.
Transfer to.

Further, when partially writing data from the host processor 2 to the cache memory 18, the write data transfer circuit 13 writes the data from the host processor 2 transferred from the host interface 10 via the bus 113,
Merges the data from the disk device 3 transferred from the read data transfer circuit 12 via the bus 122,
The merged data is written into the cache memory 18 by being transferred to the cache data writing circuit 17 via the bus 126.

The directory memory 14 stores management information of the cache memory 18, and also stores information on high-speed writing and partial writing to the cache memory 18 by the host processor 2, and communicates with the microprocessor 11 and sub-processors via buses 121 and 127. Referenced by processor 15.

The sub-processor 15 controls the cache logical sector data transfer circuit 16, the cache data write circuit 17, and the disk device data reading circuit 20 via buses 128 to 130, respectively, thereby controlling the connection between the disk device 3 and the cache memory 18. Controls data transfer between

Cache logical sector data transfer circuit 16 connects to bus 132
By transferring the data transferred from the disk device data transfer circuit 20 via the bus 131 to the cache data writing circuit 17 in units of logical sectors, the data in units of physical sectors read from the disk device 3 is transferred to the cache data writing circuit 17 via the bus 131. The data is transferred to the cache memory 18 in units of sectors.

Cache data write circuit 17 uses buses 128 and 111
By writing the data transferred from the write data transfer circuit 13 and the cache logical sector data transfer circuit 16 via the bus 133 to the cache memory 18, the data from the host processor 2 and the disk device 3 can be stored in the cache memory. 18, and data in logical sector units from the cache logical sector data transfer circuit 16 is written to the cache memory 18.

The cache memory 18 stores part of the data stored in the disk device 3 in units of logical sectors.

The cache data reading circuit 19 transfers the data read from the cache memory 18 via the bus 184 to the bus 123.
, 135 to the read data transfer circuit 12 and the disk device data write circuit 21,
Data read from cache memory 18 is transferred to host processor 2 and disk device 3.

The disk device data reading circuit 20 transfers the data read from the disk device 3 via the bus 13B to the bus 124.1.
32 to the read data transfer circuit 12 and cache logical sector data transfer circuit 16, data read from the disk device 3 is transferred to the host processor 2 and cache memory 18.

The disk device data writing circuit 21 is connected to the bus 125°11.
By writing the data transferred from the write data transfer circuit 13 and the cache data read circuit 19 via the bus 137 to the disk device 3 via the bus 137, the data transferred from the host processor 2 and the cache memory 18 is written. is written to the disk device 3 in units of physical sectors.

FIG. 2 is a flowchart showing the operation of one embodiment of the present invention. The operation of an embodiment of the present invention will be explained using FIG. 1 and FIG. 2.

In addition, when the data stored in the cache memory 18 is rewritten by the host processor 1 in the form of partial write at high speed, the following describes the operation for handling the data written to the cache memory 18 at high speed in units of physical sectors. explain.

Information about high-speed write data transferred from the host processor 2 to the cache data write circuit 17 via the host interface 10 and the write data transfer circuit 13 and written from the cache data write circuit 17 to the cache memory 18 is stored in the directory memory 14. microprocessor 11 is stored on bus 12.
1 reads information in the directory memory 14 through the
It is checked whether a partial write exists in the file that has been written at high speed by the host processor 2 (step 31 in FIG. 2).

If there is no partial writing in the file that has been written at high speed (step 32 in FIG. 2), the process ends.

Furthermore, if a partial write exists in the file that has been written at high speed (step 32 in FIG. 2), the microprocessor 11 instructs the subprocessor 15 to start up via the bus 120 (step 33 in FIG. 2). ).

When the sub-processor 15 is activated by an instruction from the microprocessor 11, it reads information from the directory memory 14 via the bus 127, and checks the address of the physical sector where the partial write was performed in the file where the high-speed write was performed ( Figure 2 step 34).

After that, the sub-processor 15 executes the directory memory 1
Check whether the disk drive W3 containing the physical sector address obtained from the information in Step 4 is available for use (Step 3 in Figure 2).
5).

If the disk device 3 is not usable (step 36 in FIG. 2), the subprocessor 15
It will wait until it becomes available.

If the disk device 3 is usable (step 36 in FIG. 2), the subprocessor 15 communicates with the disk device data reading circuit 20 via the bus 180 by performing partial writing in the file that has been written at high speed. The data in the logical sector portion that has not been updated is read from the disk device 3 and transferred to the cache logical sector data transfer circuit 1.
Outputs an instruction to transfer to 6.

The disk device data reading circuit 20 reads the disk device 3 via the bus LH according to instructions from the subprocessor 15.
After reading data from the disk device 3 and transferring the data from the disk device 3 to the cache logical sector data transfer circuit 16 via the bus 132, a transfer completion report is sent to the sub-processor 15 via the bus 130.

The sub-processor 15 is a disk device data reading circuit 2
Upon receiving the transfer completion report from 0, it instructs the cache logical sector data transfer circuit 16 via the bus 128 to transfer the data transferred from the disk device data reading circuit 20 to the cache data writing circuit 17. Output (step 37 in Figure 2).

The cache logical sector data transfer circuit 16 transfers data transferred from the disk device data reading circuit 20 in response to instructions from the subprocessor 15 to the cache data writing circuit 17 via the bus 131 in units of logical sectors.
When transferred to sub-processor 15 via bus 128
Report the completion of the transfer.

If the subprocessor 15 does not receive a transfer completion report from the cache logical sector data transfer circuit 16 (step 38 in FIG. 2), it waits until a transfer completion report is sent from the cache logical sector data transfer circuit 16. becomes.

Further, when the sub-processor 15 receives a transfer completion report from the cache logical sector data transfer circuit 16 (step 38 in FIG. It is checked whether an error has been detected (step 39 in FIG. 2), and if an error is detected during the data transfer, the process moves to error processing.

If no error is detected during the data transfer, the sub-processor 15 sends the data transferred from the cache logical sector data transfer circuit 16 via the bus 133 to the cache data write circuit 17 via the bus 129. An instruction is output to write to the logical sector part that has not been updated in the physical sector in which the partial writing of the memory 18 has been performed (step 40 in FIG. 2).

In the cache data writing circuit 17, the sub processor 1
The data transferred from the cache logical sector data transfer circuit 16 according to instructions from the cache memory 1
When the data is written to the logical sector portion which has not been updated in the physical sector where the partial writing of No. 8 has been performed, a completion report is sent to the sub-processor 15 via the bus 129.

In the sub-processor 15, the cache data write circuit 1
If no completion report is sent from the cache data writing circuit 17 (step 41 in FIG. 2), the cache data writing circuit 17 enters a waiting state until a completion report is sent from the cache data writing circuit 17.

Further, when the sub-processor 15 receives a completion report from the cache data write circuit 17 (step 41 in FIG. 2), the sub-processor 15 determines whether an error has been detected in the data write to the cache memory 18 by the cache data write circuit 17. If an error is detected during data writing (step 42 in FIG. 2), the process moves to error processing.

Further, if no error is detected during the data writing, the subprocessor 15 reports to the microprocessor 11 via the bus 120 that the data writing to the cache memory 18 has been completed (step 43 in FIG. 2).
The operation for handling data written to the cache memory 18 at high speed in units of physical sectors is completed.

In this way, data that is written to the cache memory 18 at high speed in the form of partial writing is transferred from the cache logical sector data transfer circuit 16 to the logical sector portion that has not been updated in the physical sector where the partial writing has been performed. By writing the data from the disk device w3 in logical sector units under the control of the sub-processor 15, the data in the cache memory 18 is written to the disk device f.
3, even if data can only be processed in physical sector units, the data written to the cache memory 18 at high speed in the form of a partial write can be handled in units of physical sectors. The written data can be recorded on the disk device 3.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, for data written to a cache memory at high speed in the form of a partial write, a logical By writing data transferred from the disk device in units of sectors, it is possible to write data in the cache memory that has been written at high speed in the form of partial writing to the disk device.

[Brief explanation of drawings]

′! s1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a flowchart showing the operation of the embodiment of the present invention, and FIG. 3 is a block diagram showing the configuration of a conventional example. Explanation of symbols of main parts 1...Disk cache control device 2...
...Host processor 3 ...Disk device 11 ...Microprocessor 14 ...Directory memory 15 ...Subprocessor 16 ...Cache logical sector Data transfer circuit 17...Cache data write circuit 18...
...Cache memory 20...Distribution device data reading circuit

Claims (1)

[Claims] (1) A disk device that stores data in physical sector units consisting of multiple logical sectors is connected to a host device, and has a cache memory that holds part of the data stored in the disk device in logical sector units. A disk cache control device, when a part of the plurality of logical sectors held in the cache memory is updated by data from the host device, a storage means for storing updated information; a transfer means for transferring the read data to the cache memory in logical sector units; and a transfer unit for writing the data in logical sector units transferred by the transfer means to the cache memory based on the update information of the storage means. 1. A disk cache control device comprising: a control means for controlling the disk cache.