JPH04148352A - Address converting system for information processor equipped with plural processor - Google Patents

Abstract

PURPOSE:To enable an address conversion at a high speed by using a TLB provided at each address convert feature of plural processors. CONSTITUTION:When a physical address can not be obtained by a TLB 11 in its own device at each processor 1, the address conversion using the TLB provided at the other processors is required for the other processors. As a result, when the physical address can be obtained, an access to a main storage device 3 is performed by using the physical address, and when the physical address cannot be obtained, the address conversion is operated by an address conversion table, and then the access to the main storage device 3 is operated. Thus, the address conversion can be operated at high speed by adding a hardware in small quantities to an information processor equipped with plural processors.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] The present invention relates to an address translation method in an information processing device in which a common virtual storage type main storage device and a plurality of processors each having an address translation mechanism each equipped with a TLB are coupled via a bus.

The purpose is to provide an address translation method for an information processing device equipped with multiple processors that can speed up address translation by using TLB provided in each address translation mechanism of multiple processors.Each processor performs address translation using a logical address. The conversion request processing means of the other processor is provided with a conversion request processing means which is activated when there is no corresponding physical address and sends a conversion request to another processor.

When the conversion request is received, the conversion is performed by the TLB of the own device and the result is sent to the request source, and when the request source processor receives the result, if the conversion is successful, it registers the physical address in the TLB of the own device. The main storage device is accessed, and when conversion is unsuccessful, an address conversion table in the main storage device is searched to perform address conversion.

[Industrial application field] The present invention uses a common virtual storage type main storage device.

The present invention relates to an address translation method in an information processing device in which a plurality of processors each having an address translation mechanism each equipped with a TLB are coupled via a bus.

In recent years, virtual storage, which has a virtual storage space larger than the capacity of an actual storage device, has been widely used in storage device technology for summer equipment. This virtual memory is accessed using logical addresses such as segments and pages, and an address conversion mechanism is used to convert this into an actual storage device address (real address or physical address). The address conversion requires a mechanism that indexes a table of segments and pages stored in the main memory, and a mechanism that performs the conversion using TL B (T
ranslation Lookaside Buff
A mechanism that performs high-speed operation using associative memory called er) is used.

On the other hand, multiple processors are connected by a bus.

2. Description of the Related Art Information processing apparatuses are known in which each processor uses a common main memory. In such information processing devices, a method is adopted in which storage space is widely utilized by virtual memory.

[Conventional technology] FIG. 5 is an explanatory diagram of a conventional example.

In FIG. 5, 30 is a manual logical address, 31 is a segment table starting point register, 32 is a segment table, 33 is a page table, 34 is a main memory, and 35 is a TLB (Translation Lookas).
ide Buffer).

In this traditional example, the logical address (or virtual address)
is divided into three parts, as shown in the input logical address 30 in Figure 1, consisting of a segment (indicated by SX), a page (indicated by PX), and a displacement within the page (indicated by DX).

When converting such a logical address into a physical address (or real address), as shown in FIG. The read content of the th entry is the starting point address PTO of one specific page table 33. When the contents of page PX in the input logical address 30 are read from this starting point address PTO, the address RA (address of page number) in the entry is read. By adding the displacement DX of the input logical address 30 to this address RA, the final physical address of the main storage device is obtained.

If such a conversion is performed, in TLB35.

Each piece of information at this time, ie, the segment table starting point register STO, segment SX, page PX, and address (RA) obtained by conversion, are registered.

A large number of pieces of this information are registered in the TLB 35, and when the next dynamic conversion is performed, when a logical address is input to this TLB 35, the associative memory function will output a converted address (RA) if the respective values match. Therefore, high-speed virtual address conversion is realized.

Such a virtual storage method can also be applied to an information processing device in which a plurality of processors and a common main storage device are connected via a bus. In that case, by providing each processor with an address translation mechanism each having a TLB, access to the main memory can be speeded up.

[Problems to be Solved by the Invention] In an information processing device in which a plurality of processors and a common main storage device are connected by a bus, each processor is provided with an address translation mechanism including a TLB, and the TLB is provided with a logical (virtual) address translation mechanism.
If there is a physical address corresponding to the address, it can be used to increase the speed of access to the main memory.

However, in each processor, if a physical address is not always obtained (not hit) in response to a logical address input to the TLB, the address translation mechanism uses the address translation table in the main memory (the segment table in the conventional example shown in FIG. 5). , page table) to obtain the physical address. There is a problem in that address translation in this case takes time.

On the other hand, the TLB cannot use a large amount of high-speed content addressable memory devices due to hardware or economical limitations, which limits the speed of address translation.

SUMMARY OF THE INVENTION An object of the present invention is to provide an address translation method for an information processing apparatus equipped with a plurality of processors, which can speed up address translation by using TLBs provided in the address translation mechanisms of each of the plurality of processors.

[1! [Means to solve the problem] FIG. 1 is a diagram showing the principle configuration of the present invention.

In FIG. 1, 1 is a processor unit, IO is a processor, 11 is an address translation mechanism equipped with TLB, and 12
13 is a conversion request processing means; 13 is a main storage device access means;
2 is a bus, and 3 is a common main storage device.

In the present invention, when each processor cannot obtain a physical address using the TLB in its own device, it requests other processors to perform address translation using the TLB provided in the other processor, and when a physical address is obtained as a result, the physical The main memory is accessed using an address, and if a physical address cannot be obtained, the address is translated using an address translation table before accessing the main memory.

The address conversion at this time may be provided in each CPU or may be provided in the main memory.

[Operation] When a logical (virtual) address for the main memory 3 is generated from the processor 10 in the processor unit l, the address conversion mechanism 11 converts it into a physical address. A read or write request is sent from the device access means 13 to the main storage device 3 via the bus along with a physical address.

If the address translation mechanism 11 cannot obtain a physical address, the processor 10 activates the translation request processing means 12 to supply a logical address. The conversion request processing means 12 sends an address conversion request to one or all processors with a logical address attached to the bus 2.

When the other processor unit 1 receives this request with the conversion request processing means 12, the address conversion mechanism 11 of the own device
The conversion is performed by supplying a logical address to the When a physical address is obtained from the TLB of the address translation mechanism 11, it is sent from the translation request processing means 12 to the requesting processor unit 1. When the requesting processor unit receives this in the conversion request processing means 12, it accesses from the main memory access means I3 using the physical address.

If a physical address cannot be obtained from another processor, a response indicating that there is no physical address is notified.

In this case (including when there is no response from other processors)
, the main storage device 3 is accessed by the logical address from the main storage device access means 13, the physical address is obtained using the address conversion table of the main storage device 3, and the access to the main storage device is executed using the physical address. be done.

[Embodiment] FIG. 2 is a configuration diagram of an embodiment, FIG. 3 is a configuration example of each command, and FIG. 4 is a processing flow in each processor unit.

In FIG. 2, 20A is the own processor unit, 20
B is another processor unit, 21 is a processor, 22 is a TLB, 23 is an address conversion circuit 24, a buffer memory, 25 is an interface section 26, a bus, 27 is a main storage device, and 28 is a conversion table.

In the illustrated example, it is the processor unit 20.

In the case where both 2OA and 20B are provided,
Any number of them can be provided.

The processing flow for address conversion in each processor unit 20A, 20B will be explained with reference to FIG.

In other words, the processor 2 of the second processor unit 20A
1, a logical address is generated to retrieve an operand or instruction to the main memory 27 (40 in FIG.
), the address translation circuit 23 searches the TLB 22 based on the received logical address (41), if the TLB 22 has a physical address corresponding to the logical address.

Using the obtained physical address, the buffer memory 24 or main storage device 27 is accessed by a command via the interface section 25 (43).

The format of the command at this time is shown in Figure 3, and A
, is the formant for reading.

B is the format for writing.

In this format, ID is the identification number of the processor that issued the command.Second is the command instruction (Read, Write).
te), the next is the physical address, and the data is the one at the time of writing.

FIG. 3 C1 shows a response command from the main storage device to the read command, where rD is a code representing the response (Re
ply), data.

As a result of this address conversion, if there is no corresponding physical address in the TLB 22, the address conversion circuit 23 sends a conversion request command from the interface section 25 to the other processor unit 20B (42). The format is shown in Figure 3. In other words, the publisher's In(by Illl number), TLB
Request, logical address, start address of segment table (distinguished from virtual address of land user)
, and in the case of multiple virtual machines, a number (■MID) etc. for identifying the virtual machine is added.

This command is received by the interface unit 25 of the other processor unit 20B, and when it is detected as a conversion request command (44), its contents are sent to the address conversion circuit 23. The address conversion circuit 23 of the other processor that received the conversion request uses the TLB 22 to search for a physical address based on the logical address sent.
5).

If there is a corresponding physical address, a response command containing that physical address is sent via the interface 25 to the bus 26.
(46).

The format of this response command is 10.0 as shown in FIG. TLB response (Repl
y), physical address, etc.

If there is no corresponding physical address in the TLB 22 of another processor unit 20B, the address conversion circuit 23
Notifies the conversion failure by a response command (not shown) (47).

The interface section 25 of the own processor unit 20A that is the source of the conversion request receives a response from another processor using the ID representing the own processor unit, and sends it to the address conversion circuit 23. The address conversion circuit 23 decodes the sent response (see 48), and if it finds that it is a physical address, it uses that physical address to access the buffer memory or sends a command to the main storage device 27 (see Figure 3). A,)
(43), in this case, the address conversion circuit 23 registers the physical address corresponding to the logical address in the TLB 22.

If a notification of conversion failure is received from another processor unit 20B, the address is converted from a logical address to a physical address using the conversion table 28 on the main memory 27 (49), and the converted address is registered in the TLB 22. , the buffer memory or main storage device 27 is accessed using the converted physical address.

[Effects of the Invention] According to the present invention, address translation can be realized at high speed in an information processing device including a plurality of processors by adding a small amount of hardware.

[Brief explanation of the drawing]

Figure 1 is a diagram of the principle of the present invention, Figure 2 is a diagram of the embodiment, Figure 3 is an example of the configuration of each command, Figure 4 is the processing flow in each processor unit, and Figure 5 is a diagram of the conventional example. It is an explanatory diagram. In Figure 1. 1: Pro sensor unit 10: Processor 11 Near address conversion mechanism 12: Conversion request processing means 13: Main memory access means 2: Hasu 3: Main memory

Claims (1)

[Scope of Claims] In an information processing device in which a main storage device using a common virtual storage system and a plurality of processors each having an address translation mechanism each equipped with a TLB are coupled via a bus, each processor can perform address processing using a logical address. The conversion request processing means is provided with a conversion request processing means that starts when there is no physical address corresponding to the conversion and sends a conversion request to another processor, and when the conversion request processing means of the other processor receives the conversion request, it performs the conversion using the TLB of its own device. When the requesting processor receives the result, if the conversion is successful, it registers the physical address in its own TLB and accesses the main memory, and if the conversion is unsuccessful, it sends the result to the request source. An address conversion method for an information processing device including multiple processors, characterized in that address conversion is performed by searching an address conversion table in a storage device.