JPH0414879A - Semiconductor device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Technical Field] The present invention relates to a semiconductor device, an active matrix substrate, and a semiconductor device having a semiconductor thin film having a large crystal grain size and uniform crystal orientation on an insulating substrate formed by a sol-gel method. The present invention relates to a contact image sensor with a built-in drive circuit.

[Prior art]

In recent years, parasitic capacitance has been reduced to improve transistors and integrated circuits (L
In order to increase the speed and reduce power consumption of SI), the development of techniques for creating these devices in semiconductor thin films on insulating substrates is being actively conducted.

Among these technologies, there are known ones that use a single crystal insulating substrate (for example, sapphire) (SO5 technology) and those that use an amorphous insulating substrate (for example, quartz) (SOI technology).

Among them, graphoepitaxy technology is a typical example of the latter. This technology is based on Applied Physics Letters (Ap.
pl, Phys, Lett, Vol. 35゜p, 71 (1979), etc., by periodically forming micron-order striped irregularities on an amorphous insulating substrate such as quartz, A silicon thin film is provided thereon. Silicon atoms are regularly arranged in narrow concave stripes on the order of microns, and a single-crystal silicon thin film is obtained even though it is on an amorphous insulating substrate.

However, the above-mentioned conventional technology requires ultra-fine processing on the micron order using photolithography technology, so the processing accuracy is strict and the shape of the unevenness cannot be sufficiently controlled. It was difficult to control the film quality and crystallinity of the thin film.

Therefore, Japanese Patent Application Laid-Open No. 1-270312 proposes forming an insulating substrate by a sol-gel method and creating periodic irregularities on the surface. Since the irregularities are stripes with a width on the order of microns, there is a high possibility that a single crystal silicon thin film will be obtained even though the underlying layer is amorphous.

However, the stripe-like unevenness with a width on the order of microns in the above-mentioned Japanese Patent Application Laid-Open No. 1-270312.

Considering controllability, stability, reproducibility, etc., the stripe size is 0.1 μm to 1 μm, and the depth of unevenness is 0.01 μm.
The limit is approximately 2 μm, and it is difficult to form an ideal single crystal thin film as in the case of applying grapho-epitaxy technology.

Furthermore, although it depends on the dimensions of the surface unevenness pattern, the method disclosed in JP-A-1-270312 has difficulty controlling the crystal orientation and poor reproducibility, and as a result, it is difficult to form a semiconductor thin film with the desired crystal orientation. be. In other words, when crystallization occurs based on an uneven surface as shown in Figure 5, various crystals are formed, such as a <220> crystal in the A plane orientation and a (100) crystal in the B plane orientation. A direction will occur.

Although various proposals have been made regarding the formation of single crystal thin films on other insulating substrates, control of crystal orientation is still far from satisfactory.

〔the purpose〕

An object of the present invention is to employ the uneven substrate forming method disclosed in Japanese Unexamined Patent Application Publication No. 1-2703/2003 and eliminate the drawbacks of semiconductors caused by the method.

〔composition〕

That is, the present invention relates to a semiconductor device characterized in that a first semiconductor thin film and a second semiconductor thin film are laminated on an insulating substrate formed by a sol-gel method and having periodic irregularities on its surface. It is preferable that the unevenness has a seven-figure shape.

Insulating substrates in the present invention include quartz, metal oxides, spinel, composite oxides, and the like, and all of these substrates are manufactured by the sol-gel method. That is, the insulating substrate of the present invention is produced using a hydrolysis reaction of an alkoxide compound.

For example, in the case of a quartz substrate, high-purity silica gel is first produced by adding pure water to ethyl silicate while controlling the hydrogen ion concentration. This gel is placed in a container of a predetermined size to form a flexible sol, and then a desired uneven pattern to be transferred, preferably an uneven pattern having a plane orientation that allows crystal growth of the first semiconductor thin film in the (11,1) direction, For example, pressing a suitable mold having a serrated figure 7 pattern will transfer the pattern.

After that, it was dried at 60°C for 200 hours, and then dried for 10 hours.
A firing treatment is performed at 00°C to 1200°C, preferably at 1200°C for 2 hours. This heat treatment results in approximately 1/1/2 of the initial shape.
A 5i02 board with a reduced size of 2 is created. On the surface of this quartz substrate, irregularities on the order of microns or less are formed.

The first semiconductor thin film formed on the uneven surface of the insulating substrate is made of silicon, germanium compound semiconductors (gallium arsenide, indium, zinc selenide, etc.).
The first semiconductor thin film is subjected to a crystal growth treatment after the film is formed. Although there are various crystal growth methods, normal epitaxial growth may be used, or a polycrystalline semiconductor thin film may be deposited and annealed with heat, laser light, electron beam, etc. to form a single crystal. The crystal orientation of the film obtained by this single crystallization can be controlled by the unevenness formed on the surface of the base 5i02 substrate.

For example, if the first semiconductor thin film is made of polycrystalline silicon formed by low pressure CVD, after forming the polycrystalline silicon film,
When the film is annealed, it can be made into a single crystal. The annealing treatment is preferably carried out at 500° C. or higher, preferably 600° C., with an inert atmosphere such as Ar in the furnace.

The annealing process reduces the unevenness on the insulating substrate to <111
〉 crystal orientation, the polycrystalline silicon film, that is, the first semiconductor thin film can be aligned in <Ul>. This is because the surface unevenness has a surface profile on the order of an atomic size or less, which is less than a micron size.

The thickness of the first semiconductor thin film described above is usually about 400. The (111) crystal grown along the figure 7 plane is 5
When the film thickness exceeds 00 Å, other plane orientations begin to appear (for example, <220>, <311>).

Although this itself is not preferable, since the above-mentioned annealing creates an ideal (111) plane, there is no need to particularly limit the film thickness. This first semiconductor thin film layer secures a basic orientation plane for crystal growth of the second semiconductor thin film.

The second semiconductor thin film is made of the same material as the first semiconductor thin film, such as silicon or germanium compound semiconductors (gallium arsenide, indium phosphide, zinc selenide, etc.), and the first semiconductor thin film and the second semiconductor thin film are the same. I have the materials,
N may be laminated with a combination of different materials.

The second semiconductor thin film can be formed by a known method, and is preferably formed so that the surface is flat. Since the second semiconductor thin film has the <111> orientation plane of the first semiconductor thin film, the <111> orientation can be maintained even if a considerably thick film (for example, several cm) is formed thereon.

This second semiconductor thin film functions as an active layer of the transistor.

The drawings with 1m will be explained below.

FIG. 1 shows a substrate 101 in a sol state in the sol-gel method.
A suitable mold 11 having the desired uneven pattern to be transferred to the
Pressing 1 indicates that the pattern is being transferred.

FIG. 2 shows that after forming a first semiconductor thin film 2 on an insulating substrate 1 which has been given a concavo-convex pattern and has been subjected to the drying and baking process described above, the film is formed into a single crystal thin film in <11.1>. The figure shows the shape of the surface unevenness when the surface is exposed.

FIG. 3 shows a state in which a second semiconductor thin film is provided on the first semiconductor thin film.

After forming the second semiconductor thin film, a suitable device is manufactured using the film as an active layer, thereby making it possible to manufacture a semiconductor device as shown in FIG. 4.

FIG. 4 is a sectional view showing a specific example of the semiconductor device of the present invention, showing the surface unevenness shape when the first semiconductor thin film 2 is formed as a <111> single crystal thin film, and the second semiconductor thin film 2 FIG. 3 is a diagram showing a case where a MOS transistor is formed using a silicon thin film.

The second semiconductor thin film, that is, the active layer 3 as a transistor, is separated and removed in an island shape, and a gate electrode 5 is provided via a gate insulating film 4 such as 5i02.
A source train 6 is formed in a self-aligned manner. 5
There is an aluminum-based metal wiring 8 via a glabellar insulating film 7 such as i02.

〔Example〕

Pure water was added to ethyl silicate to produce high purity silica gel. This gel was filled into a container and turned into a sol for 150 hours.

A mold having a V-shaped pattern was transferred onto the surface of this sol-formed substrate.

The substrate after transfer was dried at 60° C. for 200 hours.

It was further fired at 1200° C. for 2 hours to obtain a quartz insulating substrate that was 172 times smaller than the sol-like shape.

As a first semiconductor layer on the surface of the quartz insulating substrate, a low pressure CV
A polycrystalline silicon film with a thickness of 30 nm was deposited using the D method, and the film was annealed at 600° C. in an Ar atmosphere.

Thereafter, a 1 μm thick Po1y-5i film was deposited as a second semiconductor layer serving as an active layer by LPCVD, and the MOS transistor shown in FIG. 4 was fabricated by a known method.

It was confirmed that this MOS transistor is a device that operates at high speed with little parasitic capacitance and operates with low power consumption.

〔effect〕

According to the present invention, it is possible to provide a semiconductor device that operates at high speed with little parasitic capacitance and operates with low power consumption.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram showing a state in which a mold with a concavo-convex pattern is pressed against a sol-like substrate, FIG. 2 is an explanatory diagram showing a state in which a first semiconductor thin film is deposited on an insulating substrate, and FIG. An explanatory diagram showing a state in which a second semiconductor thin film is further deposited as an active layer, FIG. 4 is a sectional view showing a specific example of the semiconductor device of the present invention,
FIG. 5 shows a conventional type of uneven shape. 1... Insulating substrate 2... First semiconductor thin film 3... Second semiconductor thin film (active layer) 4... Gate insulating film 5... Gate electrode 6... Source/drain 7...・Interlayer insulating film 8...Metal wiring 101...Sol state substrate 111...Mold

Claims (1)

[Claims] 1. A semiconductor device characterized in that a first semiconductor thin film and a second semiconductor thin film are laminated on an insulating substrate having periodic irregularities on the surface formed by a sol-gel method.