JPH0414958A - Picture area identification device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an image area identification device commonly used in digital copying machines, facsimile machines, scanners, etc. The present invention relates to an image area identification device that is characterized in that it automatically identifies whether or not it is an image area.

[Conventional technology]

For example, in a digital copying machine, a CCD (charge-coupled device) image sensor or the like is used to read a document image in minute areas, that is, pixel by pixel, and the analog electrical signals obtained from the output of the image sensor are converted into an A/D converter. (
After performing various processing on the resulting digital signal, the signal is sent to a recording device to obtain a copy image.

By the way, in the printing apparatus used in this type of apparatus, it is difficult to change the density level for each printing pixel, so it is common to perform binary or multi-value printing of printing/non-printing. However, since a document may also include halftone images such as photographs, it is necessary to reproduce halftone images. Conventional methods for expressing halftones using recording devices that perform binary or multilevel recording include the dither method, density pattern method, submatrix method, and error diffusion method. If used, halftone images can be reproduced.

However, when halftone processing is performed, a relatively favorable copy image can be obtained when the original image density changes gradually, such as in a photograph, but when the original image density changes in a binary manner, such as with text, a relatively favorable copy image can be obtained. In this case, the outline of the copy image becomes blurred, making it difficult to read characters, and dirt on the background of the original appears on the copy image, resulting in a significant deterioration in copy quality.

For original images such as characters, a preferable copy can be obtained by performing simple binary or multivalue processing without performing halftone processing. Therefore, if a switch is provided to specify whether halftone processing is to be performed or not, a preferred copy mode can be selected based on the operator's judgment depending on the type of document.

However, there are many cases in which a single document, such as a pamphlet, contains both a half-tone image such as a photograph and a binary image such as text. In such cases, selecting binary or multilevel mode will reduce the quality of the photo,
Selecting halftone mode will reduce the quality of the text.

By the way, there is one more thing about this type of digital copying device.
There are two disadvantages. In other words, when reading an image in small pixel units using a line sensor or the like, if there is periodicity in density changes on the document, interference between the period (pitch) and the array pitch (sampling period) of the image reading sensor causes Moiré may occur on recorded images. For example, when halftone dot printing is performed on a document, the density changes on the image have periodicity, and moiré occurs due to interference between the density change period and the sampling period of the reading sensor.

For example, if the resolution of the image reading sensor is 400 dpi, dot printing with a density close to that resolution, that is, 1
When the density is in the range of 33 lines (approximately 10.5 pixels/mrn) to 200 lines (approximately 16 pixels/mrn), moire is likely to occur in the read signal. Of course, moiré occurs at other densities as well, but at the above-mentioned density, the occurrence is particularly severe, and the resulting signal fluctuation range is large.

Halftone printing itself is a kind of pseudo-halftone expression, and the density change in pixel units is a binary value of 110 (recorded/non-recorded). In halftone printing, the average density of the entire pixel set is changed in multiple steps by changing the pitch of the halftone dots and the size of the halftone dots, thereby expressing halftone density. Therefore, if we do not consider the moiré problem,
When copying a halftone dot printed original image, by processing the signal in a binary manner, it is possible to reproduce the halftone dot image in the recorded image and perform a preferable copy. However, in reality, moiré occurs as described above in a document image printed with halftone dots at a specific density, resulting in a significant deterioration in copy quality.

On the other hand, when converting an image reading signal into a binary or multivalued signal through halftone processing, the processing process averages the density of multiple pixels, changes the threshold level, etc., resulting in a copied image. Moiré does not occur or its effect is reduced. In this case, the density of the copied image is represented by halftone dots, but the halftone dots on the copy are not direct reproductions of the halftone dots on the original, but are generated by halftone processing unique to copying machines. It is a point.

Therefore, if the original is a halftone-printed image or an image copied using halftone processing by a digital copying machine, it is better to select a copy mode that performs halftone processing, although it is binary recording in pixel units. is preferred.

Furthermore, as mentioned above, it is sufficient to perform simple binary or multi-value processing for the text area, and halftone processing such as dithering for the halftone area.
A method of performing area division may also be considered. For example, JP-A-6
As shown in Publication No. 3-279665, by detecting halftone dot areas, performing halftone processing on the halftone dot areas, and performing simple binarization on the rest, the text and halftone photographic areas can be output as good images. be able to.

In the halftone dot area detection method disclosed in Japanese Patent Laid-Open No. 63-279665, recorded dots and non-recorded dots are detected by comparing a two-dimensional array pattern of input image information with a predetermined pattern. Based on the result, it is determined whether the input image information is a halftone pattern.

In a halftone-processed image, recorded dots (for example, black pixels) and non-recorded dots (for example, white pixels) are alternately and repeatedly arranged at predetermined pitches and intervals. Therefore, a recording pixel existing at a certain position and non-recording pixels existing around it are in a predetermined arrangement pattern, or a non-recording pixel existing at a certain position and recording pixels existing around it are arranged in a predetermined arrangement pattern. If a predetermined arrangement pattern repeatedly appears, the pixel can be considered to have been halftone-processed. In other words, by sequentially moving the pixel of interest and comparing the image information of a two-dimensional area consisting of it and its surrounding pixels for each pixel of interest with a predetermined recorded dot detection pattern and non-recorded dot detection pattern, It is possible to identify whether the input image is a halftone dot pattern or not.

However, when an image subjected to halftone dot processing is actually read by an image scanner, the image pattern of the read signal changes greatly depending on the density of the image, often resulting in errors in halftone dot identification. That is, in halftone printing, the density is expressed by the size of the area of halftone recording dots within a predetermined small area, so when the image density changes, the shape of the halftone dots changes significantly. In particular, when the halftone dot density is around 50%, recording F' feet (for example, black pixels) or non-recording dots (for example, white pixels) constituting the halftone dots may be connected to each other and become continuous. In such cases, it is often impossible to detect either black dots or white dots.

If you adjust the threshold level for binarizing image information into recorded pixel level and non-recorded pixel level, the halftone density will be 5.
Identification errors in the case of 0% can be reduced. However, in that case, identification errors increase when the halftone density is higher or lower than 50%.

Therefore, at least two types of threshold values are set, and a circuit for detecting recorded dots and a circuit for detecting non-recorded dots refer to the binarized image information with different threshold values, and detect recorded dots. The halftone dot pattern is identified based on both the detection result and the detection result of non-recorded dots.

In the case of a halftone image, the signals read by the image scanner are generally as shown in FIG.

Looking at the dirt, it can be seen that the height of the peaks, the depth of the valleys, and the duty of the signal change depending on the concentration.

Here, when focusing on the signal with a density level of 50%, it can be seen that the height of the peaks and the depth of the valleys of the signal change depending on the position of the image.

When a signal with a concentration of 50% is binarized using a threshold value TH,
In the first part Pa, the peak is TH, the larger valley is TH,
Because it is smaller, in the binarized signal, peaks appear as recorded pixels and valleys appear as non-recorded pixels, and in the latter part pb, both peaks and valleys are larger than TH, so in the disulfide signal, , non-recorded pixels do not appear. That is, when binarizing with TH, it is possible to detect halftone dots (recorded dots) from the array pattern of recorded pixels and non-recorded pixels in the first part Pa, but
No halftone dots can be detected from the latter portion pb.

Furthermore, when this signal is binarized using a threshold value TH2, in the first part Pa, both the peaks and valleys are smaller than TH2, so no recording pixels appear in the binarized signal, and in the later parts In Pb, the peaks are larger than TH2 and the valleys are smaller than TH, so the peaks appear as recording pixels and the valleys appear as non-recording pixels in the binarized signal. Therefore, when binarizing at T Hz, halftone dots cannot be detected from the first part Pa, but halftone dots (non-recorded dots) can be detected from the arrangement pattern of recorded pixels and non-recorded pixels in the latter part pb. obtain.

In other words, if the threshold value TH is used to detect halftone dots made up of recorded dots, and the threshold value TH2 is used to detect halftone dots made up of non-recorded dots, then the density is 50%. Even in a halftone image, halftone dots, either recorded dots or non-recorded dots, are detected. Concentration is 20%
When the density is low, such as TH2, the halftone dots of recorded dots are detected by the threshold value TH, and when the density is high, such as 80%, the halftone dots of non-recorded dots are detected by the threshold value TH2. be done.

[Problem to be solved by the invention]

However, in the above-mentioned conventional technology, after binarization, text, line drawings, etc. with a density near the binarization level tend to have line breaks, which tend to become the core of halftone dots. Furthermore, since multiple threshold levels are provided, the circuit becomes complicated.

Additionally, if there is one or more halftone dots within the matrix area of a predetermined area nXm, the area within the matrix of nXm is considered to be a halftone dot block, but if there is one or more halftone dots within the matrix of nxm For example, a part of a character or dirt on the background is often detected as a single dot and erroneously determined as a halftone area.

Furthermore, for each unit of halftone dot block (if there is one or more halftone dots), 2 x 2
If there are 3 or more halftone dots in the halftone block area, 2×2
The halftone dot block was used as the halftone dot area, but as mentioned above, a part of the text or dirt on the background may be detected as a single dot, and it may be mistakenly judged as a halftone area.
There were things that needed improvement.

It is an object of the present invention to eliminate the above-mentioned drawbacks of the prior art, reduce erroneous detection when detecting halftone dots for parts of characters or dirt on the background, and improve the accuracy of detecting halftone dots into blocks.

[Means to solve the problem]

The above purpose is to provide a means for detecting recorded dots and non-recorded dots that compares a two-dimensional array pattern of input image information with a predetermined recorded dot and non-recorded dot detection pattern and outputs the result, and a means for detecting recorded dots and non-recorded dots that detects a predetermined one-dimensional area. This is achieved by providing halftone pattern identifying means for identifying that the number of pieces of information outputted by the detecting means is plural for each case.

[Effect]

The presence of a plurality of recorded dots and non-recorded dots within a predetermined area is detected, and the detected predetermined area is defined as a halftone block.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 shows the structure of a mechanical section of a type of digital copying machine embodying the present invention. Referring to FIG. 2, this copying machine is comprised of a scanner 1 placed above the apparatus and a printer 2 placed below the apparatus.

26 is a contact glass on which the original is placed. The scanner 1 scans and reads an image of a document placed on a contact glass 26 . The sub-scanning is mechanical, and a carriage provided in the scanner moves in the left-right direction in FIG. 2 by driving the electric motor MT. Reflected light from the original is imaged on a fixed image reading sensor 10 via various mirrors and lenses. The image reading sensor 10 is C
This is a CD line sensor, and in FIG. 2, 5000 reading cells are arranged in a row in the direction perpendicular to the paper surface. In this example, when the copy magnification is 1.0, the resolution is 16 pixels per 1 mm of the original image. Main scanning is electrically performed by a COD shift register provided inside the image reading sensor 10. The main scanning direction is the direction in which the reading cells are arranged, that is, the direction perpendicular to the plane of the paper in FIG.

A signal obtained by reading an original image with a scanner 1 is sent to a printer 2 after being subjected to various processing.

The printer 2 performs binary printing in accordance with the signal.

The printer 2 includes a laser writing unit 25, a photo drum 3, a charger 24, a developing device 12, a transfer charger 14, a separation charger 15, a fixing device 23, and the like. Since this printer 2 has no particular differences from conventionally known general laser printers, only the operation will be briefly described.

The photosensitive drum 3 rotates clockwise in FIG. Then, the surface thereof is uniformly charged to a high potential by the energization of the electrification charger 24. This charged surface is irradiated with laser light modulated by a binary signal corresponding to the image to be recorded. The laser beam repeatedly scans the photosensitive drum 3 in the main scanning direction by mechanical scanning. The electrical potential of the charged surface of the photoreceptor tram 3 changes when it is irradiated with laser light. Therefore, a change in the laser beam, that is, a potential distribution depending on the image to be recorded occurs on the surface of the photosensitive drum 3. This potential distribution is an electrostatic latent image.

When the portion on which the electrostatic latent image is formed passes through the developing device 12, toner is attached depending on the potential thereof, and the electrostatic latent image is developed into a toner image, that is, a visible image. This visible image overlaps the transfer paper fed from the paper feed cassette 4 or 5 to the photosensitive drum 3, and is transferred onto the transfer paper by the bias of the transfer charger 14.

The transfer paper on which the image has been transferred passes through the fixing device 23 and is discharged onto the paper discharge tray 22 .

FIG. 3 shows the configuration of the electric circuit of the digital copying machine shown in FIG. 2. Referring to FIG. 3, the scanner 1 includes an image reading sensor 10, a scanning control section 20, an amplifier 30, an A/D (analog/digital) converter 40, and a halftone processing section 55.2.
It includes a value conversion processing section 65, a region determination section 70, an operation control section 80, an output control section 90, a motor driver MD, and the like.

The scanning control unit 20 performs signal exchange with the printer 2, main scanning control, sub-scanning control, and generation of various timing signals. Various timing signals are generated in synchronization with the scanning timing. Various status signals, print start signals, copy magnification signals, etc. are sent from the printer 2 to the scan control section 20. The scan control unit 20 sends a scan synchronization signal, a status signal, etc. to the printer 2. Motor MT
By driving the scanner 1, the scanner 1 mechanically scans and performs sub-scanning.

The image reading sensor 10 includes a large number of reading cells, a CCD shift register, etc., like a general CCD line sensor. When the scan control section 20 outputs a sub-scanning synchronizing signal, the signals accumulated in a large number of reading cells of the image reading sensor O are transferred to each bit of the CCD shift register at once. Thereafter, the signal of the CCD shift register is shifted in synchronization with the main scanning pulse signal, and the image signal held in the register appears as a serial signal at its output terminal for each pixel (a in Figure 3). (Hereinafter, signals generated from image signals are shown in parentheses).

The amplifier 30 amplifies the image signal (a), removes noise, etc. A/D converter 40 converts the analog image signal into a 6-bit digital signal.

Although not shown in the drawings, the digital signal obtained by the A/D converter 40 is subjected to various conventional image processing such as shading correction, background removal, black and white conversion, etc. It is output as a digital image signal (b) of bits, that is, 64 gradations. This digital image signal (
b) is a median filter 50. The signal is applied to the MTF correction section 60.

The digital image signal (C) processed by the median filter 50 is applied to the halftone processing section 55. The halftone processing unit 55 converts the 6-bit digital image signal (C) into a binary signal (e
).

A circuit that performs halftone processing using the submatrix method is well known, and since no special circuit is used in this embodiment, the specific configuration and operation will be omitted. Note that, in addition to the submatrix method, halftone processing may be performed using a dither method or a density pattern method.

Furthermore, the median filter 50 is necessary because it has the effect of smoothing the image information in the nxm matrix and reducing the moiré of the halftone dot image as described above. Further, the circuit related to the median filter 50 is well known, and since no special circuit is used in this embodiment, the specific configuration and operation will be omitted.

Further, the digital image signal (d) processed by the MTF correction section 60 is applied to a binarization processing section 65 and an area determination section 70. The binarization processing unit 65 compares the MTF-corrected input image signal with a predetermined fixed threshold level and outputs a binary signal (f) according to the magnitude thereof. Therefore, the processing performed here is simple binarization processing, and the signal (f) does not include information on the intermediate density of the original image.

Also, here, the halftone processing section 55 and the binarization processing section 65
The above explanation is based on the assumption that the printer output is binary white/black, but if the printer 2 is a multi-level printer such as a three-level or four-level printer, the halftone processing section 55 is a multi-value dither method, and a binarization processing unit 65 is a multi-value output using simple multi-value conversion with multiple threshold levels. Note that the multi-level dither method, simple multi-level conversion, etc. are not important points in the present invention, and can be implemented using known techniques, so their specific configuration and operation will be omitted.

As will be described later, the area determination unit 70 is a circuit that determines whether or not the original image includes halftone dot information, and outputs a binary signal (g) according to the determination result to the output control unit 90.

The operation control section 80 provides the output control section 90 with a mode signal (i) according to the operation of the mode key on the operation board.

The output control unit 90 outputs a binary image signal ( e) Selectively output the binary image signal (f) or a signal at a predetermined level (white level) output by the binarization processing unit 65.

This signal (a) is given to the printer 2 as a recording signal. The printer 2 modulates the laser beam according to this binary signal and performs recording.

FIG. 1 shows the configuration of the area determination section 70 shown in FIG. 3.

Note that this figure is also a block diagram for detecting a halftone dot area.

The input image data Da in FIG. 1 is the MT in FIG.
This is the same as the correction data (d) from the F correction section 60.

The reason why the MTF correction signal is inputted to the area determination section 70 is because, as shown in FIG. 4, if the input data is unchanged, the halftone dots may not be resolved due to the phase difference between the CCD pitch and the pitch of the halftone dots.

In other words, at a density of 20% in Figure 4, there are halftone dots with a high density and halftone dots with a low density in the input document halftone density, and at a density of 50%, shades of halftone dots appear in the intermediate density area, but here too, there are halftone dots with a high density and halftone dots with a low density. The density ratio of the dots may be large or small, and at a density of 80%, the density of the white core portion of the halftone dot may be light or dark.

As will be described later, in this embodiment, in establishing a criterion for determining whether or not a halftone dot exists, the determination is made based on whether or not the black core or white core of this halftone dot exists. Concentration information is a very important point.

Therefore, the first feature of this embodiment is to perform a predetermined MTF correction on input data.

In other words, as mentioned above, the input halftone dot pitch and CCD10
Assuming that there is not much difference between the core density and peripheral density of the halftone dot caused by the phase difference in the reading pitch, MTF correction is applied, and as shown in the post-MTF data in Figure 4(b),
By widening the density difference between the core density and peripheral density of the halftone dot,
This makes it easier to detect halftone dots, which will be described later, and improves detection accuracy.

FIG. 5 shows an example of MTF correction, in which pixels corresponding to a 3×3 matrix are corrected using weighting coefficients as shown in the figure during main and sub-scanning.

Note that this coefficient is just an example, and other coefficients may be used, and it can be changed depending on the mode magnification or the like.

A block diagram for setting the MTF coefficients shown in FIG. 5 is shown in FIG. In the figure, 61.261C is F
It is an IFO (first-in, first-out) memory, and is used for line delay in the main scanning direction.Since two are used, a two-line delay is realized, and three lines of data, including the current line, can be processed at the same time. Make it exist on the axis. In addition, F/F (flip flop) 61b, 61d, 6
1e and 61f realize a delay in the main scanning direction for each line.

With this configuration, image data corresponding to the coefficients of the matrix shown in FIG. 5 can exist on the same time axis.

That is, the image data corresponding to Ml in FIG. 5 is shown in FIG. 6, and the image data corresponding to M2 is shown in FIG.
The image data corresponding to M3 is shown in FIG. 6C, the image data corresponding to M4 is shown in FIG. 6e, and the image data corresponding to M5 is shown in FIG. 6d.

Also, in the logic circuit 61g, the sum a+b of the data of a and b, and in the logic circuit 861h, the sum d+e of the data of d and e, the logic circuit 86
In 11, the sum of (a + b) and (d + e) (a + b + d + e)
The sum of C and 2C, which is doubled by inputting C and 1 bit shift into the logic circuit 61, is realized, and furthermore, (a
+d+e) is passed through the inverting circuit 61j and the logic circuit 61
Input = (a+b+d+e) in 1 bit shift and (
3Xc by taking the sum of a + b + d + e)/2 and 3Xc
Obtain -(a+b+d+e)/2 (Logic circuit 61.#)
, MTF correction is realized using the coefficients shown in FIG.

This 3xc - (a + a + e) / 2 is M
This becomes the d output of the TF correction section 60 and is input to the area determination section 70.

In the area determining section 70, which will be described later, a density pattern matching method is described based on the density difference between the density of the pixel of interest and the density of surrounding pixels based on the MTF correction signal.
As described in Japanese Patent No. 279665, input image information is binarized using a certain threshold value, and even if the input image information is a signal after binarization, the density of halftone dots can be adjusted as described above by inputting an MTF correction signal. The amplitude is widened, making it easy to detect concentration differences. Also, in binarization, it has the effect of making it easier to output black dots and white dots.

Halftone dot area detection will be described based on FIG.

A detailed explanation of each block will be given later, so an outline will be explained here.

First, in order to determine whether it is a halftone dot or not, it is necessary to have certain areas of image data exist on the same time axis.

Here, an X signal is used to indicate the main scanning direction of the scanner 2, and a Y signal is used to indicate the sub-scanning direction. Therefore, the Y-direction delay circuit 71 and the X-direction delay circuit 7
2 allows certain areas to exist on the same time axis.

Further, the next stage white level detection circuit 73 and black level detection circuit 74 are for detecting the white core or black core of the halftone dot.
In order to determine whether the pixel of interest is the nucleus of a halftone dot, the density difference with surrounding pixels is detected, and if the density difference is above a certain level,
A pattern matching circuit 75 determines whether the halftone dot-like state matches a predetermined pattern and detects the halftone dot.

If there is one or more halftone dots in the determined area of nXm, a halftone block detection circuit (1176) that uses the area of nXm as a halftone block, and if two or more halftone dots exist in the area of nXm, , nXm area as a halftone block+2) 77 is provided, and a block for detecting two or more halftone dots among a plurality of blocks of Saramuko halftone dot blocks, a block for detecting one or more halftone dots, A halftone dot area detection circuit 78 is provided which turns the aforementioned plural halftone dot blocks into a halftone dot area when blocks with no halftone dots exist at a certain rate.

The Y-direction delay circuit 71 will be explained.

The Y-direction delay circuit 71 is connected to the memory 10 as shown in FIG.
1 to 104. Note that this circuit is just an example, and the circuit differs depending on the maximum size of the pattern used for pattern matching.

Further, FIG. 8 shows the timing. The Y-direction delay circuit 71 will be explained below using these.

First, control signals for controlling timing relationships will be explained using FIG. 9. In the figure, A represents the original, and the control signal is a signal F representing the effective original width in the sub-scanning direction (Y direction).
GATE, a signal LGATE representing the effective document width in the main scanning direction (X direction), a signal LSYNC1 for synchronizing reading in the main scanning direction, and a reference signal CLK for the entire system, although not shown in the figure. That is, in the figure, the original information is read line by line in the main scanning direction in synchronization with LSYNC, and becomes valid data when both FGATE and LGATE are "H". The read image data is output pixel by pixel from the CCD10 in synchronization with CLK.

In Fig. 8, after FGATE becomes "H", the image data read in synchronization with SYNC is valid for the first line during the period when LGATE is "H". Image data D, synchronized with CL K as 1
Each pixel is stored in the memory 101. and the next LSY
The second line of image data D2 obtained in synchronization with NC is also stored in the memory 101, but at this time, the first line of image data D1, which was already stored in the memory 101, is synchronized with CLK. Then, one pixel at a time is stored in the memory 102.
It is stored as image data delayed by a line.

After scanning the third line, fourth line, etc., the image data D3. D, ------- is obtained, the memory 10310
4, and when the 5th line is read, the outputs of memories 101 to 104 are as follows: the output of memory 104 is DI, the output of memory 103 is D2, the output of memory 102 is D3, and the output of memory 101 is becomes D4, and together with this and the currently read image data D5 of the fifth line, five lines of image data are obtained at the same time.

Next, the X-direction delay circuit 72 will be explained.

The X-direction delay circuit 72 consists of five blocks as shown in FIG. 10, and each block has five flips.
Flop group (111-115, 116-120.121
~125, 1.26~130131~135). Note that this circuit is just an example, and the circuit differs depending on the maximum size of the pattern used for pattern matching. Each block processes 5 lines of image data Dbl to I)bs obtained by the X-direction delay circuit 71, and performs the same operation, so the image data D
Only the block that processes b+ will be described.

Further, FIG. 11 shows the timing of the operation of the circuit.

The X-direction delay circuit 72 will be explained below using these figures.

In FIG. 11, when the fifth line of image data is read, one pixel at a time is read from the memory 104 in synchronization with CLK.
Image data D1 for the line is output. Then, when the image data D1-1 of the first pixel of the line ■ is input to the flip-flop 111, the flip-flop 11
It is latched to 1 and its value is stored. Then, the second pixel image data D1. ．． If 2 is input, flip
Flop] 11 memorizes the value, but at that time, 1. The image data D1-1 of the first pixel that was omitted is CLK
The data is stored in the flip-flop 112 as data delayed by one pixel in synchronization with .

Below, image data DD+-'- of the 3rd pixel and 4th pixel -
-- is input, flip-flops 113 to 11
5, and when the sixth pixel image data is input, each output of flip-flops 111 to 115 changes so that the output of flip-flop 115 becomes DI-1% flip-flop.
The output of flop 114 is DI-2, the output of flip-flop 113 is DI-3, the output of flip-flop 112 is D4, and the output of flip-flop 111 is DI-.
By combining this with the currently input image data DI-6 of the 6th pixel, image data for 6 pixels in the same line can be obtained at the same time.

Therefore, when the five blocks are combined, as shown in FIG. 12, the image data D is 5 lines x 6 pixels, a total of 300 pixels.
. , ~DC3° are obtained at the same time.

5 lines x 6 pixels from the X direction delay circuit 72, total 300
Pixel image data DCI to DC3° are obtained, and several pixels of these are used for pattern matching to detect halftone dots.

13(a) to (e) are examples of patterns used for pattern matching, and the pixel De15 marked with a circle is the current pixel of interest, and the pixel surrounded by a solid rectangle is The pixels become peripheral pixels.

For example, in the pattern in the same figure (al), the pixel of interest is beam 03., and the surrounding pixels are D cz to D C5+
D C7De12. DC+3. DCIIl, DC
I9. There are 14 pixels DC24, Dczb to Dczq. In pattern matching, the relationship between the pixel of interest and surrounding pixels is: (i) If the density of the pixel of interest is higher than the density of all surrounding pixels by a certain level or more, (11) The intensity of the pixel of interest is higher than that of all surrounding pixels. Of pixels? If the density is lower than the average density by a certain value, it is assumed that matches the pattern, and that square pixel is detected as a halftone dot. Note that the above-mentioned certain concentration is hereinafter referred to as weight.

FIG. 16 shows halftone dots with densities of 20% and 80%, and the density distribution when each halftone dot is viewed one-dimensionally at part A for simplicity. In the case of (1) above, the part (■) in the 16th step, that is, the halftone dot itself, is detected as a halftone dot, and the above (11)
), the part (2) in the 16th square, that is, the part surrounded by the halftone dots, is detected as the halftone dot.

As mentioned above, when the density of a halftone dot is high, that is, the area ratio of black in a certain area is high, there is a white nucleus, and when the density is low, that is, the area ratio of white is high, there is a black nucleus. It is possible. (Left below) Here, we will explain the 14th point in halftone detection.
As shown in the figure, the input data of the halftone image is binarized at multiple threshold levels, and each binarization pattern is
In pattern matching, which detects halftone dots depending on whether or not they are matched with the halftone dot pattern, as shown in Figure 15, text and line drawing information around the binarization threshold level are affected by density unevenness and conveyance unevenness in the image itself. Due to mechanical noise, illumination, and pitch unevenness of the CCD10 mentioned above, the density information of characters and line drawings is not uniform, and the density of the input image becomes uneven, resulting in black discontinuities in the data after binarization. . If this black discontinuity matches the halftone dot pattern, an erroneous detection will occur.

In other words, in this embodiment, the above-mentioned drawback is corrected, and even if some density unevenness occurs, the density difference level is sufficiently small compared to halftone dots. By matching the density difference pattern between the pixel and surrounding pixels, the above drawback can be compensated for and false detections can be reduced.

Further, since this density difference does not change depending on the density (area ratio) of the halftone dots, the configuration of the circuit itself becomes relatively easy.

The white level detection circuit 73 and the black level detection circuit 74 will be described below in the case of the pattern shown in FIG. 13 fal.

In the case (1) above, the black level detection circuit 74 performs the following:
In the case of (+1), the white level detection circuit 73 weights the pixel of interest relative to the surrounding pixels, and determines the magnitude relationship between the weighted pixel of interest (weighted pixel of interest) and the surrounding pixels.

FIG. 17 shows the black level detection circuit 74 when the pattern shown in FIG. 13 fa) is used. The black level detection circuit 74 is
It is composed of a subtracter 161 and comparators 162 to 175. Note that this circuit is just an example, and the configuration may vary depending on the pattern, etc. The subtracter 161 calculates the weight of surrounding pixels of the pixel of interest. In other words, the pixel data of interest I)C
Ob15 and peripheral pixel data (in this case DC2 to DC5,
I) C7, DCI2D C+3. Dell, D
(IQ, D cza, D C211~D C2Q
The signal D e l
”” Obtain D a Ia.

Here, the signal ~D8.4 becomes "H" when (weighted pixel data of interest)>(peripheral pixel data), and becomes "L" otherwise.

Next, FIG. 18 shows the white level detection circuit 73 when the pattern shown in FIG. 13 is used. White level detection circuit 73
is composed of an adder 141 and comparators 142 to 155. Note that this circuit is just an example, and the configuration may vary depending on the pattern, etc. The adder 141 weights the surrounding pixels of the pixel of interest, but the white level detection circuit 73 weights the pixel of interest data D c in contrast to the black level detection circuit 74.
+ Weight data D for s. , 1 is added to generate the weighted pixel data of interest D ((1iv15), and the comparators 142 to 15
Output to 5. Note that this weight data D. , 1 can be set arbitrarily. Similarly to the male level detection circuit 74, the comparators 142 to 155 output signals from 1 to Dd□ depending on the relationship in density between the weighted pixel of interest and surrounding pixels.

get. Here, the signals Ddl to DdIa are "H" when (weighted pixel data) is (peripheral pixel data), contrary to the black level detection circuit 74, and "L" otherwise.
”.

Note that pattern matching may use not only a single pattern but also multiple patterns, in which case a black level detection circuit 7 similar to that shown in FIGS. 17 and 18 corresponding to each pattern may be used.
This can be realized by arranging 4 and the white level detection circuit 73 in parallel, as shown in FIG. 19, for example.

Next, the pattern matching circuit will be explained.

FIG. 20 shows an example of a pattern matching circuit using the pattern shown in FIG. 13(a). The pattern matching circuit 75 is composed of AND gates 181 and 182 and an OR gate 183. Note that this circuit is just an example, and the configuration may vary depending on the pattern, etc. The signals Ddl to Dd+a obtained from the white level detection circuit 73 are as follows:
When (weighted pixel data) <(surrounding pixel data), it becomes "H", and in other cases, it becomes "L". Therefore, when the signals I)at to Dd+4 are input to the AND gate 181, and the signals Da+ to Dd+a are all "H", that is, when the density of the target pixel is lower than a certain weight with respect to all surrounding pixels, Since it matches the pattern, the pixel of interest is determined to be a halftone dot, and the signal D3. ．． is set to “H”. Conversely, when even one of the signals Ddl to Dd+4 is "L", it does not match the pattern, so the pixel of interest is determined to be a non-halftone dot, and the signal D aw is set to "L". Signal I)at~ obtained from the black level detection circuit 74 in the same manner
Input D814 to AND game)-182 and get the signal. ,
When ~De+4 are all "H", the pixel of interest has a density higher than a certain weight with respect to all surrounding pixels, so it matches the pattern. Therefore, the pixel of interest is determined to be a halftone dot, and the signal D□ is set to "H". Conversely, if even one of the signals D8 to D e l 4 is "L", it does not match the pattern, so the pixel of interest is determined to be a non-halftone dot, and the signal Dab is set to "■2". . And the signal D a W + D a b is the OR gate 18
3, and when one of the signals D a W + D a b is "H", that is, when it matches one of the patterns and the pixel of interest is detected as a halftone dot, that pixel is The pixel of interest is finally made into a halftone dot, and the signal is
is set to “H”. Further, when both signals D iW+Dab are "L", the pixel of interest is finally determined to be a non-halftone dot, and the signal Df is set to "L".

When performing pattern matching using a plurality of patterns, for example, as shown in FIG. 19, AND gates corresponding to a plurality of black level detection circuits 74a to 74C and white level detection circuits 732 to 73c are provided. , determine whether the pixel of interest matches a pattern (whether the pixel of interest is a halftone dot or a non-halftone dot), input the output to an OR gate, and determine that at least one pixel of interest in each pattern is a halftone dot. If the pixel of interest is detected to be a halftone dot in any pattern, the pixel of interest is finally determined to be a halftone dot. You can make it happen.

The halftone block detection circuit +1176 and the halftone block detection circuit (2) 77 will be explained.

In the halftone block detection circuit fl) 76 and the halftone block detection circuit (2+77), a block in which one halftone pixel exists in a block consisting of a plurality of pixels (halftone block 1)
, a block with multiple pixels (halftone block 2)
Detect each.

In conventional technology, when creating such a halftone block, if there is even one halftone pixel in the block, the block is treated as a halftone block and the area is divided into regions. As mentioned above, there is a drawback that if even one non-halftone pixel is mistakenly recognized as a halftone pixel due to noise or the like, the entire block is mistakenly recognized as a halftone block.

FIG. 21 shows image data when a halftone dot image with 100 lines and a density of 50% is read at the aforementioned 400 dpi. The hatched areas in the figure are halftone dots, and the numbers 1 to 16 on the top and left side of the image data correspond to each pixel. As is clear from this figure, if a block of an appropriate size, for example 8 x 8 pixels, is used, there are 4 to 5 halftone dots, so there are multiple halftone dots in the block. If such a block exists, the above-mentioned drawbacks can be avoided by making the block a halftone block. However, if halftone pixels are difficult to detect due to moiré, etc., or if there are multiple pixels in a block, if that block is set as a halftone block, the halftone image area will be converted into a non-halftone image. Therefore, in this embodiment, when there is a halftone dot pixel in even one pixel in the middle of the bronc, and when there are multiple halftone dot pixels in the block, the halftone dots are used. Block 1, detected as halftone block 2,
Used for subsequent processing.

FIG. 22 shows the configuration of the halftone block detection circuit (fl) 76 and the halftone block detection circuit 1i@(2177).The halftone block detection circuit (1176 is the main scanning direction halftone block detection circuit (]) 20 ] The sub-scanning direction halftone block detection circuit (11203) detects whether there is a halftone pixel in the main scanning direction of the block, and detects whether there is even one line in which a halftone pixel exists in the sub-scanning direction of the block. , the block is detected as halftone block 1.

The halftone block detection circuit (2177 is a halftone block detection circuit in the main scanning direction). 2) When a predetermined plurality of lines in which halftone dot pixels are present exists, the block is detected as halftone block 2 by the main scanning direction halftone block detection circuit (2) 202. During main scanning, it is detected whether a predetermined plurality of halftone pixels exist or not, and the sub-scanning direction halftone block detection circuit (1) 205 detects whether a predetermined plurality of halftone pixels exist in the sub-scanning direction of the block. If at least one line exists, that block is detected as halftone block 2.If that block is detected as halftone block 2, then that block is detected as halftone block 2. Detected as.

The details of each part will be described below in the case where the block size is 8 pixels in the main scanning direction x 8 lines in the sub-scanning direction, and when there are two or more halftone dot pixels in the block, halftone block 2 is defined.

The main scanning direction halftone block detection circuit fl) 201 will be explained.

As shown in FIG. 23, the main scanning direction halftone block detection circuit fl) 201 includes an octal counter 210, a flip
Flops 211-213, AND gates 214.215
, an OR gate 216, and a NAND gate 217. Note that this circuit is just an example, and the circuit differs depending on the size of the block.

Further, FIG. 25 shows an example of the timing of the operation of this circuit. In addition, the signals marked with ■ to ■ in the figure correspond to the signals marked with ■ in Fig. 23.
Corresponding to each position of ~■. Further, the numbers above CLKO in FIG. 25 correspond to pixels.

The main scanning direction halftone block detection circuit (11201) will be explained below using these figures.

The main scanning direction halftone block detection circuit +11201 detects whether or not a halftone pixel exists among the eight pixels in the main scanning direction of the block. The outputs of Q and -Qc of the octal counter 210 change sequentially as shown in FIG. 25 every time the reference signal CLK is input, so by manually inputting this to the AND gate 214, a flip flop 21
1 output■.

■ becomes "H" or "L" every 8 clocks.

For example, if the second pixel is determined to be a halftone dot and the signal R is "H", the output of the AND gate 215 is
Regardless of the state of Hb, the output of the OR gate 216 is "
This signal is latched at the next rising edge of CLK, and the output of the flip-flop 212 becomes "H".
becomes. Then, by inputting the signals ■ and ■ to the AND gate 215, the output ■ of the AND gate 215 becomes "H", and this signal ■ is inputted to the OR gate 216. Therefore, regardless of the state of the signal Df, ■ is “H”
Therefore, the signal ■ also becomes "H". Then, when the 9th pixel arrives, the signal ■ becomes ``L'', so when the signal I)f is ``L'', the signal ■ becomes ``L'', and this signal is latched at the next rising edge of CLK, and the signal ■ becomes ``L''. becomes “L”. By inputting the signal ■ and CLK to the NAND gate 217,
The output ■ of the NAND gate 217 becomes as shown in FIG. The output ■ of step 3 is “H” when the signal ■ is “H”, that is, when a halftone dot exists in 8 pixels, and conversely, the output ■ is “H” when the signal ■ is “L”, that is, a halftone dot exists in 8 pixels. If not, it becomes “L”.

Below, examples of timing will be shown in which there are two halftone dot pixels among the 8 pixels from the 9th pixel to the 16th pixel, and when there are no halftone dot pixels from the 17th pixel to the 24th pixel.

The main scanning direction halftone block detection circuit f2) 202 will be explained.

Main scanning direction halftone block detection circuit (21202 is the second
As shown in Figure 4, octal counters 220 and 221, flip-flops 222 to 224, and delays 225 and 226
, AND game 1-227.228, OR gate 229,
230 and a NAND gate 231. Note that this circuit is just an example, and the circuit differs depending on the size of the block.

Further, FIG. 26 shows an example of the timing of the operation of this circuit. In addition, the signals from ■ to [phase] in Fig. 26 are the second
This corresponds to each position of ■ to [phase] in Figure 4.

Further, the numbers above CLK in FIG. 26 correspond to pixels.

Below, we will use these figures to create halftone blocks in the main scanning direction (2
) 202 will be explained.

In the main scanning direction halftone block detection circuit f2+ 202,
It is detected whether there are two or more halftone dot pixels among the eight pixels in the main scanning direction of the block. Each output of QA"Qc of the octal counter 220 changes sequentially as shown in FIG. 26 every time the reference signal CLK is input, so by inputting these to the AND gate 227, the The outputs ■ and ■ of 222 are “H” every 8 clocks.
”or ``L''.Here, for example, the 3rd pixel and the 6th pixel
When it is determined that the pixel is a mesh or a halftone dot, and the signal RI is "H", the output of the AND gate 1-228 is When the signal Df is "H", an inverted signal of CLK is output. Then, when this signal ■ is input to the clock of the octal counter 221, when the first signal ■ becomes "H", the Q++ and Qc outputs of the octal counter 22 are both "L", so these two signals OR gate 230
The output ■ of the OR gate 230 obtained by inputting is also “L”
However, when signal ■ becomes “H” for the second time, 8
Since the QIl output of the advance counter 221 becomes "H", the signal (2) becomes "H". Since this signal (2) is latched at the next rising edge of CLK, the output (2) of the flip-flop 223 also becomes "H". After this, the Qll output remains in the "H" state until the octal counter 221 is cleared, so the signal (2) also remains in the "H" state. Then, by inputting the signal ■ and CLK to the NAND gate 231, the output ■ of the NAND gate 231 becomes as shown in FIG. Since signal ■ is latched at , the output of flip-flop 224 [
phase] becomes “H” when the signal ■ is “H”, that is, when there are two or more halftone dot pixels among the eight pixels, and the signal ■ is “H”.
When the octal counter 221 is cleared, the octal counter 221 is cleared by the signal ■. The output of the OR gate 229 is further inputted to the delay 226, and the delayed signal ■ is sent to the octal counter 221. clear terminal (CR
).

Hereinafter, timing examples will be shown in which the 9th pixel to the 16th pixel are the case where one halftone dot pixel exists, and the 17th pixel to the 24th pixel are the case where there is no halftone dot pixel.

The sub-scanning direction halftone block detection circuit (1) (reference numeral 203 or 205; hereinafter referred to as 203) will be explained.

The sub-scanning direction halftone block detection circuit fil 203 includes an octal counter 240 and a memory 24, as shown in FIG.
1, OR gate 242, AND gate 243 and NA
It is composed of an ND gate 244.

Note that this circuit is just an example, and the circuit differs depending on the size of the block.

Further, FIG. 28 shows an example of the timing of the operation of this circuit. It should be noted that the signals ``■'' to ``■'' in FIG. 28 correspond to the signals at the positions ``■'' to ``■'' in FIG. 27. Further, the numbers above 1/8 CLK in FIG. 28 correspond to blocks. Below, using these figures, the sub-scanning direction halftone block detection circuit (t
l203 will be explained.

In the sub-scanning direction halftone block detection circuit (1) 203,
The main scanning direction halftone block detection circuit fl) 20] or the main scanning direction halftone block detection circuit f2+ 202 determines whether there are halftone pixels among the eight main scanning pixels of the block, or whether there are two halftone pixels. After detecting the presence or absence of a halftone pixel, if there is a detection result that a halftone dot pixel is present in even one of the eight sub-scanning lines of the block, the block is detected as halftone block 1,
Further, when there is a detection result that two or more halftone dot pixels exist in one line among the eight lines, that block is detected as halftone block 2.

First, detection of halftone block 1 will be explained.

The octal counter 240 sequentially counts up each time LSYNC is input. And this QA””
By inputting the Q c output to the NAND gate 244, a signal ■ is obtained. First, when the output of the octal counter 240 is 7, each output of QA"-Qc becomes "H", so the signal (2) becomes "L".

Then, the signal ■(-ri,,) of the detection result of the main scanning direction halftone block detection circuit +11203 is now in the 1st block and 4th block.
If there is a halftone pixel in the block and it becomes "H", no matter what state the output (■) of the memory 241 is,
Since the signal ■ is "L", the output ■ of the AND game F243 is "L". Then, the signal ■ and the signal ■ are OR gate 24
2 and obtain the signal ■. Next, the process advances to the next line, and if the output of the counter 240 is 0, the signal ■ becomes "H".

And the signal ■ is now “H” in the 2nd and 4th blocks.
, the output of the memory 241 is equal to the output signal of the OR gate 242 on the previous line by 1, / 8 CL
This is the signal latched at K, and it is 1 at the A word ■ on the previous line.
The signals that were strongly "H" at the 5th and 4th blocks are held. And since the signal ■ is “H”, the signal ■
is the signal that is output as is, and therefore OR
The output ■ from the gate 242 is the 1st, 2.4th block “
The signal becomes "H".

The process proceeds in the same manner, and when the output of the counter is 6, the signal 2 becomes "H". And the traffic light ■ is now 3rd block ahead of 7.
If it becomes “H” for the first time including the line, then the signal ■
Since is "H", the signal ■ is the signal ■ held in the memory 241 that is output as is, and therefore the signal ■
In this case, the 1st to 4th blocks are "H" signals. Then, this signal ■ is latched at 1/8 CLK and becomes the output ■ from the memory 241 for the next line, so that even in one line out of the eight lines in the sub-scanning direction of the block, the signal ■ becomes “H”.
That is, when the detection result indicates that a halftone dot pixel exists in the eight main scanning pixels of a block, it continues to hold it, detects that block as halftone block 1, and outputs an "H" signal.

On the contrary, when all the signals in the 8 lines are "L", that is, when the detection result is that there is no halftone dot pixel, this is held and the block is regarded as a non-halftone block and an "L" signal is output. Then proceed to the next line and counter 240
When the output of becomes 7 again, the signal ■ becomes “L”, so
The output ■ of the memory 241 is no longer held and is cleared.

Regarding the detection of halftone block 2, use the signal 5. The operation is the same as the detection of halftone block 1 by only performing C2.

The sub-scanning direction halftone block detection circuit +21204 will be explained.

Sub-scanning direction halftone block detection circuit (2+ 204 is the second
As shown in FIG. 9, a memory 250, an AND gate block 251, and an R gate 252s are constructed.

Further, the AND gate pro shift 2, 5] is composed of a plurality of AND gates 260 to 287, as shown in FIG. Note that these circuits are merely examples, and other configurations may be used.

Further, FIG. 30 shows the timing of the operation of this circuit up to the output of the memory 250, and FIG. 32 shows an example of the operation from the AND gate block 251 to the output of the OR gate 252.

The sub-scanning direction halftone block detection circuit (2) 204 will be explained below using these figures.

The main scanning direction halftone block detection circuit (1) 201 detects whether or not a halftone pixel exists among the 8 pixels in the main scanning direction of the block, and the signal D9 is stored in the memory 250 (D D
Input to I N l, feed back the output of DOUT+ to DIN□, and so on. If the output of UTZ is fed back to the input of DIN3, the output of DOUT3 is fed back to the manual input of D1□, and so on, the main scanning direction halftone block detection times 1 (1) 20
] First, the first line detection signal D91-1 from D1
81, and then the second line detection signal Dg+-z
When inputting, since the output of DoUt+ is inputted to DIN2, D91-1 is output from the output of DOUT2 with a delay of one line.

Below, the detection signals of the 3rd line, 4th line, -
When 3, D, , -, , - are input sequentially, and the detection signal of the 8th line is input, the output signals D911 to D9Ie of Dou'r and 8 are the output signals of the 1st line to the 8th line. The detection signal D g + -+ ''-D g I-n is obtained, and signals for 8 lines of the block in the sub-scanning direction are obtained.

Next, the signals D9□ to D9.6 are AND gate block 25
1, as shown in FIG. 31, the AND gate pro shift 251 ANDs the inputs of each two signals Dg, . . . -D9□, so as shown in FIG. 32, Signal D9□ is 1. 3. At the 47.11.12th block, the signal D91□ is 23.4. ．． 6, 8, 9,
1. In the 2nd block, if there is a halftone pixel among the 8 pixels in the king scan and it becomes "H", and there is no halftone pixel in the signal +3 to D918 and it is always "L", then the AND gate The output signals DhlI-Dh3s from the block 251 are as follows: signal Dhl, signal D9th, D912, and 3.4.
Both “H” at the 12th block means 3, 4.
This indicates that there are at least two or more halftone dot pixels in the 12 blocks, so 3, 4. ．． The 12th block is detected as halftone block 2 and set to "H".

Other signals cannot be detected as halftone block 2 because there is no flock that is "H" on both lines.
It becomes “L”. and the signal D It l l ~Dh3
When a is input to the OR gate 252, 3 of the signal D51□
．． 4.12th block is “H”, so 3.4, 1.2
Detects the block as halftone block 2 and turns “H”
Output.

Figures 33 to 36 show the results obtained from the circuit described above.
A specific example of a circuit that determines whether it is a halftone dot area based on the DG and DH of a total of six blocks (hereinafter referred to as areas) shown in FIG. 37 based on the dot halftone block information DC12 dot block information NDH FIG. Further, FIGS. 38 and 39 are timing charts showing the operation of the circuit for determining whether the area is a halftone dot area.

The explanation will be given below based on these figures.

In Figures 33 to 36, 300.330 is P
I FORAM (first-in first-out ram), 301, 302 are large-power DF/F, 303
~317, 319~325 are multi-input A, ND elements,
318, 326.327.329.333 is multi-input OR
element, 328 is AND element, 331 is ○R element, 332
is a soft register.

In FIG. 38, from the circuit described above, L G A TE
, 1/]I=GATE, 1/8CLK, IN-DG, I
N-DH (1-point or 2-point halftone block information input to DG and DH in FIG. 33) is input. Upper five signals (LGATE, 1/81=GATE, IN-DC,
IN-DH,1,/8C].

K) IN-DC, lN-1]-1 rATGn
The signal showing the DATHn portion in detail is the 1,000-stage signal. IN-DC is 1 point halftone block information data, 1.23-10.
11. , 12. l 3-n, i.e. DATG
n-1, DATGn-2, 0ATGn-3゜DATGn
-4, -DATGn -10,DATGn-11,DA
Let it be TGn-12, -n. Similarly, IN/DH (two-dot halftone block information data) is DATHn-1, DA, TH.
n-2, DATHn3, DATHn-4,---
DATHn-10゜DATHn-11DATHn-12
, DATHn-13. F I FORAM300
The read/write CLK is 1/8CLK, and the write/reset signal and read/reset signal are 1/8LGA.
He is a TE. In other words, if the data input from the DIN+ terminal is DATGn -1, then the data input from the DIN+ terminal is 1 at the same time.
The value written when the previous 1/8 LGATE became “H”, that is, the data CDATG (n-8>1) from the nth line to the 8th line, is read out in synchronization with 1/8 CLK. Perform sequentially.

Therefore, DG23. DH23, DGl3. A signal with a timing of DHI3 can be obtained. Also DC23, DH23,
DGI 3. DH13 has multiple inputs - F/F 301
With 1/8CLK as the clock, DG22. D.H.
22, DGl2. Obtain a signal with a timing of DH12. Furthermore, DG22. DH22, DGl2. DH12 also has a large force DF/F 302, and DG21. D.H.
21, obtain DGll and DHll. This creates the 1-point and 2-point halftone dot information NDG for each block in the area shown in FIG.

DH is output at the same time and input to the next stage halftone area determination circuit. On the timing shown in FIG.
After LGATE becomes "H", calculation is performed in units of 8 pixels, and when the third DATGn3 and DATHn-3 are input, DG23. From DH23, the third DATG (n 8)-3, DATI ((n8)-3
, DG22. From DH22, 1/8 CL K
DATG (n-8) -2,D of one piece before (the second after 1,/8 L G A T E becomes “H”)
ATH(n-8)-2, DG2], 1/81-G from DH21
The first DATG (n8
) -1, DATH(n-8)-1, DGl3. DH1
From 3 onwards, 1/8 LGA 16th line before the nth line
The third DATG (n-1
6)-3, DATH(n-16)-3, DGl, 2. From DH12, DATG (n-16)=
2. DATH(n-1,6)-2, DGl, 1. D.H.
From ll, DATG (n-16)1, DATH(n-
16) It is understood from the fact that -1 and are obtained respectively.

Figures 34 and 35 show that a certain condition is satisfied based on the 1-point and 2-point halftone dot information DC and DH of each block in the area of Figure 37 obtained at the same time in Figure 33 above. FIG. 3 is a block diagram showing a circuit that determines an area to be a halftone dot area.

The above-mentioned certain conditions are as follows in the area of FIG. 37.

1) When four 2-point halftone dot information DH are "H" and one or more 1-point halftone dot information QDG is "11".

2) When five or more 2-point dot information DH are "H".

And 1. ), 2), the area is set as a halftone dot area. The above conditions are just an example, and DH
, DG can of course be varied depending on the system.

As described above, there are a plurality of halftone detection signals within a halftone block. In other words, the halftone dot area detection unit may detect six halftone blocks as DH3, that is, two-point halftone dots, but moiré occurs in the halftone original due to the phase difference with the reading pitch by the CCD 10. Due to this moiré, a plurality of halftone dots may not be detected even though the halftone dot block is actually a halftone image.

Further, for example, a part of a character or a stain n on the background may be detected as a single dot, and this may be erroneously determined to be a halftone dot area.

Therefore, as mentioned above, if one or more halftone blocks are only detected, the above-mentioned false judgments will occur 2r)), and if two or more halftone blocks are only detected, halftone areas will be detected due to the moiré. become unable.

Therefore, the above-mentioned drawbacks are improved by a combination of one-dot halftone dot and two-dot halftone dot detection blocks, and further by a combination with a block without halftone detection.

The multi-input AND elements 303 to 317 in FIG.
) indicates whether the 2-point dot information of 4 becomes "H" and transmits that information to the next stage circuit.

And Ba1~Baq+ Ba+o =Ba+,
The multi-input OR element 3270 inputs information indicating whether any one becomes "H" to one input of the AND element 328, and the other input receives one-point dot information DGII to DC from the multi-input OR element 318. ],,3. Multi-input OR element 32 determines whether one or more of DC21 to DG23 is “H”.
I'm telling 9. Therefore, the output of the AND element 328 satisfies condition 1).

Next, the multi-input AND elements 320 to 325 select all five combinations from the two-point dot information DHII to DH13, D) (21 to D H2S), and the multi-input OR element 3
26, and informs the multi-input OR element 329 whether even one of them is "H". The multi-input AND element 319 outputs two-point halftone information DHII to DH13, DH2]
~Multi-input OR element 3 determines whether all of DH23 are “H”
Tell 29. The above applies to condition 2).

Therefore, from the multi-input OR element 329, condition 1) or 2 is satisfied.
) is applied, an AMI signal of "H" is output, and otherwise, an AMI signal of "L" is output.

FIG. 36 shows that if the area in FIG. 37 is a halftone area (when the AMI signal is "H"), all the data, 8
FIG. 2 is a block diagram of a circuit whose halftone area is (pixels)×8 (lines). Here, the explanation will be given with reference to the timing chart of FIG. 39.

It is assumed that the image data DAT-IN is as shown in FIG. 39, with 1/8 CLK and 1/8 LGATEXLGATE as standards. Here, DA, Tn-1 is L at the nth line.
Counting from the rising edge of GATE, the first image data is expressed in units of 8 pixels. Furthermore, AMIn is halftone area information detected by the above-mentioned circuit on the nth line, AMI
(n-8) is the (n-8)th line, AMI (n-1
6) is the halftone dot area information for the (n-16)th line, and it is assumed that the signals at the timings shown in FIG. 39 are obtained for each.

F r FORRAM330 uses 1/8 CLK for read/write CLK and 1/8 LGAT for write/reset signal.
E. By setting the read/reset signal to L G A TE, when 1/8 LGATE is "H", the A scale dot area information is written, and when LGATE is "■]", it is written 1 line. The previously written halftone area information is converted to 1/8C.
While synchronizing with LK, read ]+jl\next.

In FIG. 39, AMIn is image data DATn-1
When DAT (n+1.)-3, it is “H” and AMI
(n-8), AMI (n-16> are all “L” within the range of the image data shown in FIG. 39. Dout++ D of P I FORΔM330
From the OUT2 terminal, only the part corresponding to the image data DATn1 is "H", and the rest is "L". O
The R element 331 outputs a signal called OR output, which is transmitted to the shift I/register 332, and further outputs the output of the OR element 331 and the Q, , Q2 of the shift register 332.
OR with the output (1 time latch and 2 time latch), multiple input O
By taking the R element-7333, we obtain the belief B.

This is image data, I) ATn-1, DATn2, DA
Tn-3, DAT (n-8)-1, DAT (n-8
) =2. In the area of DA'r (n-8)-3, only the block of DATn-1 has halftone area information or “H
”, the entire area ↓ This corresponds to the halftone dot area. When the information is set to “H”, the result becomes Q.

For example, in the final stage, FTFOR, A
M, the image data is similarly delayed by the amount of delay caused by multi-input D-F/F, etc., and halftone area information is used as a control signal, for example, image data subjected to character processing and image subjected to halftone processing. By using a selector or the like, data can be separated into characters and halftones. In addition, in the description of the specific embodiment of the present invention, the area shown in FIG. 37 is used as the halftone dot determination area, but the size of the area can be changed depending on the input/output characteristics of the device, the characteristics of the target document, etc. However, it is also possible to easily apply this embodiment based on the present embodiment so as to reduce judgment errors. Furthermore, the conditions for determining the halftone dot area can also be varied for the reasons described above, thereby reducing determination errors.

〔Effect of the invention〕

As explained above, according to the present invention, within a predetermined area,
By detecting the existence of multiple recorded dots and non-recorded dots and using the detected predetermined area as a knitting block, it is possible to (1) prevent false detection when detecting halftone dots for parts of characters or dirt on the background; (2) The accuracy of detecting block formation of halftone dots can be improved by extracting the features due to the regular arrangement of halftone dots.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the entire halftone area detection circuit according to an embodiment of the present invention, FIG. 2 is a schematic configuration diagram of a digital copying machine, FIG. 3 is an electrical configuration diagram of a scanner, and FIG. 4 5 is an explanatory diagram of an example of MTF correction, FIG. 6 is a block diagram showing the circuit configuration of MTF coefficient setting, FIG. 7 is a Y-direction delay circuit diagram, and FIG. 8 is a waveform diagram of input data and corrected data. The diagram is Y
A timing chart of the direction iN extension circuit, FIG. 9 is an explanatory diagram of the control signal that controls the timing relationship, and FIG.
Figure 11 is a timing chart of the X-direction delay circuit, Figure 12 is an explanatory diagram showing image data obtained by the X-direction delay circuit, and Figure 13 shows the pattern used for pattern matching. 14 is a signal waveform diagram of a halftone dot image read by an image scanner, FIG. 15 is an explanatory diagram of a conventional pattern matching method, and FIG. 16 shows halftone dots and their seismic intensity distribution. Explanatory diagram, 1st
Figure 7 is a block diagram of the black level detection circuit, Figure 18 is a block diagram of the white level detection circuit, Figure 19 is a diagram showing an example in which the black level detection circuit and the white level detection circuit are arranged in parallel, and Figure 20 is a block diagram of the white level detection circuit. A block diagram showing an example of a pattern matching circuit, Fig. 21, shows a 1.00 line, 50% density halftone image.
An explanatory diagram showing image data when read at 00 dpi,
FIG. 22 is a block diagram showing an example of a halftone block detection circuit, FIGS. 23 and 24 are block diagrams showing an example of a main scanning direction halftone block detection circuit, and FIG. 25 is a block diagram showing an example of a halftone block detection circuit in the main scanning direction. 26 is a timing chart of the circuit shown in FIG. 24, FIG. 27 is a block diagram showing an example of halftone block detection time 1 (11) in the sub-scanning direction, and FIG. 28 is a timing chart of the circuit shown in FIG. 27. 29 is a block diagram showing an example of the sub-scanning direction halftone block detection circuit (2), FIG. 30 is an operation timing chart of the memory in FIG. 29, and FIG. 31 is a block diagram of the AND gate block detection circuit in FIG. 29. 32 is a timing chart of the circuit shown in FIG. 31, FIG. 33, FIG. 34,
35 and 36 are block diagrams showing an example of a circuit for determining a halftone dot area, FIG. 37 is a diagram showing six blocks (areas), and FIGS. 38 and 39 are block diagrams showing an example of a circuit for determining a halftone dot area. This is a timing chart. 71... Y direction delay circuit, 72... X direction delay circuit, 73... White level detection circuit, 74... Black level detection circuit, 75... Pattern matching circuit, 76...
. . . Halftone block detection circuit (1), 77 . . . Halftone block detection circuit (2), 78 . . . Halftone area detection circuit. Figure Figure (b) 1 bit shift (X2) Figure ct q ~ N Mi1Sl-----cb ~ Figure I-t (:h-z Figure pb Figure 15 Input image (Elephant 2 Concentration BOX of part A after value conversion Fig. 16 ON - Fig. 20 Fig. L-m - Fig. 23 m ■ Fig. 22 Fig. 27,

Claims (1)

[Claims] Recording dot and non-recording dot detection means for comparing a two-dimensional array pattern of input image information with a predetermined recording dot and non-recording dot detection pattern and outputting the result; An image area identification device comprising halftone pattern identification means for identifying that the number of pieces of information outputted by the means is plural.