JPH0443764A - Picture area identification device - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image area identification device applied to digital copying machines, facsimiles, scanners, etc. The present invention relates to an image area identification device that is characterized in that it automatically identifies whether or not it is an image area.

[Conventional technology]

For example, in a digital copying machine, a C0D (charge-coupled device) image sensor or the like is used to read a document image in minute areas, that is, pixel by pixel, and the analog electrical signal obtained from the output of the image sensor is converted into an A/D converter. (
After performing various processing on the resulting digital signal, the signal is sent to a recording device to obtain a copy image.

By the way, in the recording device used for this type of device, each record &iW! Since it is difficult to change the density level for each i element, binary or multi-value recording of recording/non-recording is generally performed. However, since a document may also include halftone images such as photographs, it is necessary to reproduce halftone images. Conventionally, methods such as the dither method, density pattern method, submatrix method, and error diffusion method have been proposed as methods for expressing halftones using a recording device that performs binary or multivalue recording. For example, halftone images can be reproduced.

However, when halftone processing is performed, a relatively favorable copy image can be obtained when the original image density changes gradually, such as in a photograph, but when the original image density changes in a binary manner, such as with text, a relatively favorable copy image can be obtained. In this case, the outline of the copy image becomes blurred, making it difficult to read characters, and dirt on the background of the original appears on the copy image, resulting in a significant drop in copy quality.

For original images such as characters, a preferable copy can be obtained by performing simple binary or multivalue processing without performing halftone processing. Therefore, if a switch is provided to specify whether halftone processing is to be performed or not, a preferred copy mode can be selected based on the operator's judgment depending on the type of document.

However, there are many cases in which intermediate 11iI images such as photographs and binary images such as characters are mixed in one document, such as a pamphlet. In such a case, if the binary or multivalue mode is selected, the quality of the photograph will be degraded, and if the halftone mode is selected, the quality of the text will be degraded.

By the way, there is one more thing about this type of digital copying device.
There are two disadvantages. In other words, when reading an image in small pixel units using a line sensor or the like, if there is periodicity in density changes on the document, interference between the period (pitch) and the array pitch (sampling period) of the image reading sensor causes Moiré may occur on recorded images. For example, when halftone dot printing is performed on a document, the density changes on the image have periodicity, and moiré occurs due to interference between the density change period and the sampling period of the reading sensor.

For example, if the resolution of the image reading sensor is 400 dpi, dot printing with a density close to that resolution, that is, 1
33 lines (approximately 10.5 pixels/mm) ~ 200&l(
(approximately 16 pixels/mm) (7) range (7) % J degrees (7) Moiré occurs in the read signal. Of course, moiré occurs at other densities as well, but at the above-mentioned densities, moiré occurs particularly markedly, and the signal fluctuation range due to it is large.

Halftone printing itself is a kind of pseudo-halftone expression, and the density change in pixel units is a binary value of 110 (recorded/non-recorded). In halftone printing, the average density of the entire pixel set is changed in multiple steps by changing the pitch of the halftone dots and the size of the halftone dots, thereby expressing halftone density. Therefore, unless the moiré problem is taken into consideration, when copying a halftone dot printed original image, it is possible to reproduce the halftone image on the recorded image by binary processing the signal and perform a desirable copy. can. However, in reality, moiré occurs as described above in a document image printed with halftone dots at a specific density, resulting in a significant deterioration in copy quality.

On the other hand, when converting an image reading signal into a binary or multivalued signal through halftone processing, the processing process averages the density of multiple pixels, changes the threshold level, etc., resulting in a copied image. Moiré does not occur or its effect is reduced. In this case, the density of the copied image is represented by halftone dots, but the halftone dots on the copy are not direct reproductions of the halftone dots on the original, but are generated by halftone processing unique to copying machines. It is a point.

Therefore, if the original is a halftone-printed image or an image copied using halftone processing by a digital copying machine, it is better to select a copy mode that performs halftone processing, although it is binary recording in pixel units. is preferred.

Furthermore, as mentioned above, it is sufficient to perform simple binary or multi-value processing for the text area, and halftone processing such as dithering for the halftone area.
A method of performing area division may also be considered. For example, JP-A-6
As shown in Publication No. 3-279665, by detecting halftone dot areas, performing halftone processing on the halftone dot areas, and performing simple binarization on the rest, the text and halftone photographic areas can be output as good images. be able to.

In the halftone dot area detection method disclosed in Japanese Patent Laid-Open No. 63-279665, recorded dots and non-recorded dots are detected by comparing a two-dimensional array pattern of input image information with a predetermined pattern. Based on the result, it is determined whether the input image information is a halftone pattern.

In a halftone-processed image, recorded dots (for example, black pixels) and non-recorded dots (for example, white pixels) are alternately and repeatedly arranged at predetermined pitches and intervals. Therefore, a state in which a recording pixel existing at a certain position and non-recording pixels existing around it are in a predetermined arrangement pattern, or a state in which a non-recording pixel existing at a certain position and a recording pixel existing around it are in a predetermined arrangement pattern. If a state with an arrangement pattern of . In other words, by sequentially moving the pixel of interest and comparing the image information of a two-dimensional area consisting of it and its surrounding pixels for each pixel of interest with a predetermined recorded dot composition pattern and non-recorded dot detection pattern. , can identify whether the input image is a halftone pattern.

However, when an image subjected to halftone dot processing is actually read with an image scanner, the image pattern of the read signal changes greatly depending on the density of the image, often resulting in errors in halftone dot identification. In dot printing, the density is expressed by the size of the area of the halftone recording dots within a predetermined small area, so when the image density changes, the shape of the halftone dots changes significantly. In particular, when the halftone dot density is around 50%, recorded dots (for example, black '#l elements) or non-recorded dots (for example, white pixels) constituting the halftone dots may be connected to each other and become continuous. In such cases, it is often impossible to detect either black dots or white dots.

If you adjust the threshold level for binarizing image information into recorded pixel level and non-recorded pixel level, the halftone density will be 5.
Identification errors in the case of 0% can be reduced. However, in that case, identification errors increase when the halftone density is higher or lower than 50%.

Therefore, at least two types of threshold values are set, and a circuit for detecting recorded dots and a circuit for detecting non-recorded dots refer to the binarized image information with different threshold values, and detect recorded dots. The halftone dot pattern is identified based on both the detection result and the detection result of non-recorded dots.

In the case of a halftone image, the signals read by the image scanner are generally as shown in FIG.

Looking at this, it can be seen that the height of the peaks, the depth of the valleys, and the duty of the signal change depending on the concentration.

Here, when focusing on the signal with a density level of 50%, it can be seen that the height of the peaks and the depth of the valleys of the signal change depending on the position of the image.

When a signal with a concentration of 50% is binarized using the threshold value T H+ , in the first part Pa, the peak is TH and the larger valley is T
Since it is smaller than H, in the binarized signal, peaks appear as recorded pixels and valleys appear as non-recorded pixels, and in the latter part pb,
Both mountains and valleys are TH.

Therefore, non-recorded pixels do not appear in the binarized signal. In other words, when binarized with T H+, in the first part Pa, halftone dots (recorded pixels) are dots) can be detected, but halftone dots cannot be detected from the later portion pb.

Moreover, when this signal is binarized with a threshold value T Ht,
In the first part Pa, both the peaks and valleys are TH! In the latter part pb, the peak is greater than T Ht and the valley is smaller than T H+, so the peak appears as a recording pixel in the binarized signal. , valleys appear as non-recorded pixels. Therefore, when binarized at T Hz, halftone dots cannot be detected from the first part pa, but
In the latter portion Pb, halftone dots (non-recorded dots) can be detected from the arrangement pattern of recorded pixels and non-recorded pixels.

In other words, if the threshold value TH is used to detect halftone dots made of recorded dots, and the threshold value THt is used to detect halftone dots made of non-recorded dots, the density will be 50%. Even in a halftone image, either a recorded dot or a non-recorded dot is detected. concentration is 20
When the density is low, such as 80%, the halftone dots of recorded dots are detected by the threshold value TH, and when the density is high, such as 80%, the halftone dots of non-recorded dots are detected by the threshold value TH. is detected.

[Problem to be solved by the invention]

However, the above-mentioned prior art does not describe a halftone dot detection method that can be used when changing the magnification.

In other words, the shape of the halftone dot pattern usually changes when the magnification is changed, and the prepared pattern cannot handle it.
The halftone dot detection rate when the magnification is changed is significantly different from the halftone dot detection rate when the magnification is the same, and the image when the magnification is changed has many false detections, resulting in significant image deterioration. Conventionally, measures such as increasing the number of halftone detection patterns have been taken in order to solve these drawbacks, but this has the problem of increasing the number of circuit components.

It is an object of the present invention to eliminate the drawbacks of the above-mentioned conventional techniques, improve the detection rate of halftone dot areas, and reduce erroneous detection outside the halftone dot areas.

[Failure to solve the problem]

The above purpose is to provide an image reading means that divides the original image into a large number of minute pixel areas, reads the density thereof, and outputs an electric signal according to the density, and scans and drives the original and this image reading means relative to each other. and a first sub-scanning magnification means for changing the image magnification in the sub-scanning direction of the image by adjusting the scanning speed according to a specified image magnification ratio, and converting the analog signal outputted by the image reading means into a digital signal. a converting means for converting the image into a digital signal; and a main scanning scaling means for changing the image scaling factor by thinning or interpolating the image of the digital signal output by the converting means in the main scanning direction according to a specified image scaling factor; Recorded dot and non-recorded dot detection means that compares the two-dimensional array pattern of the digital signal with a predetermined recorded and non-recorded dot detection pattern and outputs the result;
This is achieved by a first means including a second sub-scanning magnification means that thins out or interpolates the image information scaled by the first sub-scanning magnification means in accordance with a specified magnification ratio.

The above object also includes an image reading means that divides the original image into a large number of minute pixel areas, reads the density thereof, and outputs an electric signal according to the density; and a relative scanning drive between the original and the image reading means. and a sub-scanning magnification means for changing the image magnification in the sub-scanning direction of the image by adjusting the scanning speed according to a specified image magnification, and converting the analog signal outputted by the image reading means into a digital signal. a conversion means for
a main scanning magnification means for changing the image magnification by thinning out or interpolating the image of the digital signal output by the conversion means in the main scanning direction according to a specified image magnification; and a two-dimensional array pattern of the digital signals. This can also be achieved by a second means comprising recorded dot and non-recorded dot detection means for comparing the detected dots with a predetermined recorded dot and non-recorded dot detection pattern and outputting the results.

[Effect]

According to the first and second means, the image reading means, the sub-scanning magnification changing means (the first sub-scanning magnification changing means), the main scanning magnification changing means, the converting means, and the detecting means are provided, and an arbitrary magnification ratio can be obtained. The image information scaled in the sub-scanning direction is re-scaled back to the same size image information by having a sub-scanning scaling means for identifying the halftone dot area, and the halftone dot research area is then resized in the two-dimensional image area. Compare using identification patterns,
Output the result.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 shows the structure of a mechanical section of one type of digital copying machine that embodies the present invention. Referring to FIG. 2, this copying machine has a scanner 1 placed above the device and a scanner 1 placed below the device. The printer 2 is made up of two printers.

26 is a contact glass on which the original is placed. The scanner 1 scans and reads an image of a document placed on a contact glass 26 . The sub-scanning is mechanical, and a carriage provided in the scanner moves in the left-right direction in FIG. 2 by driving the electric motor MT. Reflected light from the original is imaged on a fixed image reading sensor 10 via various mirrors and lenses. The image reading sensor 10 is C
This is a CD line sensor, and in FIG. 2, 5000 reading cells are arranged in a row in the direction perpendicular to the paper surface. In this example, when the copy magnification is 1.0, the resolution is 16 ifi elements per 1 mm of the original image. The main scan is
This is electrically performed by a CCD shift register provided inside the image reading sensor 10. The main scanning direction is the direction in which the reading cells are arranged, that is, the direction perpendicular to the plane of the paper in FIG.

A signal obtained by reading an original image with a scanner 1 is sent to a printer 2 after being subjected to various processing.

The printer 2 performs binary printing in accordance with the signal.

The printer 2 includes a laser writing unit 25, a photosensitive drum 3, a charger 24, a developing device 12, a transfer charger 14, a separation charger 15, a fixing device 23, and the like. Since this printer 2 has no particular differences from conventionally known general laser printers, only the operation will be briefly described.

The photosensitive drum 3 rotates clockwise in FIG. Then, the surface thereof is uniformly charged to a high potential by the energization of the electrification charger 24. This charged surface is irradiated with laser light modulated by a binary signal corresponding to the image to be recorded. The laser beam repeatedly scans the photosensitive drum 3 in the main scanning direction by mechanical scanning. The electrical potential of the charged surface of the photosensitive drum 3 changes when it is irradiated with laser light. Therefore, a change in the laser beam, that is, a potential distribution depending on the image to be recorded is generated on the surface of the photosensitive drum 3. This potential distribution is an electrostatic latent image.

When the portion on which the electrostatic latent image is formed passes through the developing device 12, toner is attached depending on the potential thereof, and the electrostatic latent image is developed into a toner image, that is, a visible image. This visible image overlaps the transfer paper fed from the paper feed cassette 4 or 5 to the photosensitive drum 3, and is transferred onto the transfer paper by the bias of the transfer charger 14.

The transfer paper on which the image has been transferred passes through the fixing device 23 and is discharged onto the paper discharge tray 22 .

FIG. 3 shows the configuration of the electric circuit of the digital copying machine shown in FIG. 2. Referring to FIG. 3, the scanner l includes an image reading sensor 10, a scanning control section 20, an amplifier 30, an A/D (analog/digital) converter 40, and a halftone processing section 55.2.
It includes a value processing section 65, an area determination section 70, an operation control section 80, an output control section 9o, a motor driver MD, and the like.

The scan control unit 20 exchanges signals with the printer 2, performs main scanning control, sub-scanning control, and generates various timing signals.The various timing signals are generated in synchronization with the scanning timing. Various status signals, print start signals, copy magnification signals, etc. are sent from the printer 2 to the scan control section 2o. The scan control unit 20 sends a scan synchronization signal, a status signal, etc. to the printer 2. By driving the motor MT, the scanner 1 mechanically scans and performs sub-scanning.

The image reading sensor 10 includes a large number of reading cells, a CCD shift register, etc., like the CCD line sensor -a. When the scan control section 20 outputs the sub-scanning synchronization signal, the signals accumulated in a large number of reading cells of the image reading sensor 1o are transferred to each bit of the CCD shift register at once. Thereafter, the signal of the CCD shift register is shifted in synchronization with the main scanning pulse signal, and the image signal held in the register appears as a serial signal at its output terminal one pixel at a time (a in Figure 3). (Hereinafter, signals generated from image signals are shown in parentheses).

The amplifier 30 amplifies the image signal (a), removes noise, etc. A/D converter 40 converts the analog image signal into a 6-bit digital signal.

Although not shown in the drawings, the digital signal obtained by the A/D converter 40 is subjected to various conventional image processing such as shading correction, background removal, black and white conversion, etc. It is output as a digital image signal (b) of bits, that is, 64 gradations. This digital image signal (
b) is applied to the median filter 50 and the MTF correction section 60.

The digital image signal (c) processed by the median filter 50 is applied to the halftone processing section 55. The halftone processing unit 55 converts the 6-bit digital image signal (C) into a binary signal (e
).

A circuit that performs halftone processing using the submatrix method is well known, and since no special circuit is used in this embodiment, the specific configuration and operation will be omitted. Note that, in addition to the submatrix method, halftone processing may be performed using a dither method or a density pattern method.

Furthermore, the median filter 50 is necessary because it has the effect of smoothing the image information in the nxm matrix and reducing the moiré of the halftone dot image as described above. Further, the circuit related to the median filter 50 is well known, and since no special circuit is used in this embodiment, the specific configuration and operation will be omitted.

Further, the digital image signal (d) processed by the MTF correction unit 60 is applied to a main scanning scaling processing unit 66 and a sub-scanning scaling processing unit 67, and then passes through the sub-scanning scaling processing unit 67 to an area determination unit. 70.

The binarization processing unit 65 compares the MTF-corrected input image signal with a predetermined fixed threshold level and outputs a value signal (f) according to the magnitude thereof. Therefore, the processing performed here is simple binarization processing, and the signal (f) does not include information on the intermediate density of the original image.

Also, here, the halftone processing section 55 and the binarization processing section 65
The above explanation is based on the assumption that the printer output is binary white/black, but if the printer 2 is a multi-level printer such as a three-level or four-level printer, the halftone processing section 55 is a multi-value dither method, and a binarization processing unit 65 is a multi-value output using simple multi-value conversion with multiple threshold levels. Note that the multi-level dither method, simple multi-level conversion, etc. are not important points in the present invention, and can be implemented using known techniques, so their specific configuration and operation will be omitted.

As will be described later, the area determination section 70 is a circuit that determines whether or not the original image includes halftone dot information, and sends a binary signal (g) according to the determination result to the main scanning magnification processing section 66. Output.

FIG. 40 shows a block diagram of main scanning magnification processing.

Note that this is just an example and other methods may be used.
In the scaling processing method shown in Figure 0, the toggle RAM 32
Address counters 321a, 321b of 0a, 320b
The clock is generated by the magnification data ROMs 322a and 322b.

This is because data corresponding to the magnification is stored in the internal memory of the ROM or RAM. For example, in the case of the same magnification, the address and data of the RAM 320a, 320b are 1:1, that is, in the case of the same magnification, the address counter 321a ,3
For the clock 21b, input the write clock when writing to RAM, input the clock for reading (picture frequency) when reading RAM, and use it as the RAM address.The input data will be output as is in correspondence with the picture frequency. , the input and output image frequencies are converted, and the data becomes the same size. This is the case of the timing chart (XI) shown in FIG.

Furthermore, the image frequency of the write clock is thinned out during writing depending on the relationship between the address and data of the RAMs 320a and 320b. For example, if the CLK is thinned out like the CLK at (X O, 5) in FIG.
The data at that time corresponds to the write clock, so in the case of (X 0.5), as the address increases by +1, the data advances up to 2, so the address 1
data is 1 for address 2, data is 3 for address 2, and R
The AM 320a and 320b are in a state where data is thinned out. When reading the data stored in this RAM, if the read clock is used as the address counter clock, the output data is the image frequency of the read clock, multiplied by 0.5. This is (X
This is the case of o.5).

When writing, the write clock is input as the address counter clock and the data is taken into the RAM, and when reading, the image frequency of the read clock is thinned out based on the relationship between the addresses and data of the RAMs 320a and 320b. For example, the fourth
If CLK is thinned out like (x2) CLK in the timing chart in Figure 1, when reading, the RAM address counter will be a clock that is thinned out from the read clock, and the data at that time will correspond to the read clock. Therefore, in the case of (x2), two pieces of data will be output to the read clock while the address increases by +1, and the same data will be added one piece at a time, resulting in twice the data. becomes.

That is, when reducing, the write clock is thinned out, when reading, the read clock is output, when expanding, the clock is thinned out, and when writing, the write clock is used as input.

Further, in the above system, switching of the clock during write/read is performed by the toggle RAM 320a.

320b write/read, magnification data RO
Switch to and input the counter clock of the loop counter of M. The magnification data ROMs 322a and 322b store magnification data corresponding to the addresses.

FIG. 42 shows the data stored in this magnification ROM. In the case of ×1, all are H, and the gate 326a in FIG.
, 326b, the same clock as the clock is input to the address counter 321a. In the case of ×0.5, H and L alternate, that is, 100
50 out of these become H, and by AND with gates 326a and 326b, the address clock becomes half of the original clock.

Further, in the case of x2, 100 out of 200 become H, and the address clock becomes half of the original clock by AND with gates 326a and 326b. In the case of ×0°5 and ×0.2, switching of ROM data is performed in RAM320a, 32
Synchronizes with write/read switching of 0b.

In addition, the selectors 323a and 323b switch the upper addresses of the magnification data ROMs 322a and 322b,
Switches ROM data during read/write.

The initial data is set to output ROM data such that the clock to the address counters 321a and 321b is the same as the original clock, that is, all H data.

As you can see above, when reducing, reduced data/100=
A reduction clock is used, and when enlarged, the enlargement data/100 is used as an enlargement clock, so that it also corresponds to reduction and enlargement in 1% increments.

Note that 324a and 324b are loop counter control units;
25a and 325b are latch parts, 327 is a 3-state buffer, which switches the input data of the RAMs 320a and 320b, and 328 switches the output data of the RAMs 320a and 320b.

FIG. 43 is an explanatory diagram of the loop counter control units 324a and 324b of the magnification data ROMs 322a and 322b.

The data selector 330 determines whether the magnification data is 100 or more or 1
Magnification data and initial data (here, 100) are selected using a control signal that is less than 00.

If this is less than 100, that is, when shrinking, the RAM3
Address counters 321a, 321 of 20a, 320b
Since the amount of sampled redata at the time of reduction is determined by how many counts the clock of b is with respect to the clock of the counter 331, the initial value data is selected (in this case, it will be 100 loop counter), and the number of times the clock of the counter 331 is , if we do the same as when reducing, the loop counter 331 will be 100/enlarged data amount, which will cause an error, so the enlarged data amount will always be 100, and if we take l loop enlarged data amount, then the enlarged data amount/10
0, and the RAM 320a, 3 that matches the exact magnification
It becomes a clock for address counters 321a and 321b of 20b.

In the above explanation, in order to configure a loop counter of 100 loop counter 331 during reduction and an expanded data amount loop counter during enlargement, the value of counter 331 and the value of selector 330 are compared by comparator 332, and the counter value is larger than the selector value. If there is a large amount, the clear signal of the counter 331 is sent to the comparator 3.
It is output from 32 and used as a loop count. The output data of this counter 331 is connected to the lower addresses of the ROMs 322a and 322b.

The operation control section 80 provides the output control section 90 with a mode signal (i) according to the operation of the mode key on the operation board.

The output control unit 90 outputs a binary image signal ( e) Selectively output the binary image signal (f) or a signal at a predetermined level (white level) output by the binarization processing unit 65.

This signal (a) is given to the printer 2 as a recording signal. The printer 2 modulates the laser beam according to this binary signal and performs recording.

FIG. 1 shows the configuration of the area determination section 70 shown in FIG.
Note that this figure is also a block diagram for detecting a halftone dot area.

The input image data Da in FIG. 1 is the MT in FIG.
This is the same as the correction data (d) from the F correction section 60.

The reason why the MTF correction signal is inputted to the area determination section 70 is because, as shown in FIG. 4, if the input data is unchanged, the halftone dots may not be resolved due to the phase difference between the CCD pitch and the pitch of the halftone dots.

In other words, at a density of 20% in Figure 4, there are halftone dots with a high density and halftone dots with a low density in the input document halftone density, and at a density of 50%, shades of halftone dots appear in the intermediate density area, but here too, there are halftone dots with a high density and halftone dots with a low density. The density ratio of the dots may be large or small, and at a density of 80%, the density of the white core portion of the halftone dot may be light or dark.

As will be described later, in this embodiment, in establishing a criterion for determining whether or not a halftone dot exists, the determination is made based on whether or not the black core or white core of this halftone dot exists. Concentration information is a very important point.

Therefore, the first feature of this embodiment is to perform a predetermined MTF correction on input data.

In other words, as mentioned above, the input halftone pitch and C0DIO
Assuming that there is not much difference between the core density and peripheral density of the halftone dot caused by the phase difference in the reading pitch, MTF correction is applied, and as shown in the post-MTF data in Figure 4(b),
By widening the density difference between the core density and peripheral density of the halftone dot,
This makes it easier to detect halftone dots, which will be described later, and improves detection accuracy.

FIG. 5 shows an example of MTF correction, in which pixels corresponding in a 3×3 matrix are corrected using weighting coefficients as shown in the figure during main and sub-scanning.

Note that this coefficient is just an example, and other coefficients may be used, and it can be changed depending on the mode magnification or the like.

6ia shows a block diagram for setting the MTF coefficient shown in FIG. 5 in FIG.

61c is a FIFO (first-in, first-out) memory for one line delay in the main scanning direction, and since two are used, two lines of delay can be realized.
Together with the current line, three lines of data are made to exist on the same time axis. Also, F/F (flip flop) 61b
, 61d, 61e, and 61f realize a delay in the main scanning direction for each line.

With this configuration, image data corresponding to the coefficients of the matrix shown in FIG. 5 can exist on the same time axis.

That is, the image data corresponding to Ml in FIG. 5 is shown in FIG. 6, the image data corresponding to M2 is shown in FIG.
The image data corresponding to M3 is shown in FIG. 6C, the image data corresponding to M4 is shown in FIG. 6e, and the image data corresponding to M5 is shown in FIG. 6d.

Also, in the logic circuit 61g, the sum of data a and b is a+b, and in the logic circuit 61h, the sum of data d and e is d+eX logic times! 6
1i realizes the sum (a + d + e) of (a + b) and (d + e), and realizes the sum 3Xc of C and 2C, which is doubled by shifting 1 bit and inputting it to the logic circuit 61, moreover,
(a + b + d + e) is passed through the inverting circuit 61j, and -(a ten su ten d + e) is inputted by 1 bit to the logic circuit 61, and the sum of -(a + b + d + e) / 'l and 3 x C is obtained. By taking 3xc-(a+d+e)/
2 (logic circuit 611), and M according to the coefficients in FIG.
This realizes TF correction. This 3Xc-(a+b10d
+e)/2 becomes the d output of the MTF correction section 60 in FIG. 3, and is input to the area determination section 70.

In the area determination unit 70, which will be described later, a density pattern matching method is described based on the density difference between the density of the target Wi area and the density of surrounding pixels based on the MTF correction signal d, but this method is disclosed in Japanese Patent Laid-Open No. 63
As in Publication No. 279665, input image information is binarized with a certain threshold value, and even if the input image information is a signal after binarization, by inputting an MTF correction signal, halftone dots can be adjusted as described above. The concentration amplitude is widened, making it easy to detect concentration differences. Also, in terms of disulfidation, it has the effect of making it easier to output black dots and white dots.

Halftone dot area detection will be described based on FIG.

A detailed explanation of each block will be given later, so an outline will be explained here.

First, in order to determine whether it is a halftone dot or not, we make certain areas of image data exist on the same time axis, and if the image data is scaled in the sub-scanning direction by the scanning speed of the motor at a certain arbitrary scaling ratio, then , here, reverse scaling is performed and the image data is corrected to the same size.

First, in order to determine whether it is a halftone dot or not, it is necessary to have certain areas of image data exist on the same time axis.

Here, an X signal is used to indicate the main scanning direction of the scanner 2, and a Y signal is used to indicate the sub-scanning direction. Therefore, the Y-direction delay circuit 71 and the X-direction delay circuit 7
2, a certain area is made to exist on the same time axis, and if the area has been scaled, inverse scaling is performed to obtain image data of the same size.

Further, the next stage white level detection circuit 73 and black level detection circuit 74 are for detecting the white core or black core of the halftone dot.
In order to determine whether the pixel of interest is the nucleus of a halftone dot, the density difference with surrounding pixels is detected, and if there is a certain density difference,
A halftone dot is detected by determining whether the state of the halftone dot nucleus matches a predetermined pattern in a pattern matching circuit 75.

If one or more halftone dots exist in the determined nxm area, a halftone block detection circuit (1) 76 that uses the nxm area as a halftone block, and two or more halftone dots exist in the nxm area. In this case, a halftone block detection circuit (2) 77 is provided which uses the nxm area as a halftone block, and a halftone block detection circuit (2) 77 for detecting two or more halftone dots and one or more halftone dot detection circuit among the plurality of halftone blocks is provided. A halftone dot area detection circuit 7B is provided which makes the aforementioned plural halftone dot blocks into a halftone dot area when blocks without halftone dots exist at a certain rate.

In addition, the effect of not inputting data after main and sub-scanning scaling to the area determination unit 70, but instead inputting image data that has undergone inverse scaling correction to the same size will be described below.

An example of a halftone detection pattern corresponding to the magnification shown in FIG. 44 is shown. (al is the halftone detection pattern at the same magnification, (b) 4
The halftone dot detection pattern is X 0.5 L only in the sub-scanning direction (C1 is a ×2 one).

For example, when a magnification ratio of ×0.5 is set like in this device, the document image is first read at twice the scanning speed at the same magnification as described above, and then the magnification ratio is ×2. Then the speed will be 1/2. Therefore, even if the same halftone dot is read, if the magnification ratio is different, the shape of the halftone dot detection pattern will also change in the sub-scanning direction.

When inverse magnification correction is performed in the sub-scanning direction on the area where pattern matching is performed using the halftone detection pattern as in the present invention,
By having the halftone detection pattern shown in +8+, (b)
(C) is completely unnecessary. Furthermore, there are currently many systems in which the magnification can be set in 1% increments, and if accurate halftone dot detection is to be performed, the number of halftone dot detection patterns will be enormous for the reasons mentioned above. On the other hand, reducing the circuit scale and reducing the number of halftone detection patterns directly leads to false detection. Therefore, by using the present invention, accuracy and circuit scale can be simplified.

Next, the sub-scanning scaling circuit 67 and the Y-direction delay circuit 71 will be explained.

As shown in FIG.
105 and 106, AND elements 107 and 108, and a selector 109.

Note that this circuit is one example, and the circuit differs depending on the maximum size of the pattern used for pattern matching.

Furthermore, various sub-scanning magnification methods can be considered, including already known methods.

The timing is shown in FIG. 8, and the Y-direction delay circuit 71 will be explained below using these timings.

First, we will explain the control signals that control the timing relationship using FIG.
GATE, a signal LGATE representing the effective document width in the main scanning direction (X direction), a signal LSYNC2 for synchronizing reading in the main scanning direction, and a reference signal CLK for the entire system, although not shown in the figure. That is, in the figure, the original information is read line by line in the main scanning direction in synchronization with LSYNC, and becomes valid data when both FGATE and LGATE are "H". The read image data is output pixel by pixel from the CCD10 in synchronization with CLK.

In FIG. 8, after FGATE becomes “H”, the image data read in synchronization with the first LSYNC is
IWi synchronizes with CLK by using the period when GATE is "H" as the first line's effective image data D +-+ ~ DI-a.
Each element is stored in the memory 101. And the next LSYN
Second line image data Dg-+ obtained in synchronization with C
~D! -Oh, it is still stored in the memory 101, but
At this time, the first line of image data D1-3 to D1-7 that was already stored in the memory 101 is stored pixel by pixel in the memory 102 as image data delayed by one line in synchronization with CLK. .

When the image data is obtained by scanning the 3rd line, 4th line---m=-, it is delayed in the memories 103 and 104, and when the 5th line is read, the memory 101-1
Each output of memory 104 is Dl-I-Dl.
-1l, the output of memory 103 is Dl-1~D! -7, the output of memory 102 is D3-1 to D3-r+, memory 1
The output of 01 is -1 to D4-n, and by combining this with the currently read image data of the 5th line Ds- to D, -7, five lines of image data are obtained at the same time.

This is the operation when the magnification ratio is equal to the same magnification. In other words, when variable magnification (same magnification) data is input to ROM105.106, R
OMIO3 outputs sub-scanning amount subtraction data corresponding to the magnification, and is ANDed with LGATE. This A
The output of the ND element 107 becomes a write reset signal and a read reset signal for the memories 101 to 104. Also ROM10
6 outputs a selection signal SEL that controls the final output D1 to Db% of this circuit.When the magnification is 0, inverse scaling is not necessary, and the ROMIO5 (7) output is "H" and the output from ROM106 is 'L'. (SEL signal) is output, the write reset and read reset signals of the memories 101 to 104 become LGATE, and the image data is sequentially delayed.
α1 beam, -1 to DS-, α2 is D4-1 to D4□,
α3 is Dl-I-D, -1l, α4 is D4-I~Da-
Fl, α, beam, -1 to D, -7 are A of selector 109
It becomes a series input, the SEL signal becomes °L'', and the A series input is output.

Next, junior Wl! The case where the variable magnification is set to x2 will be described. The scanning speed is 1×2, which is the same speed as when magnified, and the image data in the sub-scanning direction is doubled. Therefore, this circuit performs inverse scaling < x O, 5) to obtain image data of the same size. The operation is such that when the variable magnification data (x2) is input, the ROM 105 outputs a thinning signal, and the AND element 1
07, performs an AND with LGATE and outputs the WR signal (
Outputs write reset and read reset signals). As shown in FIG. 8, the memories 101 to 104 write data by skipping one line, such as the first line, the third line, and the fifth line. Therefore, I-line thinned data Dbl to I)bs is output and is inversely scaled to equal-size image data. Therefore, the thinning signal output from the ROM 105 enables reverse scaling by thinning out various sub-scanning lines. Conversely, when the magnification ratio is set to x0.5 in this apparatus, the scanning speed becomes twice as fast as when the image is at the same magnification, and the image data is reduced in the sub-scanning direction. Therefore, in this circuit, it is sufficient to perform sub-scanning magnification of ×2.

The operation will be explained below. ROMIO3 outputs “H” when the variable magnification data (xo, 5) is input,
AND element 107 performs an AND operation with LGATE and outputs the same <LGATE, which becomes the WR signal.

Also, the ROM106 outputs “H” and the same < LGAT
E, and the selector 109 outputs the B-series input. Here, the B series input of the selector 109 is α5×
2, α4×2, α3×1, and data Db and -D are obtained in the timing chart of FIG. Inverse scaling of ×2 is performed by outputting the same data twice.

When enlarging by inverse scaling, various types of sub-scanning scaling can be performed by changing the combination of data output by the memories 101 to 104 and outputting the same data redundantly.

As mentioned above, when performing sub-scanning magnification and Y-direction delay,
Although the present invention has been described based on one embodiment, various methods including known techniques may be used.

Also, when performing this type of pattern matching, it is not necessary to perform very strict reverse magnification in the sub-scanning direction, for example, 100% and 10%.
There is no need for inverse scaling such as 1%, but it can be approximated in 1θ% increments, or several patterns after sub-scanning scaling may be prepared, and the steps for performing sub-scanning inverse scaling may be coarsened, and the sub-scanning scaling circuit By using the present invention, it is possible to easily apply the present invention to simplify the configuration of the system. Note that while the conventional sub-scanning magnification circuit has a large-scale storage means such as a frame memory, the sub-scanning magnification circuit 67 used in this embodiment has
Because it does not require large-scale storage means as mentioned above,
The sub-scanning variable magnification method alone is also very useful.

Next, the X-direction delay circuit 72 will be explained.

The X-direction delay circuit 72 consists of five blocks as shown in FIG. 10, and each block has five flips.
Flop group (111-115, 116-120, 121
~125,126~130°131~135). Note that this circuit is just an example, and the circuit differs depending on the maximum size of the pattern used for pattern matching. Each block processes 5 lines of image data D,,%D,, obtained by the Y-direction delay circuit 71, and performs the same operation, so the image data D1
We will only explain the blocks that process.

Further, FIG. 11 shows the timing of the operation of the circuit.

The X-direction delay circuit 72 will be explained below using these figures.

In FIG. 11, when the fifth line of image data is read, one pixel at a time is read from the memory 104 in synchronization with CLK.
The image data D for the line is output. Then, when the image data D1-1 of the first pixel of the first line is input to the flip-flop 111, the flip-flop 11
It is latched to 1 and its value is stored. Then, when the second pixel image data D I-t is input, the flip-flop 111 stores that value, but at that time, the first pixel image data D+-+ that has already been stored is synchronized with CLK. The data is then stored in the flip-flop 112 as data delayed by one pixel.

Below, 3'f! j-th element, 4th pixel - image data D1
When -1D I-a-.- is input, it is delayed by flip-flops 113 to 115, and 6! When elementary image data is input, flip-flops 111 to 11
Each output of flip-flop 115 is Dl
-I, the output of the flip-flop 114 is -,, the output of the flip-flop 113 is DI-s, the flip-flop
The output of the flop 112 is DI-4, and the output of the flip-flop 111 is D1, -.

By combining this with the currently input image data D + -b of the 6th pixel, image data for 6 pixels in the same line can be obtained at the same time.

Therefore, when the five blocks are combined, as shown in FIG. 12, the image data D is 5 lines x 6 pixels, a total of 300 pixels.
CI~Dcs. are obtained at the same time.

5 lines x 6 pixels from the X direction delay circuit 72, total 300
Pixel image data DCI to DC36 are obtained, and pattern matching is performed using several pixels of these to detect halftone dots.

Figure 13 fat to fe) are examples of patterns used for pattern matching, and the pixel De15 marked with a circle is the current pixel of interest, and the pixels surrounded by solid rectangles are the surrounding pixels. Becomes a pixel.

For example, in the pattern shown in FIG.
Dc? .

Dell Dc+s+ Dell, Dell, D
There are 14 pixels from cza*Dczh to Dete. In pattern matching, the relationship between the pixel of interest and surrounding pixels is such that (i) the density of the pixel of interest is higher than the density of all surrounding pixels, (ii) the density of the pixel of interest is higher than the density of all surrounding pixels. If the density is lower than the density by a certain value or more, it is assumed that matches the pattern, and the pixel of interest is detected as a halftone dot. Note that the above-mentioned certain density is hereinafter referred to as a weight.

Figure 16 shows the density distribution when viewed one-dimensionally with halftone dots of 20% and 80% density and a section for simplifying each halftone dot, and the upper ic! In case (i), the part marked ■ in Figure 16, that is, the halftone dot itself, is detected as a halftone dot, and the above (
In the case of 11), the part marked ■ in FIG. 16, that is, the part surrounded by halftone dots, is detected as a halftone dot.

As mentioned above, when the density of a halftone dot is high, that is, the area ratio of black in a certain area is high, there is a white nucleus, and when the density is low, that is, the area ratio of white is high, there is a black nucleus. It is possible.

In performing halftone dot detection, the input data of the halftone dot image is binarized at multiple threshold levels as shown in Figure 14, and each binarized pattern is checked to see if it matches the halftone dot pattern. As shown in Fig. 15, in pattern matching that detects halftone dots, text and line drawing information around the binarization threshold level is affected by mechanical noise caused by density unevenness of the image itself, transportation unevenness, etc., illumination and Due to the above-mentioned pitch unevenness of CCD10, the character and line Mfi degree axis information is not the same, but the density of the input image becomes uneven, and the data after binarization has black breaks. If it matches the halftone pattern, it will be a false detection.

In other words, in this embodiment, the above-mentioned drawback is corrected, and even if some density unevenness occurs, the density difference level is sufficiently small compared to halftone dots, so a certain amount of density difference can be noticed. By matching the density difference pattern between the pixel and the surrounding iii pixels, the above drawback can be compensated for and false detections can be reduced.

Further, since this density difference does not change depending on the density (area ratio) of the halftone dots, the configuration of the circuit itself becomes relatively easy.

In the case of the pattern shown in FIG. 13 (al), the white level detection circuit 73 and the black level detection circuit 74 will be described below.

In the case (i) above, the black level detection circuit 74 performs the following:
In the case (ii), the white level detection circuit 73 weights the pixel of interest relative to the surrounding pixels, and determines the magnitude relationship between the weighted pixel of interest (weighted pixel of interest) and the surrounding pixels.

FIG. 17 shows the black level detection circuit 74 when the pattern shown in FIG. 13 fa) is used. The black level detection circuit 74 is
It is composed of a subtracter 161 and comparators 162 to 175. Note that this circuit is just an example, and the configuration may vary depending on the pattern, etc. The subtracter 161 weights the surrounding pixels of the pixel of interest, that is, the pixel of interest data Dco
klS and surrounding pixel data (in this case Dc! ~ D cs+
De? , Dc+z+D(131Dell, Dc
+*+ Dcta* Signals D1 to D, 14 are obtained depending on the magnitude relationship of the density of 14 pixels Dczb to Dcze.

Here, the signals D1 to D14 become "H" when (weighted attention data)>(peripheral pixel data), and become "L" otherwise.

Next, FIG. 18 shows the white level detection circuit 73 when the pattern of FIG. 13(a) is used.
is composed of an adder 141 and comparators 142 to 155. Note that this circuit is just an example, and the configuration may vary depending on the pattern, etc. The adder 141 weights the peripheral pixels of the pixel of interest, but the white level detection circuit 73 weights the pixel of interest data De15, contrary to the black level detection circuit 74.
weight data D. , and weighted pixel data of interest D
coss+s is generated and output to comparators 142-155. Note that this weight data D. 0 can be set arbitrarily. And in the comparators 142 to 155, the black level detection time j@7
Similarly to 4, signals I) a+ to D4, 4 are obtained depending on the magnitude relationship between the density of the weighted pixel of interest and the surrounding pixels. Here, the signal D a I-D a + a is the black level detection circuit 7
Contrary to 4, it becomes "H" when (weighted pixel data) < (peripheral pixel data), and becomes "L" in other cases.

Note that pattern matching may use not only a single pattern but also multiple patterns, in which case a black level detection circuit 7 similar to that shown in FIGS. 17 and 18 corresponding to each pattern may be used.
This can be realized by arranging 4 and the white level detection circuit 73 in parallel, as shown in FIG. 19, for example.

Next, the pattern matching circuit will be explained.

FIG. 20 shows an example of a pattern matching circuit using the pattern shown in FIG. 13 (Ta). The pattern matching circuit 75 is composed of AND gates 181 and 182 and an OR gate 183. Note that this circuit is just an example, and the configuration may vary depending on the pattern, etc. The signals D□ to D□4 obtained from the white level detection circuit 73 are H'' when (weighted pixel data) < (peripheral pixel data), and are “L” otherwise. Game
)181, input the signals D□~D-14, and input the signals D□~
When D4 and D4 are all "H'", that is, when the pixel of interest has a density lower than a certain weight compared to all surrounding pixels, it matches the pattern, so the pixel of interest is determined to be a halftone dot, and the signal is Set D□ to “H”. Conversely, signals Da+ to D□,
If even one of them is "L", it does not match the pattern, so the pixel of interest is determined to be a non-halftone dot, and the signal is
Similarly, the signals D1 to D□4 obtained from the black level detection circuit 74 are input to the AND gate 182, and when the signals D1 to D14 are all "H", the pixel of interest is set to "L". , the density is higher than a certain weight for all surrounding pixels, so it matches the pattern. Therefore, the pixel of interest is determined to be a halftone dot, and the signal b is set to "H", or conversely, at least one of the signals D□ to D□4 is L1.
When , it does not match the pattern, so the pixel of interest is determined to be a non-halftone dot, and a signal is sent. is set to “L”, and the signal D @ W + D a b is the OR gate 183
and when either one of the signals Dm@+Dab is "H", that is, when it matches one of the patterns and the pixel of interest is detected as a halftone dot,
The pixel of interest is finally set as a halftone dot, and the signal Dt is set to "H", and both signals Dm1m+Dab are set to "L"
, the pixel of interest is finally treated as a non-halftone dot, and the signal D
Let f be “L”.

When performing pattern matching using a plurality of patterns, for example, as shown in FIG. It determines whether the pixel of interest matches a pattern (whether the pixel of interest is a halftone dot or a non-halftone dot), inputs the output to the OR gate, and determines that at least one pixel of interest in each pattern is a halftone dot. In this case, the pixel of interest is finally determined to be a halftone dot, and if the pixel of interest is detected as a non-halftone dot in any pattern, the pixel of interest is finally determined to be a non-halftone dot. It can be achieved by doing this.

The halftone block detection circuit (1) 76 and the halftone block detection circuit (2177) will be explained.

The halftone block detection circuit (1176) and the halftone block detection circuit (2177) detect a block (halftone block l) in which there are IN number of halftone pixels in a block consisting of a plurality of pixels.
, also multiple W! Each block (halftone dot block 2) in which i elements exist is detected.

In conventional technology, when creating such a halftone block, if there is even one halftone pixel in the block, the block is treated as a halftone block and the area is divided into regions. As mentioned above, there is a drawback that if even one non-halftone pixel is mistakenly recognized as a halftone pixel due to noise or the like, the entire block is mistakenly recognized as a halftone block.

FIG. 21 shows image data when a halftone dot image with 100 lines and a density of 50% is read at the aforementioned 400 dpi. The hatched areas in the figure are halftone dots, and the numbers 1 to 16 above and to the left of the image data correspond to each pixel. As is clear from this figure, if a block of an appropriate size, for example 8 x 8 pixels, is used, there are 4 to 5 halftone dots, so there are multiple halftone dots in the block. If such a block exists, the above-mentioned drawbacks can be avoided by making the block a halftone block. However, if it is difficult to detect halftone pixels due to the influence of moire, etc., or if there are multiple pixels in a block, if that block is set as a halftone block, the halftone image part will be converted into a non-halftone image. Therefore, in this embodiment, when there is even one halftone pixel in a block, and when there are multiple halftone pixels in a block, the halftone block 1 is used. , and is detected as halftone block 2 and used for subsequent processing.

FIG. 22 shows the configuration of the halftone block detection circuit H(1) 76 and the halftone block detection circuit (2177). The presence or absence of halftone pixels in the main scanning direction of the block is detected, and the sub-scanning direction halftone block detection circuit <xi 203 detects whether there is even one line in which halftone pixels exist in the sub-scanning direction of the block. , the block is detected as halftone block 1.

The halftone block detection circuit (2) 77 uses the main scanning direction halftone block detection circuit (1) 201 to detect the presence or absence of halftone pixels in the main scanning direction of the block, and detects the presence or absence of halftone pixels in the sub scanning direction halftone block. By the detection circuit (2) 204,
When there are a predetermined plurality of lines in which halftone dot pixels exist, that block is detected as halftone block 2.

Further, the main scanning direction halftone block detection circuit + 21202 detects whether a predetermined plurality of halftone pixels exist or not during main scanning of the block, and the sub scanning direction halftone block detection circuit (1) 205 detects whether a predetermined plurality of halftone pixels exist or not. If there is even one line in which a predetermined plurality of halftone dot pixels exist in the sub-scanning direction of the block, that block is detected as halftone block 2. If that block is detected as halftone block 2 on either side, that block is detected as halftone block 2.

The details of each part are as follows, and the block size is 8i in the main scanning direction.
i! i element x 8 lines in the sub-scanning direction, 2ii in the block
When there are ii or more halftone pixels, halftone block 2
A case will be explained below.

The main scanning direction halftone block detection circuit (1) 201 will be explained.

The main scanning direction halftone block detection circuit (1) 201 includes an octal counter 210, a flip counter 210, as shown in FIG.
Flops 211-213, AND gates 214.215
, an OR gate 216, and a NAND gate 217. Note that this circuit is just an example, and the circuit differs depending on the size of the block.

Further, FIG. 25 shows an example of the timing of the operation of this circuit. Note that the signals from ■ to ■ in the figure correspond to the signals indicated by ■ in FIG.
Corresponding to each position of ~■. Further, the numbers above CLKO in FIG. 25 correspond to pixels.

The main scanning direction halftone block detection circuit (11201) will be explained below using these figures.

The main scanning direction halftone block detection circuit (11201 detects whether or not a halftone pixel exists in the 8 pixels in the main scanning direction of the block. Each output of Q, to Qc of the octal counter 210 is a reference signal Each time CLK is input, the output is changed sequentially as shown in FIG. 25, so by inputting this to the AND gate 214, the flip-flop
1 output■.

■ becomes "Hl" or "Lo" every 8 clocks.

For example, if the second pixel is determined to be a halftone dot and the signal Dt is "H", the output of the AND gate 215 is
Regardless of the state of
Therefore, this signal is latched at the next rising edge of CLK, and the output 2 of the flip-flop 212 becomes "H". Then, by inputting the signals ■ and ■ to the AND gate 215, the output ■ of the AND gate 215 becomes "H", and this signal ■ is input to the OR gate 216.
Thereafter, regardless of the state of the signal Df, the signal (2) becomes "H" and the signal (2) also becomes "H". Then, when the 9th pixel arrives, the signal ■ becomes "L", so when the signal Df is "Lo", the signal ■ becomes "Lo", and at the next rising edge of CLK, this signal is latched, and the signal ■ becomes "Ll". .Signal ■ and CLK-
By inputting to the t-NAND gate 217, the NA
The output ■ of the ND gate 217 becomes as shown in FIG. ■is a signal■
When is "H", that is, when there is a halftone dot in 8 pixels, it becomes "H", and conversely, when the signal ■ is "Lo", that is, when there is no halftone dot in 8 pixels, it becomes "L" .

Below, examples of timing will be shown in which there are two halftone dot pixels among the 8 pixels from the 9th pixel to the 16th pixel, and when there are no halftone dot pixels from the 17th pixel to the 24th pixel.

The main scanning direction halftone block detection circuit +21202 will be explained.

The main scanning direction halftone block detection circuit f21202
As shown in Figure 4, octal counters 220 and 221, flip-flops 222 to 224, and delays 225 and 226
, AND gate 227.228, OR gate 229.2
30 and a NAND gate 231. Note that this circuit is just an example, and the circuit differs depending on the size of the block.

In addition, Fig. 26 shows an example of the timing of the operation of this circuit. Note that the signals from ■ to [phase] in Fig. 26 correspond to the positions of ■ to [phase] in Fig. 24. do.

Further, the numbers on CLKO in FIG. 26 correspond to pixels.

Below, using these figures, the main scanning direction halftone block +2
1202 will be explained.

In the main scanning direction halftone block detection circuit (2) 202,
It is detected whether there are two or more halftone dot pixels among the eight pixels in the main scanning direction of the block. The outputs of Qa to Q of the octal counter 220 change sequentially as shown in FIG. 26 every time the reference signal CLK is input, so these are
By inputting it to the ND gate 227, the outputs ① and ② of the flip-flop 222 become “H” or “L” every 8 clocks.

For example, if the third and sixth pixels are determined to be halftone dots and the signal D is "H", the signal Df
By inputting the inverted signal of CLK and CLK to the AND gate 228, the output ■ of the AND gate 228 is determined when the signal Df is “
When the signal is "H", an inverted signal of CLK is output. Then, when this signal (2) is inputted to the clock of the octal counter 221, when the first signal (2) becomes "H", the Qm of the octal counter 221, Both Qc outputs are “Lo,” so the OR gate obtained by inputting these two signals to the OR gate 230
The output ■ of the gate 230 also becomes “L”, but when the signal ■ becomes “H” for the second time, the Q of the octal counter 221,
Since the output becomes "H", the signal (2) becomes "H". Since this signal (2) is latched at the next rising edge of CLK, the output (2) of the flip-flop 223 also becomes "H". After this, the Ql output maintains the "H" state until the octal counter 221 is cleared, so the signal ■ also goes "H".
maintain the condition. Then, by inputting the signal ■ and CLK to the NAND gate 231, the output ■ of the NAND gate 231 becomes as shown in FIG. 26. By inputting this signal ■ to the clock of the flip-flop 224, the output ■ Since the signal ■ is latched at the rising edge, the output [phase] of the flip-flop 224 becomes "H" when the signal ■ is "H" and when there are 2 Wi elements or more of halftone dot pixels among exactly 8 pixels, When the signal ■ is "L", when there is only one halftone pixel among exactly eight pixels, or when there is no halftone pixel, it becomes "L".The octal counter 221 is cleared. It is obtained by inputting the signal ■ to the delay 225, and inputting the obtained signal ■ and the signal ■ to the OR gate 229.The output ■ of the OR gate 229 is further input to the delay 226, and the delayed signal ■ is Advance counter 2
This is done by inputting to the clear terminal (CR) of 21.

Hereinafter, timing examples will be shown in which the 9th pixel to the 16th pixel are the case where one halftone dot pixel exists, and the 17th pixel to the 24th pixel are the case where there is no halftone dot pixel.

The sub-scanning direction halftone block detection circuit (1) (symbol 2°3 or 205; hereinafter expressed as 203) will be explained.

The sub-scanning direction halftone block detection circuit (1) 203 includes an octal counter 2402 memory 24 as shown in FIG.
1, OR gate 242, AND gate 243 and NA
It is composed of an ND gate 244.

Note that this circuit is just an example, and the circuit differs depending on the size of the block.

FIG. 28 shows an example of the timing of the operation of this circuit. The signals ① to ② in FIG. 28 correspond to the signals ① to ① in FIG. 27. Further, the numbers above 1/8 CLK in FIG. 28 correspond to blocks. The sub-scanning direction halftone block detection circuit will be explained below using these diagrams)
203 will be explained.

In the sub-scanning direction halftone block detection circuit (1) 203,
The main scanning direction halftone block detection circuit (1) 201 or the main scanning direction halftone block detection circuit (2) 202 determines whether or not there is a halftone dot pixel among the eight main scanning pixels of the block. After detecting whether two or more pixels exist or not, if there is a detection result that a halftone dot pixel exists in even one of the eight sub-scanning lines of the block, detect that block as halftone block 1, Further, when there is a detection result that there are 2M or more halftone dot pixels in the eight lines, that block is detected as halftone block 2.

First, detection of halftone block l will be explained.

The octal counter 240 sequentially counts up each time LSYNC is input, and these Q, ~Qc
By inputting the output to the NAND gate 244, a signal ■ is obtained. First, when the output of the octal counter 240 is 7, each output of Q a "" Q c becomes "H", so the signal ■ becomes "Lo".

And main scanning direction halftone block detection circuit (1) 203
The signal (=D□) of the detection result is now the 1st block and the 4th block.
If there is a halftone pixel in the block and it becomes "H", no matter what state the output (■) of the memory 241 is,
Since the signal ■ is “L”, the output ■ of the AND gate 243 becomes “Lo”.Then, the signal ■ and the signal ■ are OR gate 24
2 and obtains the signal ``0'', which then advances to the next line and when the output of the counter 240 is 0, the signal ``■'' becomes 1H''.

And the signal ■ is now “H” in the 2nd and 4th blocks.
Then, the output (■) of the memory 241 is a signal obtained by latching the output signal (■) of the OR gate 242 in the previous line with 1/8 CLK, and the output signal (2) of the memory 241 is a signal obtained by latching the output signal (■) of the OR gate 242 in the previous line with 1/8 CLK. Since the signal (2) is "H", the signal (2) becomes the signal that is output as is, and therefore the output (2) from the OR gate 242 is "H" in the 1st, 2.4th block. It becomes a signal.

The process continues in the same manner, and when the counter output is 6, the signal ■ becomes “Ho”.Then, the signal ■ is now 3rd block and the previous 7
If it becomes “H” for the first time including the line, then the signal ■
is 1H'', the signal ■ is the signal ■ held in the memory 241 that is output as is, and therefore the signal ■
The 1st to 4th blocks become a 1H" signal. This signal (2) is latched by 1/8 CLK and becomes the output (2) from the memory 241 in the next line, so in the end, 8 lines in the sub-scanning direction of the block Even in the middle 1st line, when the signal ■ is "Ho", that is, the detection result is that there is a halftone dot pixel among the 8 main scanning pixels of the block, this is held and the block is detected as halftone block 1, Outputs an “H” signal.

Conversely, if all the signals in the 8 lines are "L", that is, the detection result is that there is no halftone dot pixel, this is held and the block is treated as a non-halftone block and an "L" signal is output.Then, next When the output of the counter 240 becomes 7 again, the signal 2 becomes "L", so the output 2 of the memory 241 is no longer held and is cleared.

Regarding the detection of the halftone dot block 2, the operation is the same as that for the detection of the halftone dot block 1, by simply changing the signal 2 to Dl.

The sub-scanning direction halftone block detection circuit (2) 204 will be explained.

Sub-scanning direction halftone block detection circuit (2) 204 is the second
As shown in FIG. 9, it is composed of a memory 250, an AND gate block 251, and an OR gate 252. Furthermore, the AND gate block 251 is composed of a plurality of AND gates 260 to 287, as shown in FIG.

Note that these circuits are merely examples, and other configurations may be used.

Further, FIG. 30 shows the timing of the operation of this circuit up to the output of the memory 250, and FIG. 32 shows an example of the operation from the AND gate block 251 to the output of the OR gate 252.

The sub-scanning direction halftone block detection circuit (2) 204 will be explained below using these figures.

The main scanning direction halftone block detection circuit (inputs the signal D□ detected by the main scanning direction halftone block detection circuit 11201 to see if there is a halftone dot pixel among the 8 pixels in the main scanning direction of the block to D, N of the memory 250, The output is fed back to D02 and inputted, and so on. UTt output to DINff
The output of Do, , , is fed back to the input of , and the output of □ is fed back to the next input, and so on.
When the detection signal D91-1 of the line is first input to Dull, and then the detection signal D91-1 of the second line is inputted,
DOD? Since the output of + is input to R, N, Do
From the output of lllo, D□ is output with a delay of one line.

Below, the 3rd line, 4th line, - detection signal D*+-
s, D□-4, - are input sequentially, and when the 8th line detection signal D□-1 is input, each output signal from Dooy+ to $ is 1, 1 to D, 1. are the detection signals for the 1st line to the 8th line, -, -pet-s, and signals for 8 lines in the sub-scanning direction of the block are obtained.

Next, when the signals D*+l'' D, , , are input to the AND gate block 251, the AND gate block 251 inputs the signals 11 to D as shown in FIG.
, 18 are ANDed, so that the signal D11 becomes 1. , 18 as shown in FIG. 3. 4
At the ゜7.11.12th block, the signal D1□ is 2゜3.
4.6.8.9.At the 12th block, there is a halftone dot pixel in the main scanning 8mN element and it becomes "H", and the signal rises to 17. ~D,
If there is no halftone pixel in II and it is always “L”, the output signal Dk□~ from the AND gate block 251
Db3m is the signal D1. The fact that the signal Dez + D@+z and 3.4.12) are both 1H at the lock point indicates that there are at least two or more anchor point pixels in the 3.4.12 block. Therefore, 3,4.1
The second block is detected as halftone block 2 and set to 1H''.

Other signals cannot be detected as halftone block 2 because there is no block in which both lines are "H".
becomes “L”.Then, OR the signal I)+lI~Db3°
When input to the gate 252, 3, 4, 12 of the signal D1°
Since the block number is "H", the 3.4.12 block is detected as halftone block 2 and "H" is output.

Figures 33 to 36 show the results obtained from the circuit described above.
A specific example of a circuit that determines whether it is a halftone dot area based on the dot halftone block information DC22 dot halftone block information DH and the DG and DH of a total of six blocks (hereinafter referred to as areas) shown in FIG. FIG. 2 is a block diagram showing an example. Further, FIGS. 38 and 39 are timing charts showing the operation of the circuit for determining the halftone dot area.

The explanation will be given below based on these figures.

In Figures 33 to 36, 300.330 is P
I FORAM (first in first out ram), 301.302 is a large force D-F/F, 30
3 to 317. 319 to 325 are multi-input AND elements, 31
8, 326, 327, 329.333 is a multi-input OR element, 328 is an AND element, 331 is an OR element, and 332 is a shift register.

In FIG. 38, from the circuit described above, LGATE, 1/
8LGATE, 1/8CLK, IN-DC, IN-DH
(1-point or 2-point halftone block information input to DG and DH in FIG. 33) is input. The five signals in the upper row (L
GATE, 1/8LGATE, IN-DG, IN-DH
, 1/8CLK) IN-DC, IN-DH DATG
The signal showing the portions of n and DATHn in detail is the lower signal. IN-DG is 1-point dot block information data, 1.2° 3-40.
11. 12. 13-n, i.e., DATGn-1
, DATGn-2, DATGn-3゜DATGn-4
, -------DATGn -10, DATGn-1
1, DATGn-12, -n. IN-DH(2
Similarly, the dot dot block information data) is DATHn-1,
DATHn-2, DATHn-3, DATHn-4, -
=---DATHn-10°DATHn-11,DAT
Hn-12 and DATHn-13. PI FOR
AM300 uses 1/8 CLK for read/write CLK, and 1/8 CLK for write/reset signal and read/reset signal.
It is set as 8LGATE. In other words, if the data input from the DIN+ terminal is DATGn-1, the value written when the previous 1/8LGATE became rHJ at the same time, that is, the data from the nth line to the 8th line (DATG (n-8)-1] are sequentially read out in synchronization with 1/8 CLK.

Therefore, DC23, DH23, DG13. A signal with a timing of DHI3 can be obtained. Also DG23, DH23,
DG13. DH13 uses 1/8 CLK as a clock by multi-input D-F/F 301, and DG22. DH22,
DG12. D) Obtain a signal with a timing of 112. Furthermore, DG22. DH22, DG12. Similarly, the DH12 uses the multi-input DF/F 302 to output the DG21. DH2
1. Obtain DGll and DHII. This gives 1-point and 2-point halftone dot information DG for each block in the area shown in FIG.

DH is output at the same time and input to the next stage halftone area determination circuit. On the timing shown in Fig. 38, this means that 1/8L is applied to IN-DG and IN-DH at the nth line.
After GATE becomes “H”, calculate in 8 pixel units,
When the third DATGn-3 and DATHn-3 are input, DG23. From DH23, 1/8 LGATE becomes "H" 8 lines before the nth line, and then the third DATG (n-8)-3, DATH (n8)-3, DG22. From DH22, DATG (n-8) -2, DATH (n-8) -2 one 1/8 CLK before (the second after 1/8 LGATE became "Hl")
, DG21. From DH21, 1/8 LGATE is r
1st DATG after becoming HJ (n-8)-1,
DATH(n-8)-1, DG13. From DH13 n
1/8 LGATE is “H” 16th line before the 1st line
3rd DATG (n-16)-3,
DATH(n-16)-3, DG12. DATG (n-16)-2 from DH12
, DATH (n-16)-2, DGII, -DHII to DATG (n-16)-
, 1, DATH(n-16)-1, are obtained.

Figures 34 and 35 show that a certain condition is satisfied based on the 1-point and 2-point halftone dot information DC and DH of each block in the area of Figure 37 obtained at the same time in Figure 33 above. FIG. 3 is a block diagram showing a circuit that determines an area to be a halftone dot area.

The above-mentioned certain conditions are as follows in the area of FIG. 37.

1) When four pieces of 2-point halftone dot information DH are "H" and one or more pieces of 1-point halftone dot information DG are "H".

2) When 5 or more 2-point dot information DH is "H".

If either 1) or 2) is satisfied, that area is set as a halftone dot area. The above conditions are an example, and DH,
Of course, the number of DGs can be varied depending on the system.

As described above, there are a plurality of halftone detection signals within a halftone block. That is, the halftone dot area detecting section may perform halftone dot detection on six halftone dot blocks as DH1, that is, two dot halftone dots, but moiré occurs in the halftone original due to the phase difference with the reading pitch by CCD10. Due to this moiré, a plurality of halftone dots may not be detected even though the halftone dot block is actually a halftone image.

Furthermore, for example, a part of a character or dirt on the background may be detected as a single dot, and it may be incorrectly determined to be a halftone dot area.

Therefore, as described above, if one or more halftone dot blocks are used only for halftone dot detection, the above-mentioned erroneous judgments will increase, and furthermore, if two or more halftone dot blocks are only used for dot detection, halftone dot areas cannot be detected due to the moiré.

Therefore, the above-mentioned drawbacks are improved by a combination of one-dot halftone dot and two-dot halftone dot detection blocks, and further by a combination with a block without halftone detection.

The multi-input AND elements 303 to 317 in FIG. It indicates whether four pieces of information become "H" and transmits that information to the next stage circuit.

And B41 to B49. B41° to B□ are the inputs of the multi-input OR element 327, and any one of them becomes “H”.
” to one input of the AND element 328,
In addition, one-point dot information DGII to DG13. DG21~DC23 1 of them
The multi-input OR element 329 is informed whether there are more than one "H". Therefore, condition 1) applies to the output of AND element 328.

Next, the multi-input AND elements 320 to 325 select five dots from the two-point halftone information DHII to DH13, DH21 to DH23.
Select all the combinations one by one and use the multi-input OR element 326
The multi-input OR element 329 is informed whether even one of them is "H". Multi-input AND element 31
9 is two-point halftone information DH11 to DHI3. DH21~D
The multi-input OR element 329 determines whether all of H23 are “H”.
Condition 2) applies if the value is 0 or more.

Therefore, from the multi-input OR element 329, condition 1) or 2 is satisfied.
) is applied, an AMI signal of “H” is output, and otherwise, an AMI signal of #L” is output.

FIG. 36 shows that if the area in FIG. 37 is a halftone area (when the AMI signal is "H"), all the data, 8
FIG. 2 is a block diagram of a circuit whose halftone dot area is (pixels)×8 (lines). An explanation will now be given with reference to the timing chart of FIG. 39.

It is assumed that the image data DAT-IN is as shown in FIG. 39 with 1/8 CLK, 1/8 LGATE, and LGATE as standards. Here, DATn-1 is LG on the nth line.
Counting from the rising edge of ATE, the first image data is expressed in units of 8 pixels. Furthermore, AMIn is halftone area information detected by the above-mentioned circuit on the nth line, AM J
(n-8) is the (n-8)th line, AMI (
n-16) is the halftone dot area information for the (n-16)th line, and it is assumed that the signals at the timings shown in FIG. 39 are obtained for each.

FI FORRAM330 uses 1/8 CLK for read/write CLK and 1/8 LGAT for write/reset signal.
E. By setting the read/reset signal to LGATE,
When LGATE becomes "H", the halftone area information written when 1/8 LGATE is "H" is read out sequentially while synchronizing with 1/8 CLK. .

In FIG. 39, AMIn is image data DATn-1
And when DAT (n+1)-3, “At H3, AMI
(n-8) and AMI (n-16) are all "L" within the range of the image data shown in FIG. 39. Dout+, Dour of PIFORAM330
From the t terminal, only the portion corresponding to the image data DATn-1 is "H", and the rest is "L". The OR element 331 outputs a signal called OR output, which is transmitted to the shift register 332 and further outputs the OR element 331.
The multi-input OR element 333 obtains a signal B by ORing the output with the Q+ and Qt outputs (once latched and twice latched) of the shift register 332.

This is image data, DATn-1, DATn-2, DA
Tn-3, DAT (n-8)-1, DAT (n-8
)-2, DAT (n-8) In the area of -3, only the block of DATn-1 has halftone area information “H”
The halftone area information corresponding to the entire area is “
It will be set as “H”.

For example, in the final stage, the PIFORAM used in this example,
The image data is similarly delayed by the amount of delay caused by the multi-input D-F/F, etc., and the halftone area information is used as a control signal, for example,
By using a selector or the like, it is possible to separate text and halftones from image data that has undergone character processing and image data that has undergone halftone processing. In addition, in the description of the specific embodiment of the present invention, the area shown in FIG. 37 is used as the halftone dot determination area, but the size of the area can be changed depending on the input/output characteristics of the device, the characteristics of the target document, etc. However, this embodiment can also be applied to containers so as to reduce judgment errors. Furthermore, the conditions for determining the halftone dot area can also be varied for the reasons described above, thereby reducing determination errors.

FIG. 45 is a configuration diagram showing another example of the scanner. This configuration is the same as the configuration shown in FIG. 3 except that the sub-scanning magnification changing section 67 is removed.

Here, the effect of not inputting data after main scanning scaling to the area determination unit 70, but inputting only data after sub-scanning scaling will be described.

Figure 46 shows a model of the halftone dot shape corresponding to the magnification. (a) shows the halftone dot shape at the same magnification, and (b) shows the shape when moiré occurs in the halftone dot shape at the same magnification. show.

In (a), the halftone dots are resolved, and in (b), even if moiré occurs, they can be regarded as halftone dots. However, in the case of 50% reduction, the scaled halftone dots in only the sub-scanning direction in (C) and the scaled halftone dots in the main and sub-scanning directions in (d) are resolved. When rough moiré occurs, halftone dots are resolved in (el), but not in (f). This is because the input data is thinned out in the main scanning direction as described above. This is because of the fact that it is clearly better to pattern match data only in the sub-scanning direction when detecting halftone dots by pattern matching.

Further, (phantom to 0) is the case when the image is enlarged to 200%, and the halftone dots are resolved regardless of the presence or absence of moiré. However, as can be seen from the pattern, since the pattern enlarged only in the sub-scanning direction is not subjected to main-scanning magnification, the pattern matching area can be small and the circuit can be simplified. Therefore, by inputting only the data after sub-scanning scaling to the halftone dot detection section 70, the detection rate can be improved and the circuit can be simplified.

Next, the pixels for the area shown in FIG.
Consider the case where the pixels for the area shown in FIG. 8 are changed. This can be achieved by increasing the number of memories by 11 in the Y-direction delay circuit 71 shown in FIG. 7, and further increasing the number of F/Fs corresponding to the corresponding delay in the X-direction. The above-mentioned FIGS. 44(a) to (C) show patterns for each magnification regarding the pattern in FIG. 13(C).
A) is the same as IC) in FIG. 13, with peaks) having a 50% reduction and pattern (C) having a 200% enlargement, and this pattern is clear from the explanation of FIG. 46 above. Furthermore, white level detection and black level detection are the same as described above,
As shown in FIG. 47, the same-size data Df, ..., 50% reduced data Dtmt, 20
0% enlarged data Dyes are shown in Figures 17 to 2, respectively.
The output is as shown in Figure 0. Here selector 40
3, and by switching the signals of each magnification pattern according to the magnification selected by the magnification data key, dot pattern matching suitable for the magnification can be realized.

〔Effect of the invention〕

As explained above, according to the invention recited in claim 1.2, image information scaled in the sub-scanning direction at an arbitrary scale ratio,
By having a sub-scanning magnification means for identifying the halftone dot area, the image information is rescaled to the same size, compared using the halftone dot area identification pattern in the two-dimensional image area, and the result is output. With such a configuration, it is possible to accurately identify the halftone image area without increasing the number of circuit components.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the entire halftone area detection circuit according to an embodiment of the present invention, FIG. 2 is a schematic configuration diagram of a digital copying machine, FIG. 3 is an electrical configuration diagram of a scanner, and FIG. 4 5 is an explanatory diagram of an example of MTF correction, FIG. 6 is a block diagram showing the circuit configuration of MTF coefficient setting, FIG. 7 is a Y-direction delay circuit diagram, and FIG. 8 is a waveform diagram of input data and corrected data. The diagram is Y
9 is an explanatory diagram of control signals that control timing relationships. 1θ is a diagram of the X-direction delay circuit. FIG. 11 is a timing chart of the X-direction delay circuit. An explanatory diagram showing image data obtained by the directional delay circuit, FIG. 13 is an explanatory diagram showing a pattern used for pattern matching, FIG. 14 is a signal waveform diagram of a halftone image read by an image scanner,
FIG. 15 is an explanatory diagram of a conventional pattern matching method,
Figure 16 is an explanatory diagram showing halftone dots and their density distribution, Figure 17 is a block diagram of the black level detection circuit, Figure 18 is a block diagram of the white level detection circuit, and Figure 19 is the black level detection circuit and white level. Diagram showing an example of arranging detection circuits in parallel, No. 20
The figure is a block diagram showing an example of a pattern matching circuit.
Figure 21 shows a 4QQd halftone image with 100 lines and 50% density.
Explanatory diagram showing image data when read with pi, No. 22
The figure is a block diagram showing an example of a halftone block detection circuit, FIGS. 23 and 24 are block diagrams showing an example of a main scanning direction halftone block detection circuit, and FIG. 25 is a timing chart of the circuit shown in FIG. 23. , FIG. 26 is a timing chart of the circuit shown in FIG. 24, FIG. 27 is a block diagram showing an example of the sub-scanning direction halftone block detection circuit (1), and FIG. 28 is a timing chart of the circuit shown in FIG. 27. 29 is a block diagram showing an example of the sub-scanning direction halftone block detection circuit (2), FIG. 30 is an operation timing chart of the memory in FIG. 29, and FIG. 31 is an AND gate block diagram in FIG. 29. FIG. 32 is a timing chart of the circuit shown in FIG. 31, FIG. 33, FIG. 34, and FIG.
36 is a block diagram showing an example of a circuit for determining the halftone dot area, FIG. 37 is a diagram showing six blocks (areas), and FIGS. 38 and 39 are timing charts of the halftone dot area determining circuit. , FIG. 40 is a block diagram of the scaling process, FIG. 41 is a timing chart of the scaling process, FIG. 42 is an explanatory diagram of data stored in the magnification ROM, FIG. 43 is an explanatory diagram of the loop counter control section, and FIG. The figure is an explanatory diagram showing an example of a halftone detection pattern corresponding to a certain magnification, FIG. 45 is a configuration diagram showing another example of a scanner, and FIG. 46 is a modeled representation of a halftone dot shape corresponding to a certain magnification. FIG. 47 is an explanatory diagram showing input/output contents of the selector, and FIG. 48 is an explanatory diagram showing image data obtained by the X-direction delay circuit. 66... Main scanning magnification circuit, 67... Sub-scanning magnification circuit, 71... Y direction delay circuit, 72... X direction delay circuit, 73... White level detection circuit, 74...・Black level detection circuit, 75...Pattern matching circuit, 76
. . . Halftone block detection circuit (1), 77 . . . Halftone block detection circuit (2), 78 . . . Halftone area detection circuit. Figure (b) 1-bit shift (X2) Figure (X direction) d ~ Rumor sacrifice, 5----. 5゜Oct Fig. ---(:h-t Dr-z ---11n- Fig. 72 Fig. 20 Fig. 22 Fig. 2j Fig. 37 Main scanning (pixel) Fig. 43 Fig. 44 (a) (b) (C) Fig. 46 (b) (C) (d) (e) ( f) Figure 46 (Q) (h) (i) C horn mower and mower Figure 47 CPU data diagram

Claims (2)

[Claims] (1) An image reading means that divides the original image into a large number of minute pixel areas, reads the density thereof, and outputs an electric signal according to the density, and scans and drives the original and this image reading means relative to each other. , a first sub-scanning magnification means for changing the image magnification in the sub-scanning direction of the image by adjusting the scanning speed according to a specified image magnification ratio; and converting the analog signal outputted by the image reading means into a digital signal. a converting means for converting, a main scanning scaling means for thinning out or interpolating an image of a digital signal outputted by the converting means in the main scanning direction according to a specified image scaling ratio, and changing the image scaling ratio; recording dot and non-recording dot detection means for comparing the two-dimensional array pattern of the signal with a predetermined recording dot and non-recording dot detection pattern and outputting the result; An image area identification device comprising: a second sub-scanning magnification changer that thins out or interpolates the image information scaled by the sub-scanning magnification changer. (2) An image reading means that divides the original image into a large number of minute pixel areas, reads the density thereof, and outputs an electric signal according to the density, and scans and drives the original and this image reading means relative to each other. , a sub-scanning magnification means for changing the image magnification in the sub-scanning direction of the image by adjusting the scanning speed according to a specified image magnification ratio, and a conversion for converting the analog signal outputted by the image reading means into a digital signal. means, a main scanning magnification means for thinning out or interpolating the image of the digital signal output by the converting means in the main scanning direction according to a designated image magnification rate, and changing the image magnification rate; An image area identification device comprising a recording dot and non-recording dot detection means for comparing a dimensional array pattern with a predetermined recording dot and non-recording dot detection pattern and outputting the result.