JPH04149643A - Processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Industrial Application] This invention relates to an external memory and an error correction hood (hereinafter referred to as "EC
This relates to a processor that sends and receives data marked with "C").

[Conventional technology]

FIG. 2 shows a block diagram of a conventional processor that exchanges data with ECC and an external memory that stores data and ECC. In FIG. 2, 21 is a processor;
2 is an external data input/output terminal, 23 is an external ECC output terminal, 24 is an external ECC input terminal, 25 is an ECC circuit, 26
27 is a data register, 211 is an external memory, 2+2 is an external memory data storage section, and 213 is an external memory ECC storage section.

In the conventional processor 21 configured as described above, the external memory data storage section 212 can be tested.

[Problem to be solved by the invention]

However, in the conventional configuration described above, the external memory ECC storage section 213 could not be tested by the processor 21. In addition, the internal ECC in the processor 21 itself
It was also not possible to test circuit 25. For this reason,
With parallel computers that use many processors, it is not possible to test the entire system in parallel, which takes a long time. Furthermore, in order to perform tests in the mounted state, it is necessary to mount components for testing, which increases the mounting area.

It is an object of the present invention to provide an external memory ECC storage unit and an internal processor EC in a short time and without increasing the mounting area.
The object of the present invention is to provide a processor capable of testing C circuits.

[Means to solve the problem]

The processor of the present invention includes an ECC circuit that adds an error correction code when sending data and performs inspection and correction of the data using the error correction code when receiving data, and a plurality of data registers.
A register connected to multiple data registers; a comparator that compares the value of the two data registers with the value of the register; second and third selectors;
A CC circuit, a plurality of data registers, a comparator, a first . A control section that controls the second and third selectors, an external data input/output terminal that connects to the data storage section of the external memory, and an external ECC output terminal and external ECC input terminal that connects to the error correction code storage section of the external memory. It is equipped with

Then, the ECC output of the ECC circuit and the output of the register are connected to the input of the first selector, the output of the first selector is connected to the external ECC output terminal, and the ECC output of the ECC circuit is connected to the input of the second selector. and the external ECC input terminal, connect the output of the second selector to the input of the register, and connect the output of the register to the external ECC input terminal of the third selector.
The output of the third selector is connected to the ECC input of the ECC circuit.

[Effect]

According to the configuration of the present invention, a certain value is set in the register from the data register, the register is selected as the output of the first selector, and the value of the register is written into the external memory ECC storage section. After that, select the external ECC input terminal as the output of the second selector, and select the external ECC input terminal when reading the external memory.
The value stored in the C storage section is read into the register. By comparing the value written into the register, that is, the value of the data register, with the value read into the register using a comparator, the external memory ECC storage section can be tested.

In addition, the ECC output of the ECC circuit is selected as the output of the second selector, and when writing data to the external memory, the ECC output is selected as the output of the second selector.
Read the ECC output from the C circuit into the register. By comparing the value read into the register with the expected value in the data register using a comparator, it is possible to test whether the ECC circuit is adding ECC normally.

Furthermore, the value of the data register is set in the register, and the third
A register is selected as the output of the selector, and when reading data from an external memory, the value of the register is input to the ECC circuit as an ECC. By comparing the value of the data read into the data register with the expected value in other data registers using a comparator, it is tested whether the data inspection and correction by ECC in the ECC circuit is being performed normally. be able to.

〔Example〕

FIG. 1 shows the configuration of a processor according to an embodiment of the present invention and an external memory connected thereto. In Figure 1, 1
1 is a processor according to an embodiment of the present invention, 12 is an external data input/output terminal, 13 is an external ECC output terminal, 4 is an external ECC input terminal, 15 is an ECC circuit, 151.152 is a data port of the ECC circuit, 161 163 is a data register, 17 is a comparator, 18 is a first selector, 19 is a second selector, Ia is a third selector, 1b is a register, 1c is a control unit, 111 is an external memory 112 is external memory data A storage section 113 is an external memory ECC storage section.

The connection relationship will be explained below.

The external ECC output terminal 13 is connected to the external memory ECC storage section 113 together with the external ECC input terminal ]4.

The first selector 18 inputs the ECC signal of the ECC circuit 15.
Connect the output and the output of register ib, and connect the output to external E.
Connect to CC output terminal 13.

The second shifter 19 has an external ECC input terminal 14 as an input.
and the ECC output of the ECC circuit 15 are connected, and the output is connected to the input of the register ib.

The third selector 1a has an external ECC input terminal 14 as an input.
and the output of register 1b are connected, and the output is connected to the ECC input of ECC circuit 15.

The data port 151 of the ECC circuit 15 is connected to the external memory data storage section 112 via the external data input/output terminal 12, and the data port [52 is connected to the data register 16N-
Connect to 163.

Data registers 161-163 connect to the input and output of comparator 17.

Register lb is the comparator 17 and data register 161
Connect to ~163.

The operation of the processor 11 and external memory l1.1 configured as described above will be described below.

First, a case will be described in which the external memory +11 is tested.

Set the value to be tested from the data register 161 to register ib, and set the register ib to the output of the first selector 18.
is selected, the value of the data register 162 is stored in the external memory data storage section 112, and the value of the register lb is written into the external memory ECC storage section 113.

After that, the external ECC input terminal]4 is selected as the output of the second selector 19, and the value of the external memory data storage section 112 is read into the data register 163 via the disabled ECC circuit 15, and the external memory ECC memory The value stored in section 113 is read into register 1b.

Then, the value of data register 162 and data register 1
The external memory data storage unit 112 can be tested by comparing the value of 63 with the comparator 17.

Furthermore, the value written to register lb, that is, the value of data register 161, and register lbi:i! By comparing the stored value with the comparator 17, the processor 11 can test the external memory ECC storage section +13, which was conventionally not possible with the processor itself.

Next, a case will be described in which the ECC circuit 15 inside the processor 1 is tested.

When the ECC output of ECC circuit [5] is selected as the output of the second selector 19 and the value of, for example, the data register 161 is written to the external memory l11, the ECC output from the ECC circuit 15 is read into the register 1b. By comparing the value read into the register lb with the expected value, for example, the value stored in the data register 162, using the comparator 17, it is possible to test whether or not ECC has been added normally, which could not be done by the processor itself in the past. can be performed by Processor II.

Also, the value of the data register 161 is set to register lb, register lb is selected as the output of the third selector 1a, and data is enabled from the external memory 111.
When reading data into the data register 162 via the CC circuit 15, the ECC circuit 15 uses the value of the register 1b as ECC.
Enter. Data register 162 after reading data
By comparing the value of , for example, the value of the data register 163 with the comparator 17, the processor 11 performs a test to see if the data inspection and correction by ECC is being performed normally, which could not be done by the processor itself in the past. I can do it.

〔Effect of the invention〕

The processor of the present invention not only tests the external memory data storage section, but also tests the external memory ECC storage section.
It is possible to test the ECC circuit inside the processor, that is, test whether the addition of ECC and the inspection and correction of data by ECC are being performed normally. As a result, in a system that uses a large number of processors such as parallel computers, the test time for the entire system can be shortened. In addition, in terms of packaging, tests can be performed without the need to mount test components other than the processor as in the past, which has great effects in terms of area and reliability.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of a processor according to an embodiment of the present invention and an external memory connected thereto, and FIG. 2 is a diagram showing the configuration of a conventional processor and an external memory connected thereto. . 11... Processor, 12... External data input/output terminal, 13... External ECC output terminal, 14... External EC
C input terminal, 15... ECC circuit, 17... Comparator,
18・First selector, 19・Second selector, la
...Third selector, 1b register, 1c sub-control,
III...External memory, 112...External memory data storage unit, +13...External memory ECC storage unit, 161~
163... Data Nosta E7 = Shichinohe figure 111... External memory figure

Claims (1)

[Scope of Claims] An ECC circuit that adds an error correction code when transmitting data and inspects and corrects the data using the error correction code when receiving data, a plurality of data registers, and a register connected to the plurality of data registers; is connected to the plurality of data registers and registers, and compares the value of one data register among the plurality of data registers with the value of another data register, and compares the value of one data register among the plurality of data registers with the value of the other data register. A comparator that compares the value of the register, the first, second and third selectors, the ECC circuit, the plurality of data registers, the register, the comparator, and the first, second and third selectors. The first selector comprises a control unit, an external data input/output terminal connected to a data storage unit of an external memory, and an external ECC output terminal and an external ECC input terminal connected to an error correction code storage unit of the external memory. The ECC output of the ECC circuit and the output of the register are connected to the input of the ECC circuit, the output of the first selector is connected to the external ECC output terminal, and the second
The ECC output of the ECC circuit and the external ECC input terminal are connected to the input of the selector, the output of the second selector is connected to the input of the register, and the output of the register is connected to the input of the third selector. and the external ECC input terminal, and the output of the third selector is connected to the ECC input terminal.
A processor connected to the ECC input of the circuit.