JPH04149759A - Serial transmission circuit - Google Patents

Abstract

PURPOSE:To prevent a holding time from being shortened by automatically adjusting the holding time to a time almost equal to a time required from the n-th trailing edge of a serial transmission clock up to the n-th leading edge. CONSTITUTION:The 'L' state time width of a serial transmission clock is converted into the count data of an UP/DOWN counter 5 and the counter 5 counts down its contents by the succeeding 'H' state. The '0' state of the count data is detected by a data '0' detecting circuit 6, only when and the final leading edge of the serial transmission clock is detected by a serial transmission clock counter 3, the data '0' detection timing of the counter 5 is utilized. Consequently, the holding time can be automatically adjusted to the time width almost equal to an 'L' state time immediately before the final leading edge of the serial transmission clock and the receiving side of serial data can surely receive the data independently of a clock period.

Description

[Detailed Description of the Invention] Industrial Field of Application The present invention is applicable to serial) when the L transmission clock is in the "1." state, a fixed period is increased by a dedicated up/down counter]
5, count up the Syriano 1 transmission U to the initial value O, convert the "L" state time of the Syriano 1 transmission [] to the count data of the up-down counter 5, and make the Syriano 1 transmission U When , the up/down counter is set to 1 count (with the count data as the initial value).
By detecting the state in which the count data becomes "0", the time when the clock is in the "H" state becomes equal to the "L" state of the previous serial transmission clock. 2. The output holding time (hereinafter referred to as hold time) from the last rising edge of the serial transmission clock of the last bit of serial I' transmission data is detected. By applying the operation of the up/down counter, the hold time is set to "L" of the immediately preceding serial transmission clock.
This invention relates to a serial transmission circuit that can automatically adjust to the same extent as the state time.

2. Description of the Related Art Hitherto, microphones have been used for serial data transfer in data communication between a computer and another microcomputer, or between a microcomputer and another digital LSI.

A conventional serial transmission circuit will be described below.

FIG. 3 shows the configuration of a conventional serial transmitter circuit. In the figure, a shift buffer 1 receives a pulse-like signal for starting serial transmission (hereinafter referred to as a serial transmission start signal) through a latch or shift switching input section 10, and performs serial transmission when the serial start signal is in the "IJ" state. The data to be transmitted is received in parallel by the serial transmission data input section 9, and a latch operation is performed, and the serial number 1 is in the "■" state. The shift buffer output unit 12 outputs the serial '1' transmission data bit by bit at each rising edge of the serial '1' transmission [-] clock. The D flip flop 2, which is a delay holding means, receives the serial transmission data from the shift buffer output section 12 through the T-data input section 13, and outputs the serial transmission clock to the clock input section 14.
By receiving the inverted signal at , the output section 15 outputs serial number 1 transmission data in synchronization with the falling edge of the serial transmission clock. Serial transmission L]
The clock counter z3 receives the serial transmission clock "I".
The tsuku input section 16 outputs the rising edge of the IJ line and the tsuku. The reset input section 17 receives the serial transmission start signal and is reset to the "H" state. Serial) The output section 18 of the transmission clock counter 3 is:

When the counter 3 reaches a predetermined count value, it outputs "H". , - The shift register 38 receives the serial transmission start signal at the reset input 41, and the shift register 38 receives the serial transmission start signal at the reset input section 41, and
(The output part is reset in the “state”)
The shift data input unit 39 receives the shift clock 2, which has a higher frequency than the externally input serial transmission clock, and the shift data input unit 40 performs a shift operation a predetermined number of times. A predetermined delay time is added to the received signal, and the resultant signal is output from the shift data output section 42. The OR gate 8 inputs the output signals of the shift data output section 42 and the output section 15 of the D flip-flop to the OR gate input sections 28 and 29, respectively. OR as serial transmission data output by
The OR output of the gate output section 30 is obtained.

The operation of the serial transmitting circuit configured as described above will be described below with reference to the time chart of FIG. 4.

First, input a serial transmission start signal from the outside. A latch for data that is serially transmitted to the shift buffer 1 when the signal is in the “H” state, and a serial transmission clock counter 3.
and the reset of the shift register 38 are executed. By latching the data serially transmitted to the shift buffer 1, the output section 12 outputs data 1, which is the first bit of the serially transmitted data. Next, when the serial transmission start signal is set to the "L" state and a serial transmission clock is input from the outside, data 1 is outputted from the output section 12 of the shift buffer 1 at the timing of the falling edge of the serial transmission clock. It passes through the D flip-flop 2 and is held until the timing of the next falling edge. Next, the second bit data 2 of the serial transmission data is output from the output section 12 of the shift buffer 1 at the timing of the rising edge of the serial transmission clock. The same operation is repeated at both edges of the serial transmission clock, and at the (n-1)th rising edge, the n-th bit data n of the serial transmission data is output from the output section 12 of the shift buffer l. be done. At the next falling edge of the n-th serial transmission clock, the data n is output from the output section 15 of the D flip-flop 2 and held.

On the other hand, the serial transmission clock counter 3 counts the rising edge of the serial transmission clock, and the count value becomes n at the nth rising edge. When the number of serial transmission bits is n, the output section 18 of the serial transmission counter 3 becomes "L" when the serial transmission start signal is in the "H" state.
After entering the "H" state, the serial transmission counter 3 becomes "H" at the timing when the count value reaches n. Next, the shift register 38 has the function of delaying the output of the output section 18 of the serial transmission clock counter 3 by a shift clock input from the outside. It functions to delay only the rising edge of the output of the output section 18 of the transmission clock counter 3. The delay time will hereinafter be referred to as hold time. The output of the output section 42 of the shift register 38 rises after the hold time has elapsed after the output of the output section 18 of the serial transmission clock counter 3 rises.

Finally, the output of the output section 15 of the D flip-flop 2 and the output of the output section 42 of the shift register 38 are logically summed to output the serial transmission data output 30.

Problems to be Solved by the Invention However, in the conventional configuration described above, the hold time is a fixed amount, and considering the case where the serial transmission clock is intermittently received from the outside and the period of the serial transmission clock is short, the hold time is I have no choice but to shorten it. However, the side that receives the serial transmission data by delaying the serial transmission clock and using it as the receiving side's clock has the disadvantage that the serial transmission clock has a long period and may not be able to receive the last bit of data. Was.

The present invention solves the above-mentioned conventional problems by making the hold time a variable amount so that the hold time is approximately the same as the time in which the serial transmit clock is in the "L" state immediately before the final rise of the serial transmit clock. It is an object of the present invention to provide a serial transmitting circuit which allows a serial data receiving side to reliably receive data by automatic adjustment, regardless of whether the period of a serial transmitting clock is short or long.

Means for Solving the Problems In order to achieve this object, the serial transmission circuit of the present invention is configured such that when a serial transmission start signal is input from the outside, the serial transmission start signal is in the "H" state, and data to be serially transmitted is transmitted. a shift buffer for latching the latched data in parallel and shifting the latched data bit by bit at each rising edge of the serial transmission clock input from the outside when the serial transmission start signal is in the "L"state; At every falling edge of the clock, the delay holding means for delaying and holding the output of the final stage of the shift buffer and the serial transmission start signal are reset to the "H" state, and the serial transmission start signal is reset to the "L" state. ”
In this state, when a predetermined count is performed by counting up at the rising edge of the serial transmission clock, the signal becomes “H”.
When the serial transmission clock is in the "L" state, a serial transmission clock counter is used to output the serial transmission clock. When the serial transmission clock is in the "H" state, the clock is counted down, and an up/down counter having a reset input section, and a rising edge of the serial transmission clock is detected and applied to the reset input section of the up/down counter. A falling L-edge detection circuit for supplying a pulse-like reset signal, and receiving the run I data of the up/down counter and outputting ")-(" when the count data detects the "O" state. , a data “O” detection circuit for outputting “L” in other states, and an output of the data “O” detection circuit when the serial transmitter “] is in the “H” state and the output of the data “O” detection circuit is “ "H" state, and the output of the serial transmission clock counter is "H" state, and the output of the serial transmission clock counter is "
When the serial transmission data output, which is the output of the circuit, is in the "H" state, the serial transmission data output is set to the "1 (" state), and when the conditions are other than the above, the output of the delay holding means is passed through as the serial transmission data output. It becomes.

Effect: With this configuration, the “L” level of the serial transmission clock
The time width of the state is converted into count data of the up/down counter, and the “L” of the serial transmission clock is
In the “H” state that follows the “H” state, the up-down and
The counter is counted down, and the state in which the count data becomes "O" is detected by the data "0" detection circuit, and the last rising edge of the serial transmission clock is detected by the serial transmission clock counter. By using the detection timing of the data "0" of the up/down counter by the data "0" detection circuit, the hold time is
“L” immediately before the final rise of the serial transmission clock
The time width can be automatically adjusted to be approximately the same as the time width of the state.

EXAMPLE 4 An example of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a transmission circuit according to an embodiment of the present invention.Those having the same functions as those of the conventional example are given the same reference numerals and their explanation will be omitted. In the figure, the up/down counter 5 counts 11 clocks with a constant period sufficiently shorter than the serial transmission clock input from the outside to the clock manual section 22. is input, and when the serial transmission [] is in the "■7" state, it counts up, and when it is in the "I-H" state, !!i, it counts down. Also, the reset input section 21 inputs "■(" 5, Hidari-cho, Tsushi detection circuit 4, which is reset when the status is input,
When the serial transmission clock is input to the falling edge detection circuit input section 19, the timing of the falling edge of the serial transmission clock is output from the rising edge detection circuit output section 20.
A pulse-like signal is output and inputted to the reset input section 21 of the up-down counter. The count data 24 of the up/down counter is input to the data "O" detection circuit 6, and when the previous five self data 24 is "O",
"H" is output from the output section 25 of the data "O" detection circuit. Furthermore, when the data 24 is data other than "0", "L"' is output. The NAND gate 32 is
The input section 26 connects the output section 25 of the data "0" detection circuit.
It also receives the serial transmission clock at the input section 27. The output section 28 of the N A N D gate is such that both the input section 26 and the input section 27 of the same gate are "H".
Outputs 'L' only in the state.AND gate 33
is connected at its input 29 to the output 28 of the NAND gate.
Similarly, the input section 30 receives a clock having a constant cycle that is sufficiently shorter than the serial transmission clock supplied from the outside. The output section 31 is the input section 2
9 is in the "H" state, the clock received by the input section 30 passes through, but when the input section 29 is in the "L" state, the output section 31 outputs the "L" state. The output section 3
The output of 1 is input to the clock input section 22 of the up/down counter 5. AND gate 7 has its input 3
4 receives the output of the output section 25 of the data "0" detection circuit 6, its input section 35 receives the serial transmission clock, and its input section 36 receives the output of the output section 18 of the serial transmission clock counter 3. Receive. AND
The output section 37 of the gate 7 is connected to the input section 34 and the input section 3.
5, and the input section 36 are all in the “H” state.
The OR gate 8 receives the output of the output section 37 of the AND gate 7 at its input section 28 and also receives the output of the output section 15 of the D flip-flop 2 at its input section 29. When the input section 28 is in the "L" state, the output section 15 of the D flip-flop 2 passes through the output section 30 to output serial transmission data, and when the input section 28 is in the "H" state, the output section 30 outputs the serial transmission data. Output section 3
0, "H" is output.

Note that shift buffer 1. The D flip-flop 2 and serial transmission counter 3 have the same functions as those in the conventional configuration.

The operation of the serial transmitting circuit configured as described above will be described below with reference to the time chart of FIG. 2.

First, a pulsed serial transmission start signal is input from the outside. When the signal is in the "H" state, serially transmitted data in the shift buffer 1 is latched, and the serial transmission clock counter 3 is reset. By latching the data to be serially transmitted to the shift buffer 1, the output section 12 of the shift buffer 1 outputs the first bit data 1 of the serial transmission. Next, when the serial transmission start signal is set to the "L" state and a serial transmission clock is input from the outside, the data l output from the output section 12 of the shift buffer passes through the D flip-flop 2 at the timing of the serial transmission clock. , is held until the next falling edge of the serial transmit clock. Next, the second bit data 2 of the serial transmission data is output from the output section 12 of the shift buffer 1 at the timing of the rising edge of the serial transmission clock.

The same operation is repeated on both edges of the serial transmission clock, and at the (n-1)th rising edge of the serial transmission clock from the serial transmission start signal, the n-th bit of the serial transmission data is output from the output section 12 of the shift buffer 1. Eye data n is output. At the next falling edge of the n-th serial transmission clock, the data n is output from the output section 15 of the D flip-flop 2 and held.

On the other hand, the serial transmission clock counter 3 counts the rising edges of the serial transmission clock, and the count value becomes n at the nth rising edge. When the number of bits of serial transmission is n, the output of the output section 18 of the serial transmission clock counter becomes "H" only when the count value is n, and when the serial transmission start signal is input again, the output of the serial transmission clock counter 18 becomes "H". Outputs "H" until reset. On the other hand, when the serial transmission clock is in the "L" state, the up-down counter 5 counts up a clock with a constant period that is sufficiently shorter than the period of the serial transmission clock input from the outside, and the serial transmission clock is in the "H" state. When the switch is made, the count value immediately before the switch is counted down as the initial value. On the other hand, the falling edge detection circuit 4 generates a pulse-like signal at the falling timing of the serial transmission clock, and resets the up/down counter 5. Therefore, when the serial transmission clock is in the "L" state, the up/down counter 5 always counts up from the count value "O". Further, the count data 24 of the up/down counter 5 is input to the data “0” detection circuit 6,
When the count data is “O”, the data “0”
"H" is output from the output section 25 of the detection circuit 6.

As shown in the figure, when the time in the "H" state of the serial transmission clock is longer than the time in the "L" state immediately before, the count data of the up/down counter 5 eventually becomes "0".
”.At this timing, the data “O” detection circuit 6
An “H” level is output from the output section 25 of and input to the input section 26 of the NAND gate 32. On the other hand, the input section 27 of the NAND gate 32 receives the serial transmission clock t3.
y), if the output part f, 25 of the data "0" detection circuit 6 is in the "H" state and the serial transmission clock is in the "11" state, the N A N D gate 2
The output section 28 of No. 6 becomes "L". , the output section 28 is
・~ND Noah'-h 33's input section 29 is input, and the up-down counter '70 to 7 is input to the input section 30 of -buj, and the above-mentioned N, A N D
Gate: When the output part 28 of 32 is "■,", its l
The output 31 of the NND gate becomes "I," old. This r) Data “0” detection circuit 6, N, A NIT
: Gate 32 and AND gate 33 cause Siriano [When the time in the "I(" state of the transmitting clock is longer than the time in the "■," state immediately before (), the serial]["H" of the transmitting clock When the up-down counter 5 counts down in the "state," and the count data eventually reaches "0," the up-down counter is prohibited from being supplied to the up-down counter.
7. Hold this state until the serial transmission clock changes to the "F" state, and then perform the count-a-yb operation again...-)
4th serial transmission start signal, 4th serial signal [When the transmission clock falls, the up/down counter 5
performs a count-up operation from count data "O", and the nth serial transmission clock rises.
count down) 1 count data is “0”
The present invention can obtain the time from the second rising edge of the nth serial transmission clock until the up/down counter 5 stops when the count data is "0". The hold time is approximately equal to the time required from the 11th falling edge to the 11th rising edge of the JL transmission clock. Next, the output of the output section 20 of the data "O" detection circuit 4 and , the serial transmission clock and the output of the output section 18 of the serial transmission clock counter 3 are A I'J
is input to the D gate 7, and all three input signals are “H”.
When the output unit 37 is in the "state", the output section 37 becomes the ")-(" state.

The output unit 37 of the AND gate 7 and the output unit 15 of -F 3y output, serial transmission start signal input J
"7, Syria) Since the L transmission 1-1 count 73 is reset and reset, its output section 18 is "L,"L'-
, Naluta Me, Er Chronicle A N D Goo 1□ 7 No u3
When the output section 37 is in the state of "R,", the output of the output section 15 of the D-Fli-Bouf ■1 is OR.
Passing through the gate 8 (1ζ), -7), the serial transmitting clock No. 11 Ell QU rises [1) At the J turn, the serial transmitting L1 counter 3 +5 output section 18 outputs ")-"
17 When the output section 25 of the "0" detection circuit 6 becomes "■1",)s, the output section 37 of the door becomes "H", and the serial transmission data output becomes " ■(Fixed to "state" and held in this state until the next serial transmission start signal is input again.

As described above, according to this embodiment, the serial number 7) is transmitted [
] An up count counter that performs up or down f1 count operation by switching the state of the clock, and a rise j-7 for resetting at the falling edge of one clock and the rising edge of the first clock by serially transmitting the up/down and counting counters. A data detection circuit 7, a data "O" detection circuit 1k for detecting count data "O" from the count data of the up/down counter, a data "O" detection circuit 1k, a serial transmission clock
``and the detection circuit for the data ``0'' outputs ``II'', and the means for prohibiting the clock input of the up-down counter and the serial transmission [-] ``1''. , and when the output of the serial/1 transmitter is "11" and the output of the data "0" detection circuit is "1", the serial number [transmission data output is "H"] By providing a means for fixing the signal to
It is possible to automatically adjust the time to the same level as the time required to rise. Note that the D flip-flop used in the figure is a delay holding means that slows down and holds data only between the rising edge and falling edge of the Siriano 1 transmission clock, so it can be replaced with a JK flip-flop or other equivalent device that can perform this function. There is no problem in substituting a functional circuit.

Effects of the Invention As described above, the present invention particularly provides an up-down counter that counts up or down by switching the state of a serial transmission clock, and a system for resetting the up-down counter at the falling edge of the serial transmission clock. The falling edge detection circuit detects count data “0” from the count data of the up/down counter.
By providing a detection circuit for data "0" to detect "0", it is possible to automatically adjust the time to be approximately the same as the time required from the nth falling edge to the nth rising edge of the serial transmission clock. This makes it possible to realize an excellent serial transmission circuit with short hold times.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a serial transmitting circuit according to an embodiment of the present invention, FIG. 2 is a time chart of the same serial transmitting circuit, FIG. 3 is a block diagram of a conventional serial transmitting circuit, and FIG.
The figure is also a time chart of the serial transmission circuit. 1...Shift buffer, 2...D flip-flop, 3...Serial transmission clock counter, 4...Falling edge detection circuit, 5...
...up/down counter, 6...data "○" detection circuit, 7...AND gate, 8.
...OR gate, 9... Serial transmission data input section, 10... Serial transmission data latch clock input section, 11... Serial transmission clock input section, 12 ,15.18.20°25.28,3
1.37...Output section, 13...Data input section, 14, 16.22...Clock input section, 17...Reset input section, 19 ,26,27
゜29.30.34-36... Input section, 23.
...Up/down switching input section, 24...
Count data output section, 32...NAND gate, 33...AND gate, 38...
Shift register, 39...shift data input section, 40...shift clock input section, 42...
...Shift register output section. Name of agent: Patent attorney Haruaki Koebi Baka 26 Figure Figure

Claims (1)

[Claims] When the serial transmission start signal is input from the outside, the data to be serially transmitted is latched in parallel when the serial transmission start signal is in the "H" state, and when the serial transmission start signal is in the "L" state, the data to be serially transmitted is input from the outside. The latch data is set to 1 on every rising edge of the serial transmit clock.
a shift buffer for shifting bits bit by bit; a delay holding means for delaying and holding the output of the final stage of the shift buffer every falling edge of the serial transmission clock; state, and when the serial transmission start signal is in the "L" state and a predetermined number of counting operations are performed by counting up at the rising edge of the serial transmission clock.
a serial transmission clock counter for outputting "H"; and a serial transmission clock counter that counts up a clock continuously inputted from the outside with a cycle sufficiently shorter than the cycle of the serial transmission clock when the serial transmission clock is in the "L"state; An up/down counter that counts down the clock when the serial transmission clock is in the "H" state and further has a reset input section, and detects a falling edge of the serial transmission clock and sends a pulse to the reset input section of the up/down counter. a falling edge detection circuit for supplying a reset signal of the up/down counter; and a falling edge detection circuit for receiving count data of the up/down counter so that the count data is "0".
a data “0” detection circuit for outputting “H” when detecting the state and outputting “L” in other states;
means for inhibiting clock input to the up/down counter when the serial transmission clock is in the "H" state and the output of the data "0" detection circuit is in the "H"state; When the output of the data “0” detection circuit is “H” and the output of the serial transmission clock counter is “H”, the serial transmission data output is the output of this circuit. and a means for setting the output signal to an "H" state and passing the output of the delay holding means as the serial transmission data output when the conditions are other than the above conditions.