JPH04150338A - Clock extraction circuit - Google Patents

Abstract

PURPOSE:To improve immunity to consecutive 0s and to prevent out of synchronism by detecting consecutive 0s for a specific length or over, latching the state before the production of consecutive 0s and implementing VCXO control with the information latched on the occurrence of consecutive 0s. CONSTITUTION:A WDM phase comparator 10 receives a data and a shift register 11 fetches three data for in the preceding state and an adder 12 and a multiplier 13 are used to calculate An. The An is added to a data obtained by a multiplier 15 at an adder 14 to obtain an Sn. A consecutive Os detector 30 compares a reference level 32 with the An and consists of a comparator 31 outputting 1 when the An is small, a shift register 33 latching its output together with a past output, and an AND circuit 34 discriminating whether or not the output is all 1. On the other hand, the Sn for 15 preceding data are inputted to a mean value output circuit 40 and latched in a shift register 41. In this embodiment, when eight consecutive Os takes place, the mean value calculation circuit 42 calculates the Sn for 9-15 preceding data and the Sn are selected by a selector 50 and the result is outputted to a loop filter 20.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a clock extraction circuit on the reception side in a digital transmission system, and in particular uses a digital phase synchronization circuit and uses a waveform difference method (Wave Diff) for the phase comparator.
erence Method: Hereinafter referred to as WDM method)
This invention relates to a clock extraction circuit using a clock extraction circuit.

[Conventional technology]

Conventionally, clock extraction circuits using phase comparators based on the waveform difference method (hereinafter referred to as WDM phase comparators)
1st Year IEICE Communication Division National Conference Paper JP2-18
``Study of Low Jitter PLL for r2B+D Echo Canceller'' (Kokubei, Shinozuka et al.). Its basic configuration is shown in the block diagram of FIG. WDM phase comparator 1
The output of 0 is connected to a loop filter 20 and a variable frequency divider 23. The loop filter 20 adds noise (pattern jitter) to the output of the WDM phase comparator 10 due to code amount interference.
appears, so the complete integral type is more suitable than the lag lead type. The VCXO 21 oscillates at a frequency several tens of times higher than the original transmission lock rate, and this output is divided by a variable frequency divider 23 to obtain an extracted clock. The frequency division ratio is controlled by the output of the WDM phase comparator 10 only during initial training.

Here, the principle of the WDM method will be explained using FIGS. 8 and 9.

First, in FIG. 8, the waveform difference An is expressed as follows.

An==anX (an-+ an++)
・・・・・・(1) Focusing on the fact that when the waveform point an overlaps the peak point of the waveform, the value of An becomes 0, and VCX
The clock component can be extracted by controlling the system so that the value of An always approaches 0 by varying the oscillation frequency of O21. However, if control is performed using An as it is, there is a problem with the stability of the system, so in practice, An is often integrated and used. For example, 5n=An+2 An-+ −= (
2) is control to increase the oscillation frequency of VCXO21 when Sn>O, and vcx when Sn<0.

Control is performed to lower the oscillation frequency of , and control is performed such that the oscillation frequency remains unchanged when 5n=O.

Nhu? FIG. 9 and Table 1 always show which way the VCXO 21 is controlled depending on the phase relationship between a and the peak point of the input waveform. In either case, the oscillation frequency of the VCXO is controlled so that point a approaches the peak point of the input waveform.

In the case of FIG. 9(a), a, -+, an are (Or a n
+1 becomes (-), An becomes (+), and the VCXO 21 is controlled to increase its oscillation frequency. Figure 9(b)-(
d), the control direction can also be found from Table 1.

[Problem to be solved by the invention]

This waveform difference method is based on the premise that the input waveform is a waveform (for example, a bipolar waveform) that has a peak point. Therefore, in the case of a bipolar waveform, when the transmission data "1" is sent, the waveform has a peak point, but when the transmission data "0" is sent, the An There is a high probability that the value of will be 0. For this reason, when the extracted clock is synchronized with the input waveform, if a long series of 0's is input, the VCXO will no longer be controlled, making it more likely to become out of synchronization.

In particular, when the free-running frequency deviation of the VCXO is large, or when there is a deviation in the transmitting side transmission lock rate, there is a problem that the degree of risk increases.

The purpose of the present invention is to solve such problems and to
To provide a clock extraction circuit which is less likely to become out of synchronization even if the clock is inputted.

[Means to solve the problem]

The configuration of the present invention is such that in a clock extraction circuit using a phase-locked loop including a digital phase comparator using a waveform difference method, a loop filter, and a VCXO, consecutive 0s of a specific length or more are detected in a transmission code sequence of an input signal. an O series detection means for detecting; an average value output means for holding past outputs of the digital phase comparator and outputting the average value thereof; and a selection means for selecting the output of the average value output means and supplying the selected output to the loop filter.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention, FIG.
The figure is a circuit block diagram showing details of each part of FIG. 1.

The WDM phase comparator 10 also inputs waveform data through the input terminal 1, and takes in the data for the past three times into the shift register 11. Based on these data, adder 122 multiplier 1
An=anX(FL n-1a n+1 ) using 3
Perform the calculation. An is further added to the adder 14 and the multiplier 15
It is added to the +S and -1 data obtained in , and Sn is obtained.

The zero series detector 30 includes a comparator 31 that compares the reference level 32 and the value of An and outputs 1 when An is smaller, and a shift register 33 that holds the output including the past one. , and an AND circuit 34 that determines whether the outputs of the shift registers are all l. In this embodiment, by providing eight stages of shift registers, eight consecutive 0s are detected and 1 is output as the output signal SEL.

On the other hand, the past 15 values of Sn are held in the shift register 41 in the past average value output circuit 40. Since Sn is integrated, if it continues to be 0, it will eventually become 0, and the vcxo will no longer be controlled. However, in this example, when 0 continues 8 times, from 1
The value calculated by the average value calculation circuit 42 for the values of Sn up to five times ago is switched to Sn by the selector 50 and output to the loop filter 20.

Therefore, even in the period of continuous zeros, the VCXO 21 is controlled in the same direction as before the occurrence of continuous zeros, making it less likely that synchronization will occur.

FIG. 4 is a flowchart summarizing the operation outlined above. This is a PAD diagram representing one operation from WDM phase comparison to selector, and in reality, this flow is repeated infinitely.

Regarding this example, the phase error of the extracted clock with respect to the input signal waveform peak was calculated by computer simulation. The transmission code was a bipolar code, and 30 "0"s were inserted at three locations during continuous transmission of random patterns. In this case, it has been found that in contrast to the phase shift in the conventional configuration, the effect of zero series does not appear in this embodiment.

In FIG. 1, the loop filter 20 is of a complete integration type using a resistor and a capacitor, and the frequency division ratio of the frequency divider 22 is fixed.

Next, the O-connection detection means of this embodiment can also be implemented in a configuration as shown in FIG. 5, and FIG. 8 shows a flowchart (PAD diagram) showing its operation.

First, the output signal An of the WDM phase detector 11 is converted into a positive value by the absolute value conversion circuit 35. An integration circuit consisting of an adder 36 and a latch 37 performs integration of An.

The counter 39 counts up every time it is added up, and the count reaches 8.
At the end of the cycle, the comparator 38 compares the integrated value 2 with the reference level 32. If 0 continues, the integrated value becomes O or a value close to O, so it can be easily determined whether 0 continues.

The subsequent operations are the same as those in the first embodiment, and will therefore be omitted.

Note that although the loop filter in this embodiment is assumed to be an analog circuit, a digital filter may also be used.

〔Effect of the invention〕

As explained above, the present invention is based on a means for detecting a continuous 0 of a specific length or more, a state before the occurrence of the continuous 0, and information on the state held when the continuous 0 occurs. Since the VCXO is controlled by
This has the effect of improving the continuous zero tolerance in a PLL system using a phase comparator using the waveform difference method, and making it difficult for synchronization to occur even with deviations in the oscillation frequency of the vcxo and deviations in the transmission lock rate on the transmitting side.

[Brief explanation of drawings]

FIG. 1 is a block diagram of one embodiment of the present invention, FIG.
The figure is a circuit block diagram showing details of each part of Fig. 1, Fig. 4 is a flowchart showing the operation from Fig. 1 to Fig. 3, and Fig. 5 is a circuit of another example of the O-link detector shown in Fig. 1. Block Diagram,
Fig. 6 is a flowchart of the embodiment shown in Fig. 5, Fig. 7 is a block diagram of an example of a clock extraction circuit using the conventional waveform difference method, and Figs. 8 and 9 explain the principle of the waveform difference method. FIG. 10...WDM phase comparator, 11, 33.41
...Shift register, 12,14.36...
・Adder, 13.15... Multiplier, 20...
...Loop filter, 21...vcxo, 2
2... Frequency divider, 23... Variable frequency divider,
30...0 series detector, 31.38...
Comparator, 32...Reference level, 34...
・AND circuit, 35... Absolute value conversion circuit, 37
...Latch circuit, 39...Counter,
40...Average value output circuit, 42...Average value calculation circuit, 50...Selector. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] 1. In a clock extraction circuit using a phase-locked loop including a digital phase comparator based on the waveform difference method, a loop filter, and a VCXO, a clock extraction circuit using a phase-locked loop including a digital phase comparator based on the waveform difference method, a loop filter, and a VCXO, 0 series detection means for detecting continuity; average value output means for holding past outputs of the digital phase comparator and outputting the average value thereof; and an output of the digital phase comparator based on the output result of the 0 series detection means. and a selection means for selecting and supplying the output of the average value output means to the loop filter. 2. The 0-run detection means consists of a comparator that compares the input signal with a reference level, a shift register that receives the output of this comparator and holds a certain length of data, and a logical product of the outputs of each stage of this shift register. 2. The clock extraction circuit according to claim 1, further comprising an AND circuit that takes .