JPH04153716A - Bus control circuit - Google Patents

Abstract

PURPOSE:To improve the throughput by providing a clock arbitrating incorporating a clock selector and a clock mode selector which generates a control signal for a clock synchronizer. CONSTITUTION:The clock selector 11 selects a clock signal 6 with a select signal 15 and a clock generator 5 generates an optional reference clock signal 7. With a clock signal 10, input information of data is supplied to a clock mode selector 9 to generate a status signal 14. Then the clock synchronizer 13 generates a clock signal 17 for synchronization from clock signals 12 and 16. Here, data from a VME bus 2 can be sent to a CPU at timing T2 by using the clock signal 17, so the CPU can reads data at read timing T3. Consequently, the speeding of data access, i.e. the improvement of the throughput is realized.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bus control circuit, and more particularly to an arbitration circuit for operating clocks of a VME bus control circuit.

[Conventional technology]

The conventional VMEbusll11 circuit will be explained with reference to FIG. In FIG. 3, board 31, V
M E bus 32 , clock generation circuit 33 on board 31 . VME operating on reference clock signal 37
bus control circuit 34. clock signal 36 to VM
A clock generator 35 that generates an arbitrary reference clock signal for controlling the Ebus control circuit 34, and a clock generation circuit 3.
Clock signal 36 from 3, VMEbus control circuit 34
A reference clock signal 37 is shown which controls the reference clock signal 37.

The conventional VMEbusiiIl11 circuit 34 operated using a reference clock signal 37 obtained by converting the clock signal 36 from the clock generation circuit 33 to an arbitrary frequency using the clock generator 35 as a reference clock.

[Problem to be solved by the invention]

The conventional VMEbus control circuit described above operates using the reference clock signal 37 generated from the clock signal 36 from the clock generation circuit 33 on the board 31. I couldn't get it to work with the serial clock. Also, VME
In a system where multiple boards operate simultaneously on bus32 (multi-10 processing), VMEbus
32 serial clocks and each board 31 can improve the overall system throughput, but if the operating clock frequency of each board is different, individual control circuits are required, so one system The drawback is that it is extremely difficult to synchronize as a whole, and throughput cannot be improved.

SUMMARY OF THE INVENTION An object of the present invention is to provide a bus control circuit that solves the above-mentioned drawbacks and allows for easy improvement of throughput.

[Means to solve the problem]

The configuration of the bus control circuit of the present invention selects one of two clocks: the clock signal from the clock generation circuit on the board operating on the VMEbus, and the serial clock from the VMEbus. a reference clock generator that generates a clock of any frequency from the output signal from the clock selector; and a clock selector that generates a clock of any frequency from the output signal from the clock selector; a clock synchronizer that generates a synchronizing clock signal for synchronizing input and output of data from a signal; and a clock mode selector that generates a control signal for the clock selector and clock synchronizer. It is characterized by being equipped.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing a bus control circuit according to an embodiment of the present invention, and FIG. 2 is a timing diagram illustrating the operation of the first embodiment. In FIG. 1, in this embodiment, boards 1, VMEbus 2. Clock generation circuit on board 3.
4. VMEbus control circuit operating with reference clock signal 7 and synchronization clock signal 17; A clock generator 5 generates an arbitrary reference clock signal for controlling the VMEbus control circuit 4 from the output signal from the clock selector 11, and a clock signal 6°VMEbus from the clock generation circuit 3.
@ Control circuit 4 sends resumption circuit 4 quasi-tallock signal 7. Clock arbitration circuit 8. Clock selector 11 and clock synchronizer 1
9. A clock mode selector that generates a signal to control 9.
Control signal 10 for clock mode selector 9. Clock selector 11° for selecting clock signal 6.12 Serial clock 12° from VMEbus2 clock signal 12.16. a clock synchronizer 13 that generates a synchronization clock from the status signal 14 and the status signal 14; Status signal 14 for controlling clock synchronizer 13. Select signal 15 for controlling clock selector 11. Clock signal 16 selected by clock selector 11. VMEb
The us control circuit N4 control N4 synchronization clock signal 17 is shown.

When operating with the clock signal 6 from the clock generation circuit 3 on the board 1 as in the past, the clock mode selector 9 is set to operate with the clock signal 6 using the control signal 10, and the select signal 15 is generated. Next, the clock selector 11 of the select signal 15 selects the tarok signal 6, and the clock generator 5 generates an arbitrary reference clock signal 7. Then, the VMEbus control circuit 4 is controlled by the reference clock signal 7.

In addition, when operating with the tarok signal of the serial clock 12 from VMEbus2, the clock mode selector 9
The control signal 10 is used to set the clock signal 12 to operate, and the select signal 15 is generated. An arbitrary reference clock signal 7 is generated. Then, the reference clock signal 7 is used to control the control circuit of the VMEbus @ control circuit 4, and furthermore, in a system (multiprocessing) in which a plurality of boards 1 are operated simultaneously on the VMEbus2, the operation clock on the board 1 and the VMEbus Regarding the case where the frequency of the serial clock 12 of the bus is different, the second
This will be explained using the timing diagram shown in the figure.

FIG. 2 is a timing diagram showing the operation of the CPU on the board 1 reading data from the VMEbuS2. In FIG. 2, first, the clock mode selector 9 is set to operate with the control signal 10 and the clock signal 6, and the select signal 15 is generated. , the clock signal 6 is selected, and the clock generator 5 selects an arbitrary reference clock signal 7.
generate. Then, data input information is given to the clock mode selector 9 using the control signal 10 to generate the status signal 14.Next, the clock synchronizer 13 converts the status signal 14 and the tarok signal 12.16 into the synchronization clock signal 17. generate.

Here, if we consider the case where it is operating only with the clock signal 6, the data from V M E bus 2 is Tl
Since the data is input at timing T3, the data is sampled at timing T3 and sent to the CPU on board 1 (the second waveform from the bottom in Figure 2), so the data cannot be read at the CPU reading timing T3. Data will be read at the next timing T4. Therefore, if the synchronization clock signal 17 described above is used, VMEbu
Since the data from S2 can be sent to the CP Ll at the timing of T2 (the lowest waveform in Figure 2), the CPU
can read data at read timing T, speeding up data access (improving throughput)
can be achieved.

In the above description, the clock signals 6 and 12 are used as separate input signals, but it is clear that the same effect can be obtained by using one or more clock signal inputs. Further, although the reference clock signal 7 and the synchronization clock signal 17 are made into one output signal, it is clear that the same effect can be obtained even if a plurality of output signals are used for control.

Further, although the selection of the clock signal and the control of the synchronization clock were performed using the signals 14 and 15, the same effect can be obtained even if the control is performed by providing registers, flags, etc. on the circuit.

〔Effect of the invention〕

As described above, the present invention includes a clock selector that selects one of two clocks, a clock signal from a clock generation circuit on a board and a serial clock from a VMEbuS, and an output from the clock selector. A reference clock generator that generates a clock of any frequency from a signal, and a clock that generates a synchronization clock for synchronizing data input and output from the VMEbus serial clock and the clock signal from the clock generation circuit on the board. Since it has a clock arbitration circuit that includes a synchronizer, the clock selector, and a clock mode selector that generates a control signal for the clock synchronizer, the V M
It is possible to operate with a serial clock from the Ebus, and has the advantage that a multiprocessing system with a plurality of boards can be easily constructed on the VMEbus.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a bus control circuit according to an embodiment of the present invention, FIG. 2 is a timing diagram explaining the operation of the embodiment shown in FIG. 1, and FIG. 3 is a block diagram of a conventional VMEbus control circuit. It is. 1.31-... board, 2, 32-VME bu
s -3,33...Tarlock generation circuit, 4.34...
- VMEbuslltB circuit, 5.35... Clock generator, 6.36... Clock signal from the clock generation circuit, 7.37... Reference clock signal of the VMEbus control circuit, 8... Tarock arbitration circuit, 9... Clock mode selector, 10... Control signal from board, 11... Clock selector, 12... VME
Serial clock from buS, 13--clock synchronizer, 14--status signal for controlling clock synchronizer, 15--select signal for controlling clock selector,
16 -- Clock signal for controlling the clock generator, 17
... Synchronization clock for the VME bus control circuit.

Claims (1)

[Claims] A clock selector that selects one of two clocks: a clock signal from a clock generation circuit on a board operating on the VMEbus and a serial clock from the VMEbus, and a clock selector that selects an arbitrary frequency from the output signal from the clock selector. a reference clock generator that generates a clock;
a clock synchronizer that generates a synchronizing clock signal for synchronizing data input/output from the serial clock of the VMEbus and a clock signal from the clock generation circuit on the board; and a clock synchronizer for the clock selector and clock synchronizer. A bus control circuit comprising a clock arbitration circuit incorporating a clock mode selector that generates a control signal.