JPS6288030A - Logic circuit - Google Patents

Abstract

PURPOSE:To perform a process at a high speed by selecting dynamically one of plural clocks as a synchronizing signal in the transition time of a control state and supplying it to a state register according to the contents of a storage register for data, etc., and the state register. CONSTITUTION:The titled circuit is constituted so that the content of a register 11 in which the data, etc., are stored is processed at an arithmetic circuit 12, and each signal of the register 11, a state register 14, and clocks CL1-CL4 is inputted to a control circuit 15, and a control signal from the circuit 15 is supplied to the registers 11 and 14 and the circuit 12. And the circuit 15 supplies the signal that regulates an arithmetic content to the register 11 from a control state from the register 14 and an arithmetic result from the register 11 by the clocks CL1-CL4, and supplies the signal that assigns the transition destination of the control state and the clock that synchronizes the transition of the control state to the register 14.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a logic circuit, and more particularly to a logic circuit that allows a plurality of operations requiring different times to be executed without waiting time.

[Prior art and its problems]

As shown in FIG. 3, the conventional logic circuit inputs a register 21 for storing data and operation results, the contents of this register through a signal line 201'e, and sends a control signal from a control circuit 25 to a signal 11i1203. an arithmetic unit 20 having an arithmetic circuit 22 that performs arithmetic processing by inputting data through a state register 24, the contents of the register 21, the contents of the state register 24, and a plurality of clocks; and a control unit 23 having a control circuit 25 that supplies a control signal to the arithmetic circuit 22.The state register 24 receives one clock (third 214) in the figure. FIG. 4 is a time chart showing the operation of the conventional logic circuit shown in FIG. OLI~C
L4 is a clock whose phase differs by one unit time, and (
(a) shows the execution timing when several operations with different required times are executed, and (b) shows the state of the status register 24.

(The meaning of the operation shown in al is illustrated below.

(1) CIR=BBUS: BBUS data t-C
Store IRK.

(2) X=OP1 (BBUS, CIR): Performs the operation specified by OPI on the BBUS data and CIR data, and stores the result in t-X.

(3) Y=OP2 (BBUS, X, CIR):
O to BBUS data, X data and CIR data
Perform the operation specified by F2 and store the result in iY.

The time required for the ratio calculation shown in tal is CIR=BBU8: 2 unit time 01'
l: 4 credit hours UP2. OP3
．． OP5: 3 credit hours UP4
: 5 credit hours.

As shown in FIG. 4, even in conventional logic circuits, for operations that do not involve the bus BBUS, OF2°OF2
If the required time is shorter or longer than 4 unit hours, respectively, CLl when the state is P3 and PO when the state is P3.
It can be executed by latching the operation result in CL3 when Even though there is no relationship, it has to be executed in synchronization with clock CL4. This is because operations involving the bus change the data bus, so a signal indicating which operation is being executed is required, but the signal indicating that a specific operation is being executed is based on the contents of the status register. It is difficult to generate it from anything other than the contents of the register 21, and this is because the contents of the status register 24 always change in synchronization with the clock CL4 as shown in (a).

[Purpose of the invention]

The present invention eliminates the drawbacks of the prior art and executes multiple operations with different required times without waiting time in a logic circuit having an operation section having registers and an operation circuit, and a control section that controls the operation processing by these. The purpose is to provide the necessary means to make this possible.

[Structure of the invention]

According to the present invention, there is provided an arithmetic unit having a register for storing data and operation results, an arithmetic circuit for performing arithmetic processing on the contents of this register, a status register, the contents of the status register, the contents of the register, and a plurality of clocks. a control unit having a control circuit that inputs and supplies control signals to the register, the state register, and an arithmetic circuit, the control circuit controlling the state register according to the contents of the register and the contents of the state register. , there is obtained a logic circuit characterized in that it is configured to dynamically select and supply one of a plurality of clocks as a signal synchronized at the time of transition of a control state.

〔Example〕

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the embodiment of the present invention shown in FIG. 1, a register 11 for storing data and calculation results, the contents of this register are inputted via a signal line 101, and a control signal is sent from a control circuit 15 to a signal line 103. An arithmetic unit 10 having an arithmetic circuit 12t which performs arithmetic processing by inputting data through a state register 14, the contents of the register 11, the contents of the state register 14, and a plurality of clocks. and a control circuit 15t that supplies a control signal to the arithmetic circuit 12.The state register 14 dynamically receives one of the plurality of clocks as a signal to synchronize with the transition of the control state. This is a logic circuit configured to selectively supply the following information. The register 11 is a register array consisting of a plurality of registers for storing data, calculation results, etc., and receives and receives synchronization signals from the control circuit 15 to the individual registers that make up the register array via a signal line 102.
It receives and stores the output of the arithmetic circuit 12 through the signal line 101, supplies the output to the arithmetic circuit 12 through the signal line 101, and further supplies the output to the control circuit 15 through the signal line 106. It is configured like this.

The arithmetic circuit 12 is a combinational logic circuit play consisting of a plurality of combinational logic circuits, and is connected from the register 11 to the signal line 101.
The entire output is taken through the ffi, and the nine control circuits 15
The signal that determines the content of the calculation to be performed by each combinational logic circuit constituting the combinational logic circuit array is received via the signal line 103t from the combinatorial logic circuit array, and the result is sent to the register 11 via the signal line 105. is configured to output.

The state register 14 receives a signal from the control circuit 15 via the signal line 104 to determine the transition destination of the control state, and a clock signal to synchronize the transition of the control state via the signal line 107. It is configured to perform this and supply the result to the control circuit 15. The control circuit 15 uses the control state input from the status register 14 and the calculation result input from the register 1 via the signal line 106 to determine the clock CL input via the signal lines 111-114.
I to 4 send a signal to the register 11 via the signal line 102 to determine the content of the operation for each combinational logic circuit, a signal to the state register 14 via the signal line 104ft to specify the transition destination of the control state, and a signal to the state register 14 via the signal line 104ft. They are configured to supply clocks for synchronizing control state transitions via signal lines 107, respectively.

FIG. 2 is a time chart showing the operation of one embodiment of the present invention. CLI to CL4 have different phases for each unit time, and (a) shows the execution timing when several operations with different required times are executed, and (b) shows the state of the status register 14. It shows.

The meaning of the operation shown in fat is illustrated below.

(1) CI = BBUS: BBU, S data to C
Store in IR.

(2) X = UPI (BBUS, CIR)
: UPI for BBUS data and CIH data
Performs the operation specified by and stores the result in t-X.

(3) Y = OF2 (BBUS, X, CIR)
: Perform the operation specified by OF2 on the data of BBU8, the data of X, and the data of CIR, and store the result in iY.

(The time required for the calculation shown in al is I CI = BBUS: 2 unit time OPI
: 4 credit hours OP2. OP3. OP
5: 3 credit hours OP4
: 5 credit hours.

In FIG. 2, the CIR-BBUS calculation is first performed. Here, the contents of the status register 14 are PO as shown in (b), and this operation is completed in 2 units of time.

At this time, the control circuit 15 uses the contents of the status register 14 and the contents of the register 11 to output the signal line 107 to the output signal line 107, which is the clock CL2, which is two units of time apart from the clock CL4.
k is selected and supplied to the status register 14. This allows the control state of the state register 14 to be transitioned from PO to Pl after the minimum unit time required for the above calculation has elapsed. Similarly, in state P1, X=OP1(BBUS, CI
When executing the operation R), CL2 also returns Y in state P2.
= OP2 (BBUS,
,Y.

CIR), all control states of the state register 140 are changed in synchronization with CL4.

As described above, in the present invention, the control circuit 15 synchronizes the transition of the control state that the control circuit 15 supplies to the state register 14 via the signal line 107 according to the contents of the state register 14 and the register 11, so that the clock signals CLI to CL4 are synchronized. The configuration is such that one is dynamically selected and supplied.

As a result, operations involving the bus require a signal indicating which operation is being executed since the data bus changes, while a signal indicating that a specific operation is being executed is sent to the status register 14. Despite being generated from the contents of the register 11 and the contents of the register 11, it is possible to execute multiple operations with different required times without waiting time because the control state transitions are performed at different appropriate time intervals. Become.

〔Effect of the invention〕

As described above, the present invention provides a logic circuit having an arithmetic unit having registers and an arithmetic circuit, and a control unit that controls arithmetic processing by these, as a signal that is synchronized with the state register of the control unit when the control state transitions. By configuring the system to dynamically select and supply one clock from a plurality of clocks, it is possible to execute a plurality of operations with different required times without waiting time, thereby realizing high-speed processing.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a time chart showing the operation of an embodiment of the present invention, FIG. 3 is a block diagram showing a conventional logic circuit, and FIG. 4 is a conventional logic circuit. 3 is a time chart showing the operation of the logic circuit of FIG. 10...
...Arithmetic unit, 11...Register, 12...
... Arithmetic circuit, 13... Control section, 14...
...Status register, 15...Control circuit, 10
1-107...Signal line, 111-114...
···Signal line. Agent: Susumu Uchihara, patent attorney, w+? I.J.
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Claims (1)

[Claims] an arithmetic unit having a register for storing data, arithmetic results, etc., and an arithmetic circuit for performing arithmetic processing on the contents of this register; a status register; and the contents of the status register;
a control unit having a control circuit that inputs the contents of the register and a plurality of clocks and supplies control signals to the register, the status register, and the arithmetic circuit, the control circuit inputting the contents of the register and the status register; 1. A logic circuit configured to dynamically select one of a plurality of clocks and supply it to the state register as a signal synchronized with a transition of a control state according to the content of the logic circuit.