JPH0415560B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention generally relates to charge-coupled devices (CCDs), and more particularly to series-parallel-
It concerns CCD memory using a serial (SPS) configuration.

A two-phase series-parallel-series charge-coupled device (SPS/CCD) memory is disclosed in U.S. Pat. No. 4,165,541 to Varshney, Venkateswaran, Amelio et al. The memory has a group of parallel shift registers, a serial input shift register at one end of the group, and a serial shift register at the other end of the group. Data is provided to the serial input register according to the rate of the two-phase clock signal, and when that register is full, a serial-to-parallel transfer operation is performed to load the data into the parallel shift register. Thus, data is transferred within the parallel shift register using ripple clocking techniques, and then a parallel-to-serial transfer operation is performed to load the data into the serial output shift register.

Such memories use conventional interlacing techniques, so that there is one parallel shift register for each element of the input or output serial shift register. By using a two-phase clock electrode structure for the input and output registers, charge is transferred to or from parallel registers with the correct phase, so that charge is transferred to or from alternating parallel registers. are transferred alternately. Traditionally, transferring charge from a parallel register to a serial output register required applying an intermediate voltage to the last storage gate. Such an intermediate voltage is such that the data in alternate parallel channels is transferred to the series gates at a high potential (i.e., φ ₁ or φ ₂ );
And data from other alternating parallel channels is transferred by virtue of the fact that the intermediate voltage applied to the last storage gate is higher than the potential of the series gate where we do not want charge transfer to occur. This is to ensure that the
In the conventional technology, not only does this require an intermediate voltage, but also the timing requirements are extremely high because the charge from the parallel registers is directly transferred and interlaced to the series registers that operate at high speed. It's tough.

The present invention has been made in view of the above points, and an object of the present invention is to provide an improved SPS/CCD memory.

According to one feature of the invention, the two-phase SPS/CCD memory array has means for transferring charge from the parallel registers to the serial output registers, the means for transferring charge being arranged in each of the first alternating parallel registers. a first transfer gate associated with each of the second alternating parallel registers, a first storage gate of the parallel registers associated with each first transfer gate, and a first storage gate of the parallel registers associated with each first transfer gate; a second storage gate of a parallel register associated with a transfer gate of and means for controlling the first transfer gate and the second transfer gate, wherein the charge from the first alternating parallel register is charge is transferred to the serial output register via a first storage gate, and charge from the second alternating parallel register is transferred to the serial output register via the second storage gate. It is something.

Another feature of the present invention is that the two-phase SPS
A method of transferring charge from a parallel register to a serial output register of a CCD memory array, the method comprising: (a) transferring charge from a first alternating parallel register to a first storage gate; (c) transferring charge from a second alternating parallel register to a second storage gate; and (d) transferring charge from the second storage gate to the serial output register. It is characterized by having each step of transferring charge to.

Another feature of the present invention is that two-phase series-
The parallel-series charge-coupled device array has charge transfer means, the charge transfer means comprising a first end-most storage element of the first parallel register and a second end-most storage element of the second parallel register. a first transfer element associated with the first end-most storage element; a second transfer element associated with the second end-most storage element; and a first transfer element associated with the first end-most storage element. a second intermediate storage element associated with said second transfer element; said first intermediate storage element and said second intermediate storage element;
a common storage element associated with intermediate storage elements of the common storage element, wherein the charge from the first endmost storage element passes through the first transfer element and the first intermediate storage element and the charge from the second most extreme storage element is transferred to the common storage element via the second transfer element and the second intermediate storage element.

Hereinafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings. Referring to the drawings, FIG. 1 is a schematic diagram showing the SPS/CCD array disclosed in US Pat. No. 4,165,541.
CCD memory array 10 is configured as a serial-parallel-serial memory, using interlacing to and from parallel registers, and using ripple clocking of parallel shift registers to increase bit storage capacity. ing.
The parallel shift register of the illustrated block has nine groups of eight electrodes to which ripple clock signals R ₁ , R ₂ , ..., R ₈ are applied, and each group carries 7 bits of information. It is possible to store. Serial input register 12 has 32 electrodes each associated with clock signals _.phi.1 and _.phi.2 , for a total of 64 electrodes.

In operation, data is provided to serial input shift register 12 driven by clock signals φ ₁ and φ ₂ . The data in this case is sequentially moved step by step through a serial shift register as in the case of a conventional two-phase CCD. When a bit is stored under every other electrode in the series shift register, a signal φ _T1 is applied to transfer the bits represented by the charge buckets stored under the series register electrodes. bit information is transferred to the input electrodes of every other parallel shift register 14. Subsequent data is then introduced into the serial shift register by applying signals φ ₁ and φ ₂ . Then, when data is stored below every other electrode in the serial input shift register that was not used in the previous transfer step, the signal φ _T1 is applied again to the bottom of these electrodes. Any charge present is transferred into the input elements of every other register that were not used in the previous step of the parallel shift register. When the input operation is completed as described above, the ripple clock signals R ₁ , R ₂ ,
..., R ₈ is applied to a group of elements of the parallel shift register so that data is transferred along the parallel register. When each input electrode of the parallel shift register is empty, new data from the input serial shift register is transferred and the above process is repeated.

By applying a ripple clock signal,
The 64-bit data in the parallel shift register is rippled. That is, within each group of eight electrodes of the parallel shift register, the blank potential well is moved backwards, so that as the blank potential well is moved backwards, data for each of the eight electrodes is moved backward. is transferred forward by one electrode.

The application of signal φ _T2 causes data to be transferred from the output electrodes of every other one of the 64 parallel shift registers to the corresponding alternating electrodes of the serial output shift registers. These data are then sent to the signal φ ₁
and φ ₂ are applied to the serial output register. Once the serial output register is empty, another transfer of data from the parallel shift register is initiated.

Additional gates 18 are provided to effect charge transfer from the alternating parallel registers 14 to the serial output registers 16. The signal Vc.c. applied to electrode 18 provides an intermediate voltage level between the high level of clock φ ₁ (or φ ₂ ) and the low level of clock φ ₂ (or φ ₁ ), thus Low level clock _φ2
(or φ ₁ ).

2A-2D illustratively illustrate charge transfer from parallel register 14 to serial output register 16 of the array of FIG. In FIG. 2A, the charge stored below the _Vcc electrode 18 of the parallel register, indicated by the symbol X, is aligned in a standby state for transfer. As shown in FIG. 2B, when clock φ ₁ is high and clock φ ₂ is low, the charge in the φ ₁ register is transferred to the transfer gate 2.
2 to the serial output register 16.
As mentioned above, the voltage V _cc on electrode 18 prevents the transfer of charge to the low φ ₂ electrode of output register 16.
Once the φ ₁ charge is removed from the output register, the φ ₂ charge that is under electrode 18 while clock φ ₂ is high and clock φ ₁ is low is then transferred to the series register, as shown in FIG. 2C. Transferred to 16.
As shown in FIG. 2D, the charge thus transferred is loaded into an output register, ready for transfer out of the array.

FIG. 3 shows an SPS system constructed based on the present invention.
This shows one example of a CCD array. This array is similar to the array of FIG. 1, and therefore the same reference numerals have been used for the same elements. In an embodiment of the invention, parallel register 1
The endmost electrodes 20 of the parallel registers 20 are linearly offset, i.e., the transfer gate 30 for transferring the charge from the φ ₁ column to the output register transfers the charge from the φ ₂ column of the parallel register to the output register 16. It is arranged closer to the output register than the transfer gate 32 for transfer. Transfer gate 30 is responsive to signal R _B while transfer gate 32 is responsive to signal R _A to transfer charge from the φ ₁ and φ ₂ columns via storage gate 34 and transfer gate 36, as described in more detail below. and selectively transferred to storage gate 37. Storage gate 34 is controlled by signal R _C and transfer gate 36 and storage gate 37 are controlled by signal R _D. Also, the transfer to the storage gate of the serial output register 16 is controlled by the serial gate φ ₁ . It is important to note that the interlacing from parallel registers to serial output registers is done by the extreme end electrodes of the parallel registers, not by the serial output registers. be. Furthermore, in the present invention, since the endmost electrodes 20 of the parallel registers are arranged in a staggered manner, there is no need for an intermediate voltage _Vcc . Furthermore,
Since charge transfer from storage electrode 37 to serial register 16 is performed in response to serial register _φ1 clock, timing requirements are relaxed.

4A to 4D schematically illustrate the state of charge transfer from the parallel registers to the serial output registers in the array shown in FIG. 3.
As shown in FIG. 4A, the charge in the φ ₁ column is below storage gate 34, while the charge in the φ ₂ column is below electrode 20, so that the charge in the φ ₁ parallel register is φ ₂ is offset from the charge in the register. As shown in FIG. 4B, the charge present in the φ ₁ column is transferred from storage gate 34 to the φ ₁ electrode of output register 16. When this charge is moved out of the output register, the charge in the φ ₂ column is transferred to the series register 16 via the storage electrode 37. On the other hand, it is also possible to transfer this charge to the φ ₂ electrode of resistor 16 by using a separate storage gate, but it is also possible to share storage gate 37, as described below with respect to FIG. Therefore, it is possible to transfer the charge to the φ ₁ electrode. After transferring the charge to register 16, the charge is removed from the output register by two-phase clocking, as shown in FIG. 4D. Importantly, in the present invention, the intermediate voltage _Vcc is removed and charge interlacing occurs in the slow transfer region of the parallel registers rather than the fast transfer region of the serial output register 16. . Furthermore, since the serial register _φ1 clock is used to perform charge transfer, the timing requirements for charge transfer to the serial output register are relaxed.

FIG. 5 shows in more detail a portion of the array of FIG. 3 according to an embodiment of the present invention, including the extreme end electrode 20 of the parallel register and the transfer gate electrode 30 of the φ ₁ channel. A transfer electrode 32, a storage electrode 34, a transfer electrode 36, and a storage electrode 37 of the φ ₂ channel are shown. Such a structure is covered by U.S. Patent No.
Similar to the semiconductor structure disclosed in US Pat. and serial output registers are indicated by diagonal lines 42. Transfer gates 30 and 32
are polysilicon electrodes provided on the respective barriers of the φ ₁ channel and the φ ₂ channel.
The storage electrode 34 is formed of polysilicon and is provided on the φ ₁ channel between the barrier 43 and the barrier 45, and on the φ ₂ channel between the barrier 44 and the barrier 45. is placed above. Storage gates 34 in the _φ1 and _φ2 columns
The charges from each are transferred to the serial output register 16 via separate transfer gates. However, in this embodiment, one storage gate 37
are used for two adjacent columns φ ₁ and φ ₂ , so that charges from these two columns are alternately transferred via storage gate 37 to the φ ₁ gate of the serial output register. Transfer gate 36 has a polysilicon electrode that includes polysilicon 48 overlying doped barrier 45;
Storage gate 37 comprises polysilicon overlying the charge storage region. The φ ₁ electrode of the series output register overlaps the barrier 52 between the storage gate 37 and the series resistor.

The detailed operation of the SPS/CCD array of the present invention is described in the 8th section.
6A to 6.
This will be explained with reference to the timing diagram shown in FIG. C and the schematic diagram of the adjacent _φ1 column and _φ2 column shown in FIG. As shown in FIG. 7, the two parallel rows of extreme electrodes 20 are controlled by a voltage R ₁ . Transfer gates 30 and 32 are controlled by voltages _RA and _RB , respectively. Storage gate 34 is controlled by voltage R _C and transfer gate 36 and storage gate 37 are controlled by voltage R _D. The charge is transferred into the gate of serial output register 16.

Next, referring to FIG. 6, the signals φ ₁ and φ ₂ for transferring charges in the series registers are equal to the ripple voltage R ₁ for transferring charges in the parallel registers.
to _R8 . In the figure, the control voltage R _A ,
R _B , R _C , and R _D are shown in appropriate time relationships with clock voltages φ ₁ and φ ₂ and ripple voltages R ₁ to R ₈ .

Next, referring to FIGS. 8 to 15, the explanation will be as follows:
In these figures, the respective times t ₁ to t ₁₂ (as shown in Figures 6A to 6C) for the transfer of charge from the parallel register to the serial output register are shown.
The state at FIG. 8 is at time t ₁ and charge is present below the extreme electrode of the parallel resistor. Figure 9 shows time t ₂ , t ₃ , t ₄
It indicates the state at which the control voltage R _B
and R _C , charge is shown being transferred from the φ ₁ channel to the storage gate 34 .

FIG. 10 shows the situation at time _t5 , in which storage gate 34 responds to control voltage R _D.
The state in which the charge present in the storage gate 37 is transferred via the transfer gate 36 to the storage gate 37 is shown. FIG. 11 shows the state in which charge is transferred from the parallel register to the serial output register at time _t6 in response to the serial register clock _φ1 . Figure 12 is time
The beginning of the condition in which charge is clocked out of the series register at _t7 is shown. FIG. 13 shows the situation at times t ₈ , t ₉ , and t ₁₀ as the charge in the serial output register is clocked out and the charge in the parallel register channel φ ₂ Charge is control voltage
The states transferred to storage gate 34 in response to R _A and R _C are shown. At time t ₁₁ , the charge in storage gate 34 is transferred to storage gate 37 and loaded into serial output register 16 in response to control voltage R _D . Finally, at time _t12 , the charge in storage gate 37 is transferred into series output register 16 in response to voltage _φ1 .

As described in detail above, according to the present invention, charges are interlaced at the end electrodes of the parallel registers, and the charges are transferred via a shared storage gate, so the conditions regarding the timing of charge transfer are relaxed. , eliminating the need to use intermediate voltages. Furthermore, the configuration of the present invention allows the CCD device to operate at lower voltages than those used in the prior art. Furthermore, it is important to note that transfers to the serial shift register are accomplished by using serial clock _φ1 .

Although the specific configuration of the present invention has been described in detail above, the present invention should not be limited to these specific examples, and various modifications can be made without departing from the technical scope of the present invention. Of course.

[Brief explanation of drawings]

Figure 1 is a schematic diagram showing a conventional SPS/CCD array, Figures 2A to 2D are explanatory diagrams showing states in which charge transfer is performed in the array shown in Figure 1, and Figure 3. is an SPS/CCD based on the present invention
A schematic diagram showing one embodiment of the array, FIGS. 4A to 4D are explanatory diagrams showing the state of charge transfer in the array shown in FIG. 3, and FIG. 5 is a schematic diagram showing one embodiment of the present invention. Schematic diagram showing in detail a part of the SPS/CCD array of FIG. 3 based on an example, FIGS. 6A to 6C
Figure 7 is a timing diagram showing the timing related to charge transfer within the array shown in Figure 3.
The figure is a schematic diagram showing the electrical connection state of two adjacent parallel channels of the SPS/CCD array shown in Fig. 5, and Figs. 8 to 15 are based on the timing diagram shown in Fig. 6. 6A and 6B are explanatory diagrams showing states of charge transfer to be performed; FIG. Explanation of symbols, 10... SPS/CCD memory array, 14... Parallel shift register, 16... Serial output register, 20... End electrode, 30, 3
2, 36... Transfer gate, 34, 37... Storage gate.

Claims (1)

[Claims] 1. In a two-phase SPS/CCD memory array,
Charge transfer means are provided for transferring charge from the parallel registers to the serial output registers, said charge transfer means comprising a first transfer gate associated with the alternating first parallel registers and a first transfer gate associated with the alternating second parallel registers. a second transfer gate associated with the first transfer gate; a first storage gate associated with the first transfer gate; a second storage gate associated with the second transfer gate; control means for controlling a transfer gate, wherein the charge from the first parallel register is transferred to the serial output register via the first storage gate and the charge from the second parallel register is transferred to the serial output register through the first storage gate; is transferred to the serial output register via the second storage gate, the first transfer gate and the second transfer gate are arranged linearly offset, and the first parallel resistor and the second parallel register from being simultaneously transferred. 2. According to claim 1, a third storage gate receives charge from the first storage gate and the second storage gate and transfers the charge to the serial output register. array. 3. The array of claim 2, wherein the third storage gate has a separate storage gate for each of the first storage gate and the second storage gate. . 4. In any one of claims 1 to 3, the third storage gate is connected to the first storage gate.
and a second storage gate, wherein charge from the first and second storage gates is alternately supplied to the third storage gate, and the charge from the first and second storage gates is alternately supplied to the third storage gate; An array characterized in that the means for controlling the gates is responsive to a serial register clock signal. 5. In a two-phase SPS/CCD array, a charge transfer means is provided, said charge transfer means connecting a first end storage element of a first parallel register and a second end storage element of a second parallel register. an end storage element; a first transfer element associated with the first end storage element; and a second transfer element associated with the second end storage element.
a transfer element, a first intermediate storage element associated with the first transfer element, a second intermediate storage element associated with the second transfer element, the first intermediate storage element and the second intermediate storage element; a common storage element associated with an intermediate storage element, wherein the charge from the first endmost storage element is transferred to the common storage element via the first transfer element and the first intermediate storage element. and the charge from the second most storage element is transferred to the common storage element via the second transfer element and the second intermediate storage element, and the charge from the second most storage element is transferred to the common storage element, and the second transfer element are arranged linearly offset to prevent simultaneous charge transfer from the first parallel register and the second parallel register. . 6. In claim 5, the common storage element is associated with a storage element of a serial output register, and wherein the common storage element is associated with a storage element of a serial output register, and the charge from the first edge-most storage element and the charge from the second edge-most storage element are charges are alternately transferred from the common storage element to the storage elements of the serial output register in response to a clock signal of the serial output register.