JPH04158552A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPH04158552A
JPH04158552A JP28405490A JP28405490A JPH04158552A JP H04158552 A JPH04158552 A JP H04158552A JP 28405490 A JP28405490 A JP 28405490A JP 28405490 A JP28405490 A JP 28405490A JP H04158552 A JPH04158552 A JP H04158552A
Authority
JP
Japan
Prior art keywords
silicon nitride
nitride film
film
semiconductor device
metal wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP28405490A
Other languages
Japanese (ja)
Inventor
Yukio Morozumi
幸男 両角
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Seiko Epson Corp
Original Assignee
Seiko Epson Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp filed Critical Seiko Epson Corp
Priority to JP28405490A priority Critical patent/JPH04158552A/en
Publication of JPH04158552A publication Critical patent/JPH04158552A/en
Pending legal-status Critical Current

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To improve humidity resistance and an effect of contamination resistance and to improve the reliability of a miniaturized semiconductor device by a method wherein a first silicon nitride film is formed, a spacer is formed on the side wall of a metal wiring by anisotropic etch back and then a second silicon nitride film is formed on the occasion when a protective insulation film is formed. CONSTITUTION:After metal wirings 14 and 15 are formed, a first silicon nitride film 16 is made to grow by bringing SiH4 and NH3 into a plasma reaction with N2, used as a carrier. Next, anisotropic etch back is applied by CF4, C2, F6 and 02, so that a spacer constituted of the silicon nitride film 16 is formed in the side wall parts of the metal wirings, and then a sintering process is executed. Next, a second silicon nitride film 17 is deposited by a plasma reaction and then subjected to sective dry etching, and thereby a bonding pad 19 for extraction of an external electrode is opened.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の製造方法に関し、特に保護絶縁
膜の形成に関する。
DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method for manufacturing a semiconductor device, and particularly to the formation of a protective insulating film.

〔従来の技術〕[Conventional technology]

従来、LSI等に用いる半導体装置の最終金属配線上の
保護絶縁膜は、物理的損傷、コンタミネーションや水分
の侵入を防ぐ為に、低温で気相成長したプラズマシリコ
ン窒化膜が用いられ、その厚みは8000A以上を要す
る。
Conventionally, the protective insulating film on the final metal wiring of semiconductor devices used in LSI etc. is a plasma silicon nitride film grown in a vapor phase at low temperature to prevent physical damage, contamination, and moisture intrusion. requires 8000A or more.

従来の半導体装置の製造方法は、例えば、第2図に示す
如く半導体素子が作り込まれたシリコン基板11上のフ
ィールド酸化膜12や層間絶縁膜13を介して、厚みが
1.0μm前後のA1合金膜14の金属配線上に、保護
膜として300〜400℃程度の低温で、SiH4とN
H8もしくはN2を導入したプラズマ反応によって、厚
みが1゜0μm程度のシリコン窒化膜17を気相成長さ
せ、その後パターニングしたフォトレジストをマスクに
、シリコン窒化膜17をCF4、C2FB、NFSや0
2等を用いた混合ガス等を用いて選択ドライエツチング
し、外部電極取り出し用のボンディングパッド19を開
孔して、場合によってはさらにモールド時のストレス緩
和の為に、ボリイミド樹脂等を積層する。
In the conventional method of manufacturing a semiconductor device, for example, as shown in FIG. SiH4 and N are applied as a protective film on the metal wiring of the alloy film 14 at a low temperature of about 300 to 400°C.
A silicon nitride film 17 with a thickness of about 1.0 μm is grown in a vapor phase by a plasma reaction introducing H8 or N2, and then, using a patterned photoresist as a mask, the silicon nitride film 17 is grown with CF4, C2FB, NFS, or 0.
Selective dry etching is performed using a mixed gas such as No. 2, etc. to open a bonding pad 19 for taking out an external electrode, and if necessary, a polyimide resin or the like is further laminated to relieve stress during molding.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

しかしながら従来技術では、LSIの様な半導体装置が
、サブミクロン程度に微細化されてくると金属配線のバ
ターニングはトライエツチング化され、断面形状が急峻
化されると共にアスペクト比(段差/スペース)が大き
くなる為、シリコン窒化膜17のカスピングによって、
金属配線のスペースにはスリット20か形成されコンタ
ミネーショントラップとなる上、金属配線の側壁部や底
面部及び四部コーナのシリコン窒化膜17が、金属配線
上に比較して極めて薄くなり、この領域から水分や汚染
が侵入することにより、トランジスタ特性やフィールド
反転耐圧の変動及びl配線の腐蝕等に関わる半導体装置
の長期信頼性が問題となっていた。単に、シリコン窒化
膜の厚みを大きくしても平坦部ボイドが形成されるだけ
で四部のシリコン窒化膜の厚みはほとんど変化なく信頼
性の向上はなされない。
However, with conventional technology, as semiconductor devices such as LSIs are miniaturized to the submicron level, the patterning of metal wiring becomes tri-etching, the cross-sectional shape becomes steeper, and the aspect ratio (steps/spaces) increases. Due to the large size, cusping of the silicon nitride film 17 causes
A slit 20 is formed in the space of the metal wiring, which becomes a contamination trap. In addition, the silicon nitride film 17 on the sidewalls, bottom surface, and four corners of the metal wiring is extremely thin compared to the top of the metal wiring, and the silicon nitride film 17 is formed in this area. The intrusion of moisture and contamination has caused problems in the long-term reliability of semiconductor devices, including fluctuations in transistor characteristics and field inversion breakdown voltage, and corrosion of l-wirings. Even if the thickness of the silicon nitride film is simply increased, voids are formed in the flat portion, and the thickness of the silicon nitride film in the four parts hardly changes, and reliability is not improved.

しかるに本発明はかかる問題点を解決するものて、保護
絶縁膜に関わる耐湿性や耐汚染効果を改善し、微細半導
体装置の信頼性の向上と安定供給を目的としたものであ
る。
However, the present invention solves these problems, and aims to improve the moisture resistance and anti-contamination effects of the protective insulating film, thereby improving the reliability and stable supply of fine semiconductor devices.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の半導体装置の製造方法は、半導体装置の最終金
属配線上に保護絶縁膜を形成するに当たり、少なくとも
、プラズマ反応による第1のシリコン窒化膜を形成する
工程、該シリコン窒化膜を異方性エッチバックして金属
配線の側壁にスペーサーを形成する工程、プラズマ反応
による第2のシリコン窒化膜を形成する工程、外部電極
取り出し用のボンディングパッドを開孔する工程を具備
したことを特徴とする。
The method for manufacturing a semiconductor device of the present invention includes at least the step of forming a first silicon nitride film by plasma reaction in forming a protective insulating film on the final metal wiring of the semiconductor device, and forming the silicon nitride film anisotropically. The method is characterized by comprising a step of etching back to form a spacer on the side wall of the metal wiring, a step of forming a second silicon nitride film by plasma reaction, and a step of opening a bonding pad for taking out an external electrode.

〔実 施 例〕〔Example〕

第1図は、本発明の半導体装置の製造方法の一実施例に
ついて説明する為の概略断面図てあり、SiゲートcM
Os−LSIの絶縁保護膜に適用した場合を示している
。シリコン基板11には、P及びNMO3)ランジスタ
、高抵抗等の半導体素子が形成され、フィールド絶縁膜
12や層間絶縁膜13を介して不純物層18等がらのコ
ンタクトホールを開孔し、Cuを約0. 5%を含んた
Ag合金膜14を約1. 0μmと、この上にキャップ
メタルとしてTiN膜15を600八積層スパッタリン
グしてから、フォトリソ工程で最小間隔が約0.8μm
にパターン形成し、フレオン系のガスとCF2系のガス
で該積層膜をドライエツチングして、はぼ垂直な側面形
状を持った金属配線(14,15)を形成した。続いて
ロードロック付き平行平板電極を持った気相成長装置で
、約360℃、N2をキャリアーとし6 torrの圧
力でSiH4とNH3をプラズマ反応させた第1のシリ
コン窒化1M116を0. 5μm成長させた。この時
、膜成長開始までの加熱時間は30秒、成長速度は0゜
7μm/分であり、全処理時間は4分以内としAlのヒ
ロックの成長を抑えた。次にCF4、C2、FBと02
で異方性エッチバックを施し金属配線の側壁部にシリコ
ン窒化膜16でなるスペーサーを形成してから、トラン
ジスタ等電気特性安定化の為450’C13%H2/A
r雰囲気中で30分間のシンター処理を施した(第1図
−a)。
FIG. 1 is a schematic cross-sectional view for explaining one embodiment of the method for manufacturing a semiconductor device of the present invention.
The case is shown in which it is applied to an insulating protective film of Os-LSI. Semiconductor elements such as P and NMO3) transistors and high resistance are formed on the silicon substrate 11, contact holes are formed in the impurity layer 18, etc. through the field insulating film 12 and the interlayer insulating film 13, and Cu is deposited approximately. 0. The Ag alloy film 14 containing 5% is about 1. After sputtering a TiN film 15 as a cap metal in 600 layers, the minimum spacing is approximately 0.8 μm using a photolithography process.
A pattern was formed, and the laminated film was dry etched using a Freon gas and a CF2 gas to form metal wirings (14, 15) having substantially vertical side surfaces. Next, in a vapor phase growth apparatus equipped with parallel plate electrodes with a load lock, the first silicon nitride 1M116 was grown at about 360° C. using N2 as a carrier and a plasma reaction of SiH4 and NH3 at a pressure of 6 torr. It was grown to 5 μm. At this time, the heating time until the start of film growth was 30 seconds, the growth rate was 0.7 μm/min, and the total treatment time was within 4 minutes to suppress the growth of Al hillocks. Next CF4, C2, FB and 02
After performing anisotropic etch-back to form a spacer made of silicon nitride film 16 on the side wall of the metal wiring, 450'C13%H2/A was applied to stabilize the electrical characteristics of the transistor etc.
A sintering process was performed for 30 minutes in a r atmosphere (Fig. 1-a).

この時A1合金膜14の上面はTiN膜15で、又側面
はシリコン窒化膜16のスペーサーで覆われており、微
細金属配線で問題となる横方向AIヒルロックの成長は
なく、配線間リークは発生しない。次に前記同様にプラ
ズマ反応させた第2のシリコン窒化膜17を約1.0μ
m積層させ、続いてバターニングされたフォトレジスト
をマスクにして、第2のシリコン窒化膜17を選択ドラ
イエツチングし、外部電極取り出し用のボンディングパ
ッド19を開孔した(第1図−b)。
At this time, the top surface of the A1 alloy film 14 is covered with a TiN film 15, and the side surface is covered with a spacer of a silicon nitride film 16, so there is no growth of lateral AI hillocks, which is a problem with fine metal interconnects, and leakage between interconnects occurs. do not. Next, the second silicon nitride film 17 subjected to the plasma reaction in the same manner as above is coated with a film of about 1.0 μm.
Then, using the patterned photoresist as a mask, the second silicon nitride film 17 was selectively dry etched to form a bonding pad 19 for taking out an external electrode (FIG. 1-b).

この様にしてなる半導体装置は、第2のシリコン窒化膜
17にカスピングがあっても四部のコーナーには第1の
シリコン窒化膜16でなる側壁スペーサーが形成されて
おり、実効的に膜厚が大きく耐湿性やコンタミネーショ
ンに対する遮蔽効果が向上し、従来の様なデバイスの信
頼性試験に於ける不良は激減した。又、シリコン窒化膜
のスリットやボイド形状も改善され、更に側壁スペーサ
ーの効果として、厚みが最小幅と同じかむしろ大きな傾
向にある金属配線のマイグレーション特性劣化や横方向
への物理的ストレスに対しての緩和作用も認められた。
In the semiconductor device constructed in this way, even if there is cusping in the second silicon nitride film 17, sidewall spacers made of the first silicon nitride film 16 are formed at the four corners, and the film thickness is effectively reduced. The moisture resistance and contamination shielding effect have been greatly improved, and the number of defects in conventional device reliability tests has been drastically reduced. In addition, the shape of slits and voids in the silicon nitride film has been improved, and the effect of the sidewall spacer is to prevent deterioration of the migration characteristics of metal wiring whose thickness tends to be equal to or even larger than the minimum width and physical stress in the lateral direction. A relaxing effect was also observed.

この他の実施例として、ポリシリコン等をレーサーで溶
断して収率を上げる冗長回路を持つLSIメモリーの製
造にも適用したが、ドライエツチングでほぼ垂直に側面
が形成された1、0μm厚みの19合金膜でなる金属配
線を施した後、この上に気相成長装置により400℃で
Si(OC2H5)4と02を反応させカスピングの少
ないシリコン窒化膜あるいはP (CH3)3を添加し
たリンガラス膜を後工程のプラズマシリコン窒化膜のス
トレスダメージ緩和の為約0. 3μm成長させてから
、450℃の3%H2/Ar雰囲気中で30分間シンタ
ー処理を行なったあと、初期電気特性を測定しレーザー
に依る修復処理を施した後、約360℃でSiH4とN
H3をプラズマ反応させた第1のシリコン窒化膜を0.
4μm成長させ異方性をエッチバックを施してから、次
に前記同様プラズマ反応させた第2のシリコン窒化膜を
約0、 8μm積層させた。更にバターニングされたフ
ォトレジストをマスクにして、第2のシリコン窒化膜と
シリコン酸化膜あるいはPSG膜をドライエツチングし
て、外部電極取り出し用のボンディングパッドを開孔し
た。尚、工程途中に於ける気相成長、エツチング処理の
プラズマ装置等から発生する電荷ダメージを消去する為
の紫外線照射処理を各工程間で施しである。以上の様に
してなる半導体装置は、前記実施例と同様な改善効果が
認められ信頼性向上が図れた。
As another example, we applied it to the manufacture of LSI memory with redundant circuits to increase the yield by melting polysilicon etc. with a laser. After applying metal wiring made of 19 alloy film, on this metal wiring, Si(OC2H5)4 and 02 are reacted at 400°C using a vapor phase growth apparatus to form a silicon nitride film with less cusping, or phosphorus glass added with P (CH3)3. To reduce stress damage to the plasma silicon nitride film in the subsequent process, the film is heated to about 0. After growing to a thickness of 3 μm, sintering was performed for 30 minutes in a 3% H2/Ar atmosphere at 450°C, the initial electrical characteristics were measured, and a laser repair process was performed. SiH4 and N
The first silicon nitride film produced by plasma reaction of H3 was heated to 0.
After growing to a thickness of 4 μm and etching back the anisotropy, a second silicon nitride film subjected to a plasma reaction in the same manner as described above was deposited to a thickness of about 0.8 μm. Furthermore, using the patterned photoresist as a mask, the second silicon nitride film and silicon oxide film or PSG film were dry-etched to form bonding pads for taking out external electrodes. Incidentally, ultraviolet irradiation treatment is performed between each step to erase charge damage generated from plasma equipment, etc. for vapor phase growth and etching treatment during the process. In the semiconductor device constructed as described above, the same improvement effect as in the above embodiment was observed, and the reliability was improved.

又本発明は、MOS−LSIに限らず、バイポーラ、D
MO3およびこれらを組み合わせたLSI等や多層配線
の半導体装置にも適用できる。金属配線としては、A1
1−Cuに限らずSi、Ti。
Furthermore, the present invention is applicable not only to MOS-LSI but also to bipolar, D
It can also be applied to MO3, LSIs, etc. that combine MO3, and semiconductor devices with multilayer wiring. For metal wiring, A1
1-Not limited to Cu, but also Si and Ti.

Pt5Mg等を含むものや、ヒロック、コンタクトバリ
ヤーの為にT i、WSP t、Mo等の高融点金属や
その窒化物、ケイ化物あるいはこれらの合金を上あるい
は下に積層構造としたもの、あるいはこの後にモールド
ストレス緩和の為にポリイミド樹脂等を積層したものに
も応用可能である。
Those containing Pt5Mg, etc., those with a laminated structure on top or bottom of high melting point metals such as Ti, WSP t, Mo, their nitrides, silicides, or their alloys for hillocks and contact barriers, or these It can also be applied to products laminated with polyimide resin or the like to alleviate mold stress later.

〔発明の効果〕〔Effect of the invention〕

以上本発明によれば、保護絶縁膜の構成をプラズマシリ
コン窒化膜の側壁スペーサーと更にシリコン窒化膜の積
層構造とし、微細化されたMOS−LSI等の半導体装
置に於ける保護絶縁膜自身の付き回り不具合を改善し、
耐湿性、耐汚染効果の向上や金属配線のヒロック発生を
防止し、電気特性を含めた長期信頼性に関わる品質改善
効果があり、より集積化、多機能化された半導体装置の
安定供給に寄与できるものである。
As described above, according to the present invention, the protective insulating film has a laminated structure of a sidewall spacer of a plasma silicon nitride film and a silicon nitride film, and the protective insulating film itself is formed in a semiconductor device such as a miniaturized MOS-LSI. Improved rotation problems,
It improves moisture resistance and contamination resistance, prevents the occurrence of hillocks in metal wiring, improves quality related to long-term reliability including electrical characteristics, and contributes to the stable supply of more integrated and multifunctional semiconductor devices. It is possible.

【図面の簡単な説明】 第1図は本発明による半導体装置の製造方法の実施例を
示す概略断面図である。 第2図は、従来の半導体装置の製造方法に係わる概略断
面図である。 11・・・シリコン基板 12・・・フィールド酸化膜 13・・・層間絶縁膜 14・・・Al1合金膜 15・・・TiN膜 16・・・第1のシリコン窒化膜 17・・・第2シリコン窒化膜 18・・・不純物層 19・・・ボンディングパッド 20雫・・スリット 以上 出願人 セイコーエプソン株式会社
BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic cross-sectional view showing an embodiment of a method for manufacturing a semiconductor device according to the present invention. FIG. 2 is a schematic cross-sectional view of a conventional method of manufacturing a semiconductor device. 11... Silicon substrate 12... Field oxide film 13... Interlayer insulating film 14... Al1 alloy film 15... TiN film 16... First silicon nitride film 17... Second silicon Nitride film 18... Impurity layer 19... Bonding pad 20 drops... Slit or more Applicant: Seiko Epson Corporation

Claims (1)

【特許請求の範囲】[Claims] 半導体装置の最終金属配線上に保護絶縁膜を形成するに
当たり、少なくとも、プラズマ反応による第1のシリコ
ン窒化膜を形成する工程、該シリコン窒化膜を異方性エ
ッチバックして金属配線の側壁にスペーサーを形成する
工程、プラズマ反応による第2のシリコン窒化膜を形成
する工程、外部電極取り出し用のボンディングパッドを
開孔する工程を具備したことを特徴とする半導体装置の
製造方法。
In forming a protective insulating film on the final metal wiring of a semiconductor device, at least a step of forming a first silicon nitride film by plasma reaction, and anisotropic etching back of the silicon nitride film to form a spacer on the side wall of the metal wiring are performed. 1. A method of manufacturing a semiconductor device, comprising the steps of: forming a second silicon nitride film by plasma reaction; and forming a bonding pad for taking out an external electrode.
JP28405490A 1990-10-22 1990-10-22 Manufacture of semiconductor device Pending JPH04158552A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP28405490A JPH04158552A (en) 1990-10-22 1990-10-22 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP28405490A JPH04158552A (en) 1990-10-22 1990-10-22 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPH04158552A true JPH04158552A (en) 1992-06-01

Family

ID=17673695

Family Applications (1)

Application Number Title Priority Date Filing Date
JP28405490A Pending JPH04158552A (en) 1990-10-22 1990-10-22 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPH04158552A (en)

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