JPH0415935A - Method of forming region for isolating semiconductor element from other - Google Patents

Abstract

PURPOSE:To perform easily a simplification of processes and a formation of a wide region for isolating semiconductor elements from others, by performing a lithographic process only once to form a resist pattern on a first insulation film, and by forming the region for isolating semiconductor elements from others through leaving second insulation films only on the sidewalls of grooves. CONSTITUTION:An oxide film 2 and a silicon nitride film 3 are deposited on the surface of a silicon substrate 1. Then, a resist pattern 4 is formed by an only once lithographic process. A working part 5A and an opening part 5B are specified. Then, after forming grooves 5A, 5B, the resist pattern 4 is removed, and a silicon oxide film 6 and a silicon nitride film 7 are deposited. A second insulation film is formed with both of them. Then, an anisotropic etching is performed, and the second insulation films are left only on the sidewalls of the grooves 5A, 5B. Then, the epitaxial growths of silicon crystals 8 are performed selectively only on the bottoms of the grooves 5A, 5B. Thereafter, by oxidizing only the surfaces of the silicon crystals 8 through a thermal oxidation method, silicon oxide films 9 are formed. Finally, the first insulation film is removed, and a series of the forming processes of the region for isolating semiconductor elements from others is completed.

Description

[Detailed description of the invention] [Industrial application field]

The present invention relates to a method for forming a semiconductor element isolation region that electrically isolates semiconductor elements constituting a semiconductor integrated circuit.

[Conventional technology]

The capacity of very large scale integrated circuits (Large Scale Integrated Circuits), such as DRAM (Dynamic Random Access Memory) and SRAM (Static Random Access Memory), is increasing at a rate of four times every three years. Currently, 256Kb and IMb DRAMs are mainly produced. In addition, intensive studies are underway on 4Mb and 16Mb, which will become mainstream in the future, and it is expected that they will further develop into 64Mb and 256Mb. This increase in integration within a limited chip area is
This has been brought about by the miniaturization of semiconductor elements that make up integrated circuits. For example, the minimum size of a MOS (Metal Oxide Semiconductor) transistor currently used in a 1Mb DRAM is approximately 1μ, and it is certain that it will be further miniaturized in the future to 0.5μra, 0.5μ, or 25μl. Similarly, reduction of the element isolation region is essential for higher integration, and it has become necessary to reduce the isolation width to less than 1μ, or even less than 05μ. Generally, a means called a selective oxidation method is used to form the element isolation process. In this method, a silicon nitride film covering a silicon substrate is patterned and opened, and the exposed silicon substrate surface is selectively oxidized to form a silicon oxide film, which is an insulating film. However, in this method, during selective oxidation, the oxidation of the silicon substrate progresses to the area covered with the silicon nitride film.
Because the solicon oxide film spreads, which is called a bird's beak, it is not possible to obtain a fine isolation region according to the mask size. In other words, with the selective oxidation method, there is a limit to the miniaturization of the element isolation region, and it is not possible to cope with future improvements in the degree of integration. Moreover, in order to obtain an oxide film with a certain thickness to obtain sufficient insulating properties, a long oxidation process is required, and the volume expansion due to oxidation places stress on the Noricon substrate, causing defects. There is also the problem that the device characteristics are deteriorated. As an element isolation method to replace the selective oxidation method which has such problems, a method called a trench-embedding isolation method has been proposed. This method involves digging a trench in a silicon substrate using a resist pattern formed by lithography as an etching mask, and filling the inside of the trench with an insulating film such as a silicon oxide film. Incidentally, each element constituting a semiconductor integrated circuit is arranged at a very high density within a limited chip area.
The element density within each chip is not constant but varies. Taking a 4Mb DRAM as an example, the separation distance between adjacent elements in the memory cell part is very fine, less than 1 μm, whereas in the peripheral circuit part it is several μm or even tens of μm.
There is a wide separation area. In the element isolation process, it is necessary to form isolation regions having various widths in the same process. FIG. 2 shows how a wide isolation region and a narrow isolation region are formed in the same process using the conventional trench filling isolation method. A conventional trench-filling isolation method will be explained with reference to FIG. ■ First, a resist pattern (not shown) is formed on the silicon substrate 21 by a lithography process, and this resist pattern is used as an etching mask to determine the shoulder width Wt.
A narrow groove 22 having a groove width W2 and a wide groove 23 having a groove width W2 are formed. Here, the groove width Wl of the narrow groove 22 is the minimum in the integrated circuit manufactured on the Noricon substrate 21, while the groove width W2 of the wide groove 23 is the maximum. Further, the depth of the grooves 22 and 23 is d, and the groove width W2 of the wide groove 23 is wider than twice the groove depth d (FIG. 2(a)). ■Next, a silicon oxide film 2 with a thickness t2 is deposited on the silicon substrate 21 by a vapor phase growth method (hereinafter referred to as CVD method).
4 (FIG. 2(b)). The silicon oxide film 24 is deposited on the side walls of the grooves 22 and 23 at almost the same speed as the silicon substrate 21 surface, so the narrow groove 2
2 is filled with a film thickness that is half the groove width Wl. On the other hand, in the case of the groove 23 which is larger than twice the groove width or the groove depth, it is necessary to deposit a silicon oxide film 24 having a thickness corresponding to at least the depth d of the groove to completely fill the groove. After all, the thickness of the silicon oxide film 24 required to simultaneously fill both grooves on the Noricon substrate 21 is required to be equal to or greater than the groove depth d. Also, the surface of the silicon oxide film 24 is relatively flat at the position of the narrow groove 22, or becomes less flat as the groove width becomes wider, and in the case of a wide groove 23, as shown in FIG. 2(b). In this case, a step having a height corresponding to the depth d of the groove is formed. (2) In order to eliminate the step difference, a resist pattern 25 is formed in the wide groove 23 by a lithography process. This is to prevent the silicon oxide film existing in the wide groove 23 from being removed in the step of removing the silicon oxide film 24 existing in the element region. Naturally, the film thickness t3 of the resist pattern 25 is approximately equal to the depth d of the groove, and its width W3 is less than or equal to the value obtained by subtracting twice the film thickness t2 of the Noricon oxide film 24 from the width W2 of the wide groove 23. Something is desired. After forming the resist pattern 25, a resist or other spin coating film 26 is formed thereon to flatten the surface (FIG. 2(C)). (2) Finally, the spin coating film 26, the resist 25, and the silicon oxide film 24 are etched at a constant speed until the silicon substrate surface 217 in the element region is exposed, thereby completing the element isolation process. In this way, in the trench-filling isolation method, only the region of the trench processed in the silicon substrate using the resist pattern formed in the lithography process as an etching mask becomes the isolation region, so it is possible to reduce the isolation width to the limit of lithography. Therefore, it is suitable as an element isolation method for semiconductor integrated circuits, which are becoming increasingly highly integrated.

[Problem to be solved by the invention]

However, in the conventional trench-filling element isolation method, in addition to the phosphorography process for defining the element isolation regions 22 and 23, a resist pattern 25 is formed to eliminate the step difference in the silicon oxide film 24 in the wide isolation region 23. There are several lithography steps, and a total of two lithography steps are required. Moreover, the latter lithography process
Second, strict mask alignment is required. In the manufacturing process of semiconductor integrated circuits, adding a lithography process not only increases the process time but also becomes a major factor in lowering the chip yield, ultimately leading to an increase in product cost.
It needs to be avoided as much as possible. Furthermore, in the narrow trench 22, the CVD silicon oxide films 24 grown from the sidewalls on both sides of the trench collide and accumulate at the center of the trench, so the film quality of the oxide film in the center of the trench is weak, and after the element isolation process. The oxide film at the center of the groove is removed by the hydrofluoric acid solution treatment, resulting in the formation of a slit. If there is a slit in the center of the groove as described above, there is a problem in that conductive material remains in the slit after wiring such as polycrystalline silicon for gates is processed, causing an electrical short circuit between adjacent wirings. Therefore, an object of the present invention is to shorten the first process time for forming an element isolation region, improve the reliability of a semiconductor integrated circuit, reduce manufacturing costs, etc. To provide a method for forming a semiconductor element isolation region using a trench filling isolation method that does not require any other lithography process, does not cause wiring short circuit even when the isolation width is narrow, and therefore provides high reliability. It is.

[Means to solve the problem]

In order to achieve the above object, the method for forming an element isolation region of the present invention includes forming a first insulating film on a semiconductor substrate, and then
Using a resist pattern formed by one lithography process as a mask, etching the first insulating film and the semiconductor substrate in a portion that will become an element isolation region;
A groove is formed in the semiconductor substrate, and then the resist pattern is removed and a second insulating film is formed on the inner wall of the groove and
2. The second insulating film is formed on the first insulating film, and then the entire surface is etched, so that the second insulating film is left only on the side walls of the trench, and the semiconductor substrate L is formed on the central part of the bottom of the trench. exposing the surface of the semiconductor substrate, and then selectively growing a Norikono crystal on the bottom surface of the groove where the surface of the semiconductor substrate is exposed;
Next, the surface of the grown Noricon crystal is oxidized to form an oxide film.

[Effect]

According to the method of the present invention, the lithography process performed to form the element isolation region forms a resist pattern defining the element isolation region on the first insulating film at the beginning of the element isolation region formation step. The lithography process is performed only once during the process, and no lithography process is performed in subsequent steps. Therefore, compared to the conventional trench-embedded device isolation method that requires two lithography steps, the process is not only simplified and process time reduced, but also the yield of chips is improved. Manufacturing costs are reduced. In addition, the second insulating film is left only on the sidewalls of the trench, a silicon crystal is grown therein, and only the surface of the silicon crystal is selectively oxidized to form an oxide film to form an element isolation region. Therefore, no matter how wide the element isolation region is to be formed, it can be handled simply by increasing the width dimension of the oxide film formation region by selective oxidation, which simplifies the process compared to conventional methods. It is possible to easily form a wide separation area. On the other hand, in narrow grooves, the oxide film is not deposited at the center of the groove while colliding with each other as in the conventional method, so even if treatment with hydrofluoric acid solution etc. is applied, a slit will not be formed in the center of the groove. There isn't. Further, since the second insulating film defining the peripheral portion of the element isolation region is formed on the sidewall of the groove formed by the lithography process, the element isolation region can be formed faithfully to the resist mask size. Furthermore, the oxide film that needs to be formed in the center of the element isolation region by selective oxidation is only on the surface of the grown silicon crystal; There is no need to make the oxide film extremely thick, and the occurrence of defects due to volumetric expansion due to oxidation is also suppressed, thereby improving device characteristics.

【Example】

Hereinafter, the present invention will be explained in detail with reference to illustrated embodiments. FIGS. 1(a) to 1(g) are process diagrams illustrating an embodiment of the method for forming an isolation region of the present invention, in which isolation regions having different widths are simultaneously formed on the same substrate by a common process. It shows how it goes. In addition, each process (a) to (g) explained below corresponds to (a) to (g) in FIG. 1, respectively.
It corresponds to (a) First, the surface of a common silicon substrate l is thinly oxidized to form a silicon oxide film 2 with a thickness of 100 to 500, and then a silicon nitride film 3 of 10 to 100 nm is formed by low pressure CVD.
00-3000 people will accumulate. This silicon oxide film 2 and silicon nitride film 3 form a first insulating film. continue,
The isolation region is defined and a cyst pattern 4 is formed by one photolithography process. In this resist pattern 4, a sandwiched element isolation region is defined by the opening 5A, and a wide element isolation region is defined by the opening v5B, only a portion of which is shown. Note that a semiconductor element will be formed on the surface of the silicon substrate in the region covered with the resist 4. (b) Next, using the resist pattern 4 as an etching mask, the silicon nitride film 3, the silicon oxide film 2, and the silicon substrate I are anisotropically etched by a reactive ion etching (RrE) method, so that the silicon substrate 1 is etched to a depth. Groove 5A of 0.3-2.0 μm. 5B (for convenience, the same numbers as those indicating the openings of the resist pattern 4 are used) are formed. In the etching process in this step, the silicon substrate I can be etched all at once, so the etching can be easily controlled. Groove 5A
, 5B, the resist pattern 4 is removed. 1st
Figure (b) shows the state after the resist pattern 4 has been removed. (c) Next, the exposed parts of the silicon substrate l that form the inner walls of the grooves 5A and 5B are oxidized to form a thin silicon oxide film 6 of about 100 to 300 layers, and then a silicon nitride film is formed on the entire surface. 7 is deposited thinly by low pressure CVD method. The silicon oxide film 6 and the silicon nitride film 7 form a second insulating film. (d) Next, the Noricon nitride film 7 and the Noricon oxide film 6 are anisotropically etched using the RrE method until the silicon substrate 1 is exposed. As a result, as shown in Figure (d), the silicon oxide film 6 and the silicon nitride film 7, which are the second insulating films, remain only on the side walls of the trenches 5A and 5B, and the R5A
, 5B, the Noricon board 1 is exposed on the bottom surface. (e) Next, a silicon crystal 8 is selectively grown epitaxially only on the bottom surface of the exposed groove 5A5B of the silicon substrate I using a hydrochloric acid-based growth gas. The growth of the Noricon crystal 8 is such that the height of the surface of the Noricon crystal 8 after growth is covered with the silicon oxide film 2 and the Noricon nitride film 3 on the unprocessed silicon substrate 1.
It is desirable to do this so that the height is approximately the same as the zero surface (see FIG. 1(e)). This is because if the height of the surface of the grown Noricon crystal 8 is significantly different from the height of the surface of the unprocessed Noricon substrate 1, there will be a large gap between the active region and the element isolation characteristics after the element isolation region is completed. This is because there will be a difference in level. Note that since the region where the silicon crystal 8 is grown becomes part of the element isolation region and no semiconductor element is formed therein, it does not matter whether the silicon crystal 8 contains crystal defects or is polycrystalline. (f) Next, the silicon substrate 1 is oxidized by a thermal oxidation method. At this time, the portion covered with the silicon nitride film 3.7 is not oxidized, but only the surface of the silicon crystal 8 is oxidized, and a silicon oxide film 9 is formed as shown in FIG. 1(f). Oxidation of the silicon crystal 8 does not proceed outside the trenches thanks to the silicon nitride film 7 formed on the sidewalls of each of the trenches 5A and 5B, so the device isolation region is enlarged due to bird's beaks that are observed when forming the device isolation region by selective oxidation. doesn't happen. Note that the grooves 5A and 5B mainly determine the element isolation characteristics.
Since the silicon oxide film 6 and the silicon nitride film 7 are the second insulating films formed on both side walls of the It is sufficient because it is very thin compared to the film thickness. Therefore, the oxidation time is short and the volumetric expansion caused by oxidation can be suppressed as much as possible, so the stress applied to the silicon substrate is reduced, the generation of crystal defects is suppressed, and device characteristics such as junction leakage current are improved. I can do it. (g) Finally, the silicon nitride film 3 and silicon oxide film 2 covering the element region are removed using hot phosphoric acid and dilute hydrofluoric acid solution, respectively, to complete the series of steps for forming the element isolation region. FIG. 1(g) shows the cross-sectional shapes of the narrow element isolation region and the wide element isolation region obtained by the series of steps described above (only a portion of the wide element isolation region is shown). In this way, if an element isolation region is formed using this method, a wide element isolation area and a narrow element isolation area can be formed in the same process in a very simple process and in a short time compared to the conventional trench-buried element isolation method. If it can be formed in accordance with the design process, it will be possible to reduce the element isolation region to the limit of lithography, and it will be possible to fully respond to the further miniaturization of integrated circuits in the future. When the formation of the element isolation region is completed through the above steps, elements such as MOS (MOS) lannostar and capanostar are constructed in the active region of the silicon substrate l according to the usual method, and a semiconductor integrated circuit having the element isolation region is completed. . The characteristics of the MoS transistor thus formed were measured. As a result, it was found that the transistor had characteristics comparable to those of transistors of the same size separated by selective oxidation. In particular, the silicon oxide film 9, which is an insulating film in the center of the isolation region, is very thin compared to an oxide film formed by selective oxidation, so the stress on the silicon substrate 1 due to volumetric expansion is weak. , the reverse leakage current of the junction was suppressed to an extremely low value. In addition, regarding the parasitic MOS (transistor) transistor that is inevitably formed between adjacent elements, its field inversion voltage and field punch lumen voltage are more than twice the power supply voltage, which is excellent despite the extremely narrow separation width of 0.5 μm. characteristics were obtained. In this embodiment, the Noricon crystal 8 may be epitaxially/dial-grown single crystal Noricon, or may be polycrystalline silicon. It should be noted that the present invention relates to a method for forming a semiconductor element isolation region, and materials, means, numerical values, etc. are not limited to those related to this embodiment, except as specified in the claims. .

【Effect of the invention】

As is clear from the above, according to the method for forming a semiconductor element isolation region of the present invention, a semiconductor element isolation region can be formed on a semiconductor substrate by a phosphorography process. A second insulating film is left only on the side walls of the trench thus formed, silicon crystals are selectively grown on the semiconductor substrate surface exposed at the bottom of the trench, and only the surface of the grown silicon crystal is selectively oxidized. An oxide film is formed, and the region surrounded by this oxide film and the second insulating film around the oxide film is used as the element isolation region, so the one-note rough-cut process is performed throughout the entire process to form the trenches that define the isolation region. It will only be used once. In addition, the phosphorography process that involves strict mask alignment to planarize a wide isolation region, which is required in the conventional trench-buried element isolation method, is no longer required, which reduces the number of steps required to fabricate a semiconductor integrated circuit. The time required for this method can be significantly reduced compared to the conventional trench-embedded device isolation method, and the yield of chips can be improved to significantly reduce manufacturing costs. In addition, according to the present invention, it is possible to handle from an extremely fine element isolation region that is the limit of lithography to a sufficiently wide element isolation region, and it is possible to handle any size and shape of the element isolation region by lithography. The resist pattern can be formed faithfully to the resist pattern formed by the process. Therefore, pattern shifts and other complicated restrictions are eliminated, making circuit layout easier and contributing greatly to miniaturization of semiconductor integrated circuits. Also, unlike the conventional trench-filling isolation method, the trench is not filled with only the oxide film grown from the sidewalls.
Even if hydrofluoric acid solution treatment is performed after the element isolation process, no slits are formed in the bundle in the groove, so there is no problem of electrical shorts between adjacent wirings due to the presence of slits, and high reliability can be achieved. can. In addition, since the thickness of the oxide film formed by the selective oxidation process according to the present invention does not need to be increased, the oxidation process time can be shortened, and the stress on the semiconductor substrate caused by volume expansion can be reduced, resulting in crystal defects. Because it is possible to avoid the occurrence of
Good device characteristics can be obtained.

[Brief explanation of drawings]

FIG. 1 is a diagram showing each process for forming an element isolation region on a semiconductor substrate according to an embodiment of the present invention, and FIG. 2 is a diagram illustrating problems of the conventional trench-embedded element isolation method. . 1... Silicon substrate, 2... Thin Norikun oxide film, 3... Silicon nitride film, 4 Resist pattern defining element isolation region, 5 A
, 5 B-R (opening of resist pattern), 6.
Silicon oxide film formed by oxidizing the inside of the trench, 7. Silicon nitride film, 8. Norifun crystal selectively grown on the silicon substrate surface exposed at the bottom of the trench, 9. Noricon crystal surface with elongated length. A silicon oxide film formed by oxidizing F;

Claims (1)

[Claims] (1) Form a first insulating film on a semiconductor substrate, and then
Using the resist pattern formed in the lithography process as a mask, the first insulating film and the semiconductor substrate existing in the element isolation region are etched to form a groove in the semiconductor substrate. The pattern is removed and a second insulating film is formed on the inner wall of the groove and the first insulating film, and then etching is performed on the entire surface, so that the second insulating film is formed only on the side walls of the groove. , and expose the surface of the semiconductor substrate at the center of the bottom of the groove. Next, selectively grow silicon crystals on the bottom of the groove where the semiconductor substrate surface is exposed. 1. A method for forming a semiconductor element isolation region, the method comprising forming an oxide film by oxidizing a surface of a silicon crystal.