JPH04159691A - Synchronous type semiconductor memory - Google Patents

Abstract

PURPOSE:To perform an optimum write/read cycle time with small number of synchronous signals by controlling a frequency converter by a signal for controlling writing and reading operations. CONSTITUTION:Input signal holding circuits 2 - 5 and an output signal holding circuit 6 are composed of D-type FF circuits, and controlled by internal synchro nous signals CLKI, -CLKI from selectors 7, 8. With the CLKI, -CLKI, a synchro nous signal CLKA or -CLKA delayed in the same phase at an external clock CLK by a gate circuit 10 and frequency division output CLKB or -CLKB of a frequency converter 9 are selected by the selector 7 or 8. With the configura tion, the signal CLKA or -CLKA of one cycle of the external block signal is used for reading, and the signal CLKB or -CLKB corresponding to two cycles is used for writing. Thus, optimum reading/writing is performed by one type of the synchronous signal.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a synchronous semiconductor memory device, and more particularly to a synchronous semiconductor memory device that converts the frequency of a synchronous signal.

[Conventional technology]

Such a conventional synchronous semiconductor memory device has RA and M circuit blocks, and an input signal holding circuit and an output signal holding circuit provided on the input/output side, and the input signal holding circuit and the pressure signal holding circuit are controlled by a synchronizing signal. Controls the circuit into a data retention state or data through state. For example, when the synchronization signal is at a high level, the input signal holding circuit is in a data holding state and the output signal holding circuit is in a data through state, and when it is at a low level, the opposite operation is performed.

FIG. 4 is a block diagram of a synchronous semiconductor memory device showing an example of such a conventional semiconductor memory device.

As shown in FIG. 4, this storage device includes a RAM circuit block 1 composed of memory cells, an address signal terminal Add for this RAM circuit block 1, write enable signal terminals WE and C3 signal terminals, and input data. Input signal holding circuits 2 to 5 that hold signals and data from terminal Dos, output data holding circuit 6 that holds data output from RAM circuit block 1 to pressure terminal OUT, and clock (synchronous signal) from terminal CLK. Input external synchronization signal, in-phase and delayed internal synchronization signal C
It has a gate circuit lO that outputs LKA and an internal synchronization signal CLKA which is an inverted version of the internal synchronization signal CLKA clock.

The cycle time that influences the operation of such a synchronous semiconductor memory device is determined by the slower read cycle and write cycle.

[Problem to be solved by the invention]

The above-described conventional synchronous semiconductor memory device has a drawback in that, in a circuit that performs a fast read operation and a slow write operation, the write cycle time becomes the read cycle time, making it impossible to take advantage of the high speed of the read operation. Another disadvantage is that in order to take advantage of the high speed, it is necessary to prepare two synchronizing signals, such as a fast cycle time for reading and a slow cycle time for writing.

SUMMARY OF THE INVENTION An object of the present invention is to provide a synchronous semiconductor memory device that achieves optimal write cycle time or read cycle time using a small number of synchronization signals.

Means for Solving the Problem] A synchronous semiconductor memory device of the present invention includes a synchronous signal terminal,
An input signal holding circuit and an output signal holding circuit that perform a data holding operation in synchronization with a synchronization signal, a signal terminal that controls write and read operations, and a signal terminal that controls the write and read operations and that is controlled by the signal that controls the frequency of the synchronization signal. and a frequency conversion circuit that converts the frequency.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a synchronous semiconductor memory device showing a first embodiment of the present invention.

As shown in FIG. 1, this embodiment includes a normal RAM circuit 1, input signal holding circuits 2 to 5, output signal holding circuit 6,
Selectors 7 and 8 for selecting these input signal holding circuits 2 to 5 and output signal holding circuit 6;
．． a frequency conversion circuit 9 using a frequency dividing circuit that supplies an internal synchronization signal of opposite phase to the external synchronization signal CLK; and a gate circuit that creates an internal synchronization signal CLKA that is in phase and delayed from the external synchronization signal CLK, and an internal synchronization signal CLKA that is inverted therefrom. 10. Further, the input signal holding circuits 2 to 5 and the output signal holding circuit 6 are configured with, for example, D-type flip-flops, and the internal synchronization signal CLKI from the selector 7.8 is
, CLKI, respectively. This internal synchronization signal CLKI.

CLKI is generated from an external synchronization signal CLK.

That is, the gate circuit 10 selects the in-phase (same frequency) and delayed synchronization signal CLKA of the external clock CLK or the inverted synchronization signal CLKA and the frequency-divided output CLKB of the frequency conversion circuit 9 or the inverted synchronization signal CLKB by the selector 7 or Select with 8. Which of the internal synchronization signals CLKI and CLKI is selected is determined by the write enable signal WE°. For example, since the frequency conversion circuit 9 is composed of a frequency dividing circuit, the external I[signal cL
K is input at the same frequency as the read cycle. Also,
Since the write cycle is slower than the read cycle, it is necessary to double the cycle through a frequency divider circuit.

FIG. 2 is a waveform diagram of an internal synchronization signal obtained from an external synchronization signal using a frequency dividing circuit as the frequency conversion circuit in FIG.

As shown in FIG. 2, for reading, the synchronizing signal CLKA or CLKA corresponding to one cycle of the external synchronizing signal is used, and for writing, the synchronizing signal CLKB or CLKB corresponding to two cycles is used. These two selections are based on the write enable signal WE°.
Selectors 7 and 8 are performed.

FIG. 3 is a waveform diagram of an internal synchronization signal obtained from an external synchronization signal when a multiplier circuit is used as a frequency conversion circuit for explaining a second embodiment of the present invention.

As shown in FIG. 3, the hardware configuration of this embodiment is the same except that the frequency conversion circuit 9 of FIG. 1 is replaced with a multiplier circuit. In this embodiment, reading is performed in 1/2 cycle of external synchronizing signal CLK, and writing is performed in 1 cycle. still,
Selection of read and write cycles is performed by write signal WE in the same manner as in the first embodiment described above.

[Effects of the Invention] As explained above, the synchronous semiconductor memory device of the present invention, which has different read cycles and write cycles, is equipped with a selector that switches between the frequency conversion circuit and the input/output holding circuit of the synchronous signal. This has the effect that an optimal read or write cycle can be realized using a synchronization signal.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a synchronous semiconductor memory device showing a first embodiment of the present invention, and FIG. 2 is a block diagram of an internal synchronization signal obtained from an external synchronization signal using a frequency dividing circuit in the frequency conversion circuit in FIG. 3 is a waveform diagram of an internal synchronization signal obtained from an external synchronization signal when a multiplier circuit is used as a frequency conversion circuit for explaining the second embodiment of the present invention, and FIG. 4 is a waveform diagram of an internal synchronization signal obtained from an external synchronization signal. FIG. 1 is a block diagram of a synchronous semiconductor memory device showing an example. 1...RAM circuit block, 2-5...
Input signal holding circuit, 6... Output signal holding circuit, 7,
8... Selector, 9... Frequency conversion circuit, 10
...Gate circuit. Agent Patent Attorney Shinya Uchihara 2 Figure

Claims (1)

[Claims] 1. A synchronous signal terminal, an input signal holding circuit and an output signal holding circuit that perform data holding operations in synchronization with the synchronous signal,
A synchronous semiconductor memory device comprising: a signal terminal for controlling write and read operations; and a frequency conversion circuit that is controlled by a signal for controlling write and read operations and converts the frequency of the synchronization signal. 2. The synchronous semiconductor memory device according to claim 1, wherein the frequency conversion circuit is a multiplier circuit. 3. The synchronous semiconductor memory device according to claim 1, wherein the frequency conversion circuit is a frequency dividing circuit.