JPH04162473A - semiconductor storage device - Google Patents

Abstract

PURPOSE:To obtain a memory cell having a high software error resistance without increasing memory cell area by forming a load and drive transistor with single crystal semiconductor layer or polycrystalline semiconductor layer of two or more layers and predetermining a resistance value of one or both gate electrodes of a couple of drive transistors and load transistors. CONSTITUTION:A transfer transistor is formed within a P-type well 15 provided within an N-type substrate 37 with N-type high concentration impurity regions 5a, 5b (drain electrode, source electrode) and a first layer polysilicon film 6 (gate electrode). Moreover, a gate electrode 14b is formed by a second layer polysilicon film on an oxide film 11 provided on a gate electrode 4b (first layer polysilicon layer) of a drive MOS transistor. A load transistor consisting of polysilicon layer is formed by providing drain electrode 8, source electrode 18 and channel part 17 with a third layer polysilicon film. In this case, a resistance value of the gate electrode 14b is set to 10KOMEGA or more by not executing or executing a small amount of ion implantation to a part or to the entire part of the gate electrode 14b of the load transistor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a highly integrated static random access memory device with excellent soft error resistance.

[Conventional technology]

The conventional device is IEE Transaction on Nuclear Science NS-32.
(1985) pp. 4133-4139 (IEE
E, trans, Nuc, NS-32 (1985
) PP4133-4139, and as shown in FIG. T8 is a p-channel MOS transistor formed on the surface of the substrate, and is a complete CMOS static memory cell, and a resistor is provided between the storage node N1 and the gate electrode of the transistor T8, and between the storage node N2 and the gate electrode of the transistor T7. There is.

In addition, IEEE Electron Device Letters ED-L8 (1987) pages 7 to 9 (IEEE Elec Dev Lett
A similar device is also stored in EDL 8 (1987) PP7-9).

[Problem to be solved by the invention]

The above-mentioned conventional technology does not take into consideration high integration, and if both the load transistor and the drive transistor are formed on a semiconductor substrate, the gap between the storage node and the gate electrode of the load transistor.

Alternatively, when a resistor is provided between the storage node and the gate electrode of the drive transistor, there is a problem that the area of the memory cell increases.

According to the present invention, a resistance can be provided by increasing the resistance values of the gate electrodes of the load transistor and the drive transistor, so a memory cell with high soft error resistance can be provided without increasing the memory cell area.

[Means to solve the problem]

The above object is to provide a static memory cell formed by cross-connecting two sets of inverters each consisting of a load transistor and a drive transistor, a single crystal semiconductor layer of 2J￥0 or more;
Alternatively, the load and the drive transistor are formed using a polycrystalline core layer, and the resistance value of the gate electrode of one or both of the two drive transistors and the load transistor is set to 10Ω or more, more preferably 20Ω or more. This is achieved by setting the above.

[Effect]

Of the two storage nodes of the static memory cell,
α rays are incident on the first storage node which is in a high potential state, and the first
When the potential of the storage node decreases, a resistor is interposed between the first storage node and the gate electrode of the second load transistor whose drain electrode is connected to the second storage node that is in a low potential state. Therefore, the gate potential of the second load transistor does not drop immediately, and therefore the second
The current in the load transistor does not increase immediately, and information is not reversed as easily compared to a case without a resistor, making it possible to realize a memory cell with high soft error resistance.

Further, when a resistor is interposed between the gate electrode of the second drive transistor whose drain electrode is connected to the first storage node in the high potential state and the second storage node in the low potential state, , when α rays are incident on the first storage node and the potential drops, the gate potential of the second drive transistor does not drop immediately, and the time during which the second drive transistor becomes non-conductive is longer than in the case where there is no resistance. becomes long and the rise in the potential of the second storage node is delayed, so that the information held in the memory cell does not easily invert, and a memory cell with high soft error resistance can be realized.

〔Example〕

An embodiment of the modified invention is shown in FIGS. 1(a) to 1(c). (,
) shows a plan view, (b) a cross-sectional view, and (c) a circuit diagram.

In FIG. 1(b), a p
In the type well 15, n-type high concentration impurity regions 5a, 5b (
A transfer transistor is formed by the drain electrode, source electrode) and the first layer polysilicon film 6 (gate electrode), and the oxide film 11 provided on the gate electrode 4b (first layer polysilicon layer) of the drive MO3 transistor. A gate electrode 14b is formed on the second layer polysilicon film, and a drain electrode 8.b is formed on the third layer polysilicon film. Source electrode 18.
By providing the channel portion 17, a load transistor made of a polysilicon layer is formed.

Further, the drain electrode 5b of the transfer transistor is connected via the polysilicon pad 9 and the first layer metal wiring 12.
Furthermore, it is connected to the second layer metal wiring 13. At this time, by not implanting a part or the entire gate electrode 14b of the load transistor, or by implanting a small amount, the resistance value of the goo 1-electrode 14b can be reduced to 30
KΩ or more.

The plan view at this time is shown in FIG. 1(a), and this plan view A-
A cross-sectional view of A' is shown in FIG. 1(b). Also, the circuit diagram is the first
Shown in Figure (c). In the plan view shown in FIG. 1(a), the shaded area in the gate electrode of the polysilicon pMOS transistor is a region where no implantation is performed or where a small amount of implantation is performed. In FIG. 1(c), the drain electrode of the first drive transistor T1 and the first load transistor T5 are connected to each other.
are connected to form a first storage node. Similarly, the drain electrode of the second drive transistor T2 and the drain electrode of the second load transistor T6 are connected to form a second storage node. Furthermore, the storage node Nl.

“Write” information to N2, and also write information to storage node N2.
1, transfer nMO8) for "reading" information stored in N2 - transistor T3. T4 is provided. The above flip-flop circuit has a positive power supply voltage ■
CC and ground potential are supplied, and the data lines 1 and 2 are connected to the transfer MOS transistors T3 and T4, and the goo1 electrode of T3 and T4 is connected to the word line 3. configured. Such a static random access memory operates by setting the word line 3 to a high potential to transfer data from transfer Mo5t to transistor T3. T
4 is made conductive, and from data lines 1 and 2, "Ql', tLI
IT information is stored in storage nodes Nl and N2, and information in storage nodes Nu and N2 is read out to data lines 1 and 2. In the circuit shown in Figure 4(b), storage node N1
When N2 is in a high potential state and N2 is in a low potential state, when α rays enter the memory cell and electrons are collected at the storage node N1, the potential of the storage node N1 decreases, and the poly 2932PM
Since the gate potential of the OS transistor T6 decreases and the current flowing through 16 increases, the potential of the storage node N2 increases by ten. As the potential of the storage node N2 rises, the gate potential of the polysilicon 2MO8 transistor T5 rises, so the current flowing through T5 decreases, and the rise in the potential of the storage node N1 by 1 is delayed. As a result, the storage node N1 becomes a low potential state and the storage node N2 becomes a high potential state, resulting in a so-called rough 1-error. By adopting a circuit configuration as shown in FIG. 1(C), which is an embodiment of the present invention, α rays are incident and electrons are collected at the storage node N1, thereby reducing the potential of the storage node N1. At this time, the gate potential of the polysilicon pMOS transistor T6 decreases exponentially due to a time constant determined by the resistor R3 and the gate capacitance of T6.

Therefore, the current flowing through T6 does not increase immediately, and the potential of storage node N2 does not increase immediately.

On the other hand, the poly 29 connected to the storage node N2
The gate potential of the 32PMOS transistor T5 does not change because the potential of the storage node N2 connected thereto is at the ground potential, so the current flowing through T5 does not decrease.

As a result, the potential of the storage node N1 is restored to a high potential again, the potential of the storage node N2 is held at the ground potential, and no soft error occurs. FIG. 2 shows another embodiment of the invention.

Increasing the resistance of the gate electrode of the polysilicon PMOS transistor is the same as in the embodiment shown in FIG.
In this embodiment, the second layer polysilicon layer 14 was implanted using conventional implantation. By forming a double structure in which a third layer polysilicon layer 9a is laminated on top of b with no implantation or with a small amount of implantation, the resistance value of the gate electrode is increased and the gate of the polysilicon pMos+- transistor is A resistive element can be provided between the electrode and the storage node.

FIG. 3 shows another embodiment.

In the embodiment not shown in FIGS. 1 and 2, the gate electrode of the polysilicon two-open OS transistor has a high resistance, whereas the third embodiment
The embodiment shown in the figure is a case where a resistance element is provided between the gate electrode of the drive transistor and the storage node. Figure 3(c)
, when α rays are incident on the memory cell and the potential of the storage node N1, which is in a high potential state, decreases, the storage node N1
If a resistor is interposed between the gate electrode of the drive transistor T2 and the gate electrode of the drive transistor T2, T2 will not immediately become non-conductive, and therefore the potential of the storage node N2 will not rise immediately. From this point of view, between the storage node N1 and the gate electrode of the drive transistor T2, between the storage node N2 and the drive transistor T1
Even when a resistor is provided between the gate electrodes of each gate electrode, the strength of soft error resistance is also increased.

The plan view at this time is shown in Figure 3 (,), and the cross-sectional view is shown in Figure 3 (b).
). Resistors R2 and R4 in the figure are made by increasing the resistance of the gate electrodes 4a and 4b of the drive transistor by not performing implantation or by performing a small amount of implantation.
Between the gate electrodes of storage nodes N1 and T2, storage node N2
A resistance element is provided between the gate electrodes of T1 and T1. Figure 3 (a
).

The shaded area within 26 in (b) is an area where no implantation is performed or where a small amount of implantation is performed. FIG. 5 shows the calculation results of the resistance value dependence of the critical charge amount at which a soft error occurs. From this figure, when resistors R1 and R3 are provided between the gate electrode of the polysilicon 2-open OS transistor and the storage node, the critical charge increases rapidly when the resistance value exceeds 20 Ω, and the gate electrode of the drive transistor When resistors R2 and R4 are provided between the electrode and the storage node, the critical charge amount increases rapidly when the resistance value exceeds 10Ω, and the soft error resistance becomes extremely strong.

The reason why R2 and R4 have a smaller resistance value than resistors R1 and R3 is due to the difference in current driving ability between the polysilicon pMOS transistor and the drive transistor.

That of a polysilicon 2-open OS transistor is about several μA,
The Ilu dynamic transistor has a difference of about several mA, which is about three orders of magnitude, and it is more effective to provide a resistor to control the transistor with a larger current driving ability. Also, the 6th
The figure shows the current-voltage characteristics of the polysilicon 2-open OS transistor used in the calculation of FIG.

FIG. 7 shows another embodiment of the present invention. (a) is a plan view;
A cross-sectional view is shown in (b). In the embodiment shown in FIG. 1, the gate electrodes of the transfer MOS transistor and the drive transistor are both formed of the first layer polysilicon, whereas in this embodiment, the gate electrode of the transfer MOS transistor is formed of the second layer polysilicon. This is a memory cell formed using a two-layer gout method in which a polysilicon film is formed, the gate electrode of a drive transistor is formed of a first layer polysilicon layer, and the gate electrode of a polysilicon 2-open OS transistor is formed of a third layer polysilicon film.

In FIG. 7(b), an n+ type high concentration impurity region 5a,
5b (Drain electrode.

The transfer MOS transistor is formed by the source electrode) and the second layer polysilicon film 25a (gate electrode), and the drive M
A third layer polysilicon film 26d (gate electrode) and a fourth layer polysilicon film (drain electrode, source electrode, channel portion) 14c are provided on the oxide film 11 provided on the gate electrode 4C of the OS transistor. A polysilicon double-open OS transistor serving as a load is formed by this. Further, the drain electrode 5a of the transfer transistor is further connected to the second layer metal interconnect 13 through the silicon pad 9 and the first layer metal interconnect 12. At this time, the drive MO
Gate electrode 4c of the S transistor.

By not performing implantation at 4d or by performing a small amount of implantation, the resistance value of the goo 1-electrode can be reduced to 2OKΩ.
The above shall apply. In FIG. 7(,), the shaded areas are areas where no implantation is performed, or where a small amount of implantation is performed. Thereby, a resistance element can be provided between the storage node and the gate electrode of the drive transistor.

FIG. 8 shows another embodiment. In contrast to the embodiment shown in FIG. 7 in which the gate electrode of the drive transistor has a high resistance, the present invention has a gate electrode of a polysilicon pMO8+- transistor with a high resistance and a resistance value of 1 OKΩ or more.

The plan view at this time is shown in Figure 8 (a), and the cross-sectional view is shown in Figure 8 (1).
). In FIG. 8(a), the shaded areas are areas where no implantation is performed or where a small amount of implantation is performed. FIG. 9 shows another embodiment. In the present invention, as in FIG. 1, the gate electrodes of the transfer Mos+- transistor and the drive transistor are both formed of a first-layer polysilicon film, and the gate electrode of the polysilicon pMO8+- transistor is formed of a third-layer polysilicon film. . In FIG. 9(a), an n+ type high concentration impurity region 15a is located in the p type substrate 37a.
A p-type impurity region 15 is further formed.

In addition, a transfer transistor is formed by the n+ type high concentration impurity regions 5a, 5b (drain electrode, source electrode) and the first layer polysilicon film 4a' (gate electrode), and similarly the n
+ type high concentration impurity region 5a.

5c (drain electrode, source electrode) and the first layer polysilicon film 4c (gate electrode) form a drive MOS transistor, and the fifth layer polysilicon film 39b (drain electrode, source electrode, channel part) and the third layer polysilicon film 4c (gate electrode) form a drive MOS transistor. The layered polysilicon film 26d (gate electrode) forms an open OS transistor of the polysilicon layer 22, which is a load. At this time, the third
On the oxide film formed on the polysilicon film 26d,
A fourth polysilicon layer 38 is provided, and a fifth polysilicon layer is formed, but there is no oxide film between the fourth and fifth polysilicon layers.

Only the source electrode portion has a double structure formed by the fifth layer polysilicon film, and by adopting such a structure, the resistance of the source electrode portion is reduced.

The drain electrode of the transfer MoS transistor is connected to the second layer metal interconnect 13 via the first layer metal interconnect 12 . At this time, a cross-sectional view when the gate electrode 26c of the polysilicon pMO8 transistor is made high in resistance is shown in FIG. 9(b), and a plan view is shown in FIG. 9(a). In this case, the gate electrode 26c of the polysilicon PMOS transistor,
The resistance value of the gate electrode can be reduced to 3O by not performing implantation or by performing a small amount of implantation.
KΩ or more. The shaded areas in FIG. 9(a) are areas where no implantation is performed or where a small amount of implantation is performed. In addition, in FIG. 9(b), polysilicon pMO8
The gate electrodes 26c and 26d of the transistors are not implanted or have a small amount of implantation. FIG. 10 shows another embodiment.

In the present invention, the embodiment shown in FIG.
In contrast to the high resistance electrode of the transistor, the gate electrode of the drive transistor is made high resistance. A plan view at this time is shown in FIG. 10(a), and a cross-sectional view is shown in FIG. 10(b).

In this case, as shown in FIG.
In the area surrounded by diagonal lines including d, a resistive element is provided with an electrode resistance value of 10 KΩ or more to goo 1 of the drive transistor by not performing implantation or by performing a small amount of implantation.

Further, the present invention is not limited to CMO3SRAM, but is applicable to bipolar.

It can also be applied to Bi-CMO3 circuits.

〔Effect of the invention〕

According to the present invention, when the potential of a storage node that is in a high potential state decreases due to incidence of α rays, implantation is not performed on a part or all of the electrode of the load L/transistor or the drive transistor G1. By performing a small amount of implantation, the resistance value of the gate electrode is set to 3 OKΩ or more, which prevents the current flowing to the storage node that is in a high potential state from decreasing, and as a result, the information is not inverted.
This has the effect of improving soft error resistance.

Further, since this resistance increases the resistance value of the gate electrode itself of the load transistor and the drive transistor, it is possible to achieve this without increasing the memory cell area, which has the effect of increasing integration.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view, a plan view, and a circuit diagram of an embodiment of the present invention, FIG. 2 is a cross-sectional view of an embodiment of the present invention, and FIG. 3 is a cross-sectional view, a plan view, and a circuit diagram of an embodiment of the present invention. Figure 4 shows the conventional example, Figure 5 shows the resistance value dependence of the critical charge group that causes soft errors, Figure 6 shows the current-voltage characteristics of the polysilicon PROS transistor used in the simulation, and Figure 7 shows the current-voltage characteristics of the polysilicon pros transistor used in the simulation.
Figure, Figure 8. 9 and 10 are a plan view and a sectional view of an embodiment of the present invention. 1.2...Bit line, 3...Word line, 4.4a. 4b...gate electrode (first layer polysilicon film), 4c
, 4d... Gate electrode (first layer polysilicon film small amount implant region), 5, 5a to 5f... High concentration n-type impurity region, 6... Glue ~ electrode (first layer polysilicon film) , 7... Dielectric, 8... Polysilicon p MO31
Helangister drain region (4th M polysilicon film),
9a, 9b...Polysilicon pMO8+- transistor gate electrode (third layer polysilicon film), 10.11...
- Dielectric, 12... First layer metal wiring, 13... Second layer metal wiring, 14. a, 14b... Electrode to polysilicon pMOS transistor 1 (3rd layer polysilicon film small amount implant region) 14. c. 14e... Fourth layer polysilicon film, 15... P type well, 15a... Low concentration n type impurity region, 15b...
・P-type silicon substrate, 16-8in2.17a, 17b
...Polysilicon pMOS transistor channel region (second layer polysilicon film), 18...Polysilicon 2
Open OS transistor source region (fourth layer polysilicon film), 19, 21. 23a, 23b. 24, a, 24b, 28, 30, 31, 34, 35°3
6... Connection hole, 20... Dielectric material, 22... High-potency n-type impurity region, 25a, 25f... Second layer polysilicon film (word line), 25b... Second layer polysilicon film Silicon film (ground wiring), 25 c, 25 d, 25
e ・□・Second layer polysilicon film, 26a, 26b...
・First layer polysilicon film small amount implant region, 26c, 2
6d... Third layer polysilicon film small amount implantation region, 27
・3rd layer polysilicon film small amount implant area, 32°33
...Aluminum electrode, 37...N-type silicon substrate, 37
a...p-type silicon substrate, 38...4th layer polysilicon layer (ground wiring), 39a, 39b...5M polysilicon film (polysilicon pMOS h range 1)
Figure (1st Figure (C) ￥i Garden Cb) Funeral Z Senba 3 Figure (υ A' 13 Figure (C) 纂 4 Cause G ■ 3 Figure (b) 1...Kun C8 1 5th Figure 8 (phantom q side (＾小■B times) (b) Kei q country (b)

Claims (1)

[Claims] 1. The drain electrode of the first drive transistor and the drain electrode of the first load transistor are connected to form a first storage node, and similarly the drain electrode of the second drive transistor and the drain electrode of the first load transistor are connected. The drain electrodes of the load transistors are connected to form a second storage node, the gate electrodes of the first drive transistor and the gate electrode of the first load transistor are connected to the second storage node, and the gate electrodes of the first drive transistor and the first load transistor are connected to the second storage node. 2
In a static memory cell in which a gate electrode of a drive transistor and a gate electrode of a second load transistor are connected to the first storage node, the first and second drive transistors and the first and second load transistors are connected to the first storage node. The load transistor is formed of two or more single crystal semiconductor layers or polycrystalline semiconductor layers, or a laminated structure of two or more layers using a single crystal semiconductor layer and a polycrystalline semiconductor layer, and the first and second drive transistors are or the gate electrodes of the first and second load transistors have a resistance value of 10 KΩ or more. 2. The semiconductor memory device according to claim 1, wherein the first and second load transistors are p-channel or n-channel thin film MOS transistors formed of a polysilicon film, The first and second drive transistors are formed on a semiconductor substrate.
A semiconductor memory device characterized by being a channel or p-channel type MOS transistor. 3. A semiconductor memory device according to claim 1, in which the first and second load transistors are formed of a single crystal semiconductor layer provided on an insulating film formed on a drive transistor. A semiconductor memory device characterized by: 4. The drain electrode of the first drive transistor and the gate electrode of the second drive transistor are connected to form a first storage node, and the drain electrode of the second drive transistor and the gate electrode of the first drive transistor are connected. connected second
A first resistance element formed on an oxide film provided on the drive transistor is connected to the first storage node, and similarly, a second resistance element and the second storage node are connected to each other.
1. A semiconductor memory device, characterized in that, in a static memory cell comprising storage nodes connected to each other, gate electrodes of the first and second drive transistors have a resistance value of 5KΩ or more.