JPH045271B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a semiconductor memory integrated circuit device,
In particular, it is suitable for increasing the density of memory cells.
The present invention relates to a semiconductor memory integrated circuit device using MOS transistors.

[Prior art]

Generally, MOS type memory is divided into two types: dynamic type memory and static type memory. Among these, most static type memories use bistable flip-flops as memory cells. This static type memory is characterized by the fact that it does not require the memory cell refresh operation required for a dynamic type memory, has the same access time and operation cycle time, and is capable of high-speed operation. However, on the other hand, the memory cell has two drive MOS transistors and two transfer MOS transistors.
It requires a MOS transistor and two load elements that supply information retention current, and a flip-flop circuit must be configured. Therefore, connection of these elements necessarily requires connection between polycrystalline silicon and a diffusion layer, which has the drawback of increasing the area occupied by the memory cell. Also,
Simply reducing the memory cell area had the disadvantage that the data storage capacity would also become smaller and the resistance to soft errors caused by alpha rays would deteriorate.

On the other hand, in Japanese Patent Application Laid-open No. 57-53972, two drive MOS transistors constituting a static semiconductor memory cell are
Among the transistors, one drive MOS transistor is formed on the surface of the semiconductor substrate, and the other drive MOS transistor is formed on the surface of the semiconductor substrate.
It has been proposed to stack the two drive MOS transistors one above the other by forming the MOS transistor on the polycrystalline silicon gate of one of the drive MOS transistors, thereby reducing the required area of the memory cell.

However, in the memory cell disclosed in Japanese Patent Laid-Open No. 57-53972, the inventors of the present application discovered that the gate insulating films of the two drive MOS transistors are formed in different manufacturing processes. Therefore, it has been found that the two driving MOS transistors tend to have different threshold voltages, and it is difficult to maintain electrical symmetry in the static flip-flop as a memory cell.

[Object of the Invention] Accordingly, an object of the present invention is to provide a static memory cell that occupies a reduced area and has good electrical symmetry.

[Summary of the Invention] Among the inventions disclosed in this application, an outline of typical inventions is as follows.

That is, at least two drive MOS transistors 3, 4 and two transfer MOS transistors 1,
In a bistable flip-flop type memory cell including 2, the two driving MOS transistors 3 and 4 are formed on a silicon substrate 206, and the silicon substrate 206
Silicon layer 204 formed on upper insulating film 205
By forming the two transfer MOS transistors 1 and 2 in the memory cell, the first storage node region of the memory cell operates as at least one of the source region or the drain region of the one transfer MOS transistor 1; One drive MOS
a first single region 10 of the silicon layer in which a gate electrode of the transistor 4 is formed on the insulating film;
1, and the first single region 101 is connected to the other drive MOS transistor 3 in the memory cell.
connected to the drain region of through the first connection part,
The memory cell storage second node region which operates as at least one of the source region and the drain region of the other transfer MOS transistor 2 and the gate electrode of the other drive MOS transistor 3 in the memory cell are connected on the insulating film. a second single region 102 of said silicon layer formed in
It is characterized in that the second single region 102 is connected to the drain region of one of the drive MOS transistors 4 in the memory cell via a second connection portion.

Conventionally, the two storage node regions of a memory cell are generally composed of two N-type impurity layers in a P-type substrate, while the gate electrodes of the two drive MOS transistors are formed on a gate insulating film. The N-type impurity layer, which operates as a memory cell storage node region, and the drive MOS
Two connection parts are required to connect the polycrystalline silicon layer that acts as the gate electrode of the transistor, and an N-type impurity layer that acts as at least one of the source region or the drain region of one transfer MOS transistor. Since a third connection is required, there is a limit to the reduction in memory cell area.

According to the present invention, the memory cell storage node region, which is at least one of the source region and the drain region of the transfer MOS transistor, and the gate electrode of the drive MOS transistor are formed in a single region of a silicon layer formed on an insulating film. Since it has been
Two connections are sufficient instead of the three connections conventionally provided, making it possible to reduce the memory cell area.

[Embodiments of the Invention] A first embodiment of the present invention will be described below with reference to FIGS. 1 and 2.
This will be explained using figures. In FIG. 1, 1 and 2 are first conductivity types whose substrate is the upper polycrystalline silicon layer.
This is a MOS transistor and indicates a transfer MOS transistor. Further, 3 and 4 are first conductivity type MOS transistors formed on the lower silicon substrate,
The drive MOS transistor is shown. Furthermore, 5 and 6
A load resistor is shown at , a pair of complementary data lines D at 7 and 8, a word line W at 9, and a power supply line for the memory cell are shown at _Vcc .

Further, FIG. 2 shows a partial sectional view of the first embodiment, and each number in the drawing indicates the same thing as in FIG. 1. Therefore, 1 in Figure 2 is transfer
A cross-section of the MOS transistor, 4 is a cross-section of the drive MOS transistor, and a cross-sectional view of the gate electrode portion thereof is shown. Furthermore, 7 is a data line D and indicates the drain region of 1. Further, 101 is a storage node, one source region, and four gate electrodes. An outline of the manufacturing process of the example will be described below.
An oxide film 20 for element isolation is formed on a silicon substrate 206.
5 is formed, and then a gate oxide film 201 of a driving MOS transistor is formed. Thereafter, a first layer of second conductivity type polycrystalline silicon layer 204 is laminated on top. Further, an oxide film 203 that becomes a gate oxide film of the transfer MOS transistor 1 is formed, and a second layer of polycrystalline silicon 202 is laminated on top of the oxide film 203 to form a gate electrode 9. Next, using the gate electrode 9 as a mask, first conductivity type impurities are implanted to form the drain electrode 7 and the source electrode 101. As a result, the source electrode 101 of the transfer MOS transistor 1 can be used as the gate electrode of the drive MOS transistor, eliminating the need for a connection between the diffusion layer and the gate electrode, which was a drawback of the conventional method, and reducing the memory cell area. is reduced.

Next, the operation of the above memory cell will be explained. A write operation is performed using a pair of complementary data lines 7, 8.
After setting desired information "1" or "0" to the word line 9, the word line 9 is set at a high potential for a predetermined period to select it.
As a result, transfer MOS transistors 1 and 2 become conductive, and storage nodes 101 and 102 become conductive.
“1” and “0” are written to each. On the other hand, in order to retain information, the resistance values of load resistors 5 and 6 are controlled, and sufficient current is applied to the
1 and 102. Furthermore, in the read operation, similarly to the write operation, a predetermined word line 9 is selected,
A minute potential difference (approximately 200 mV) appearing between a pair of complementary data lines 7 and 8 is amplified by a sense amplifier connected to the data lines and transmitted to the next stage output circuit.

Further, FIG. 3 shows a layout diagram of a memory cell a of the conventional method and a memory cell b of the present invention based on the same design rule. In the figure, the area surrounded by the thick solid line is the active area formed on the silicon substrate, the thin solid line is the gate part, the dashed line is the wiring metal,
The hatched portion indicates the connection between the active region and the gate portion. As shown in the figure, according to the memory cell of the present invention, the transfer MOS transistor is formed of a polycrystalline silicon layer, and since it can be used as the gate electrode of the drive MOS transistor, the diffusion layer and the polycrystalline silicon layer are There is one less connection point, and the area can be reduced by approximately 30% compared to the conventional method.

In this embodiment, a first conductivity type MOS transistor is used as the transfer MOS transistor, but a second conductivity type MOS transistor may also be used. In that case, the word line 9 is selected at a low potential.

Furthermore, as the first layer of polycrystalline silicon 204,
It is also possible to use pure polycrystalline silicon without impurities. Furthermore, it is also possible to use a metal or metal silicide layer for the second layer of polycrystalline silicon. In that case, the word line resistance of the memory cell can be extremely low. This has the effect of shortening the word line delay time, and since the metal gate can be formed in a step near the end of the process, there are fewer heat treatment steps and the metal is not oxidized. Therefore, manufacturing advantages are extremely large.

FIG. 4 shows a second embodiment. In the memory cell of this embodiment, first conductivity type transfer MOS transistors having polycrystalline silicon as a substrate are applied to 1 and 2 as in the first embodiment, and 3 and 4 have first conductivity type transfer MOS transistors. drive MOS transistor and 11
and 12 load MOS transistors of the second conductivity type constitute a complementary flip-flop type memory cell. Also in this embodiment, the first
Similar to the embodiment, there is no need for a connection between the diffusion layer and the polycrystalline silicon layer, and the memory cell can be reduced in size compared to the conventional method of fabricating a transfer MOS transistor on a silicon substrate. Further, the second conductivity type load MOS transistors 11 and 12 share the gate electrodes of the drive MOS transistors 3 and 4,
Since it is possible to stack the memory cell on top of it, it is possible to further reduce the memory cell area.

FIG. 5 shows a third embodiment. In the figure, numerals 1 and 2 are first conductivity type transfer MOS transistors whose substrates are polycrystalline silicon, as in the first embodiment. Moreover, 301 and 302 are
It shows the leak resistance between the source and drain of the MOS transistor. In this embodiment, by controlling the current caused by this leak resistance to about 10 ^-10 to ^{10 -11} A, it is made to play the role of the load resistor shown in the first embodiment. That is, as shown in Figure 5,
A pair of complementary data lines 7 and 8 supply the current necessary to retain information. The operation of the memory cell of this embodiment will be explained below.

During a write operation, one of the pair of complementary data lines is always at a low potential (0V). Therefore, if a memory cell is selected for a long time, there is a possibility that information in unselected memory cells connected to the same data line as the selected memory cell may be destroyed. Therefore, in the semiconductor memory of this embodiment, it is necessary to perform a dynamic operation of the data line such that a series of write operations is completed before the accumulated charges in unselected memory cells are discharged below a certain level. Note that during read operation, the data line capacitance is
Since it is several tens to hundreds of times larger than the storage capacity of the cell, the potential difference between the pair of complementary data lines is minute. Therefore, the read operation does not destroy information in unselected memory cells. Furthermore, in the information holding state, since the potentials of the pair of complementary data lines are set to high potential at the same time, information destruction does not occur as in reading.

According to the present invention, in addition to the effects of the first embodiment,
The load resistors 5 and 6 shown in FIG. 1 become unnecessary, and the power supply line V _cc becomes unnecessary. Therefore, the area of the memory cell is smaller than that of the first embodiment.

FIG. 6 shows a specific example of improving the performance of the transfer MOS transistors used in the first to third examples. In the same figure, 206
2 is a silicon substrate, 208 is an oxide film for element isolation, and 2
07 is the first polycrystalline silicon layer, 203 is the gate oxide film of the transfer MOS transistor, 202 is the
A second layer of polycrystalline silicon, a metal layer, or a metal silicide layer is shown, and serves as the gate electrode of the transfer MOS transistor. 13 and 14 are 20
2 is used as a mask to show the drain and source electrodes after impurity implantation.

The feature of the present invention is that the polycrystalline silicon layer is made into a single crystal by sequentially irradiating the laser beam from the contact portion 209 between the silicon substrate and the polycrystalline silicon layer.

Note that the MOS shown in the first and second embodiments
Although the transistor has been described using a first conductivity type MOS transistor, it goes without saying that a second conductivity type MOS transistor can also be used by reversing all the potential relationships.

〔Effect of the invention〕

According to the present invention, a MOS transistor using a polycrystalline silicon layer as a substrate is formed on an insulating oxide film. Therefore, there is no substrate dependence of threshold voltage that occurs in MOS transistors fabricated on general silicon substrates. Furthermore, since the polycrystalline silicon layer is thin, charge generation due to alpha rays is extremely small. Therefore, it is effective in improving the soft error resistance of the memory. Furthermore, by laser annealing polycrystalline silicon, it is expected that the mutual conductance gm will be improved.
As a transfer MOS transistor for memory cells,
It is extremely effective.

[Brief explanation of drawings]

1 and 3 are specific embodiments of the present invention, FIG. 2 is a partial sectional view of the embodiment of the present invention, and FIG.
Other embodiments of the present invention are shown in FIGS. 5 and 6, respectively. 1, 2... Transfer MOS transistor, 3, 4... Drive MOS transistor, 5, 6... Load resistor, 7,
8... Complementary data line (D,), 9... Word line (W), 101, 102... Storage node, 201... Gate oxide film of drive MOS transistor, 202...
Second polycrystalline silicon layer, 203...Transfer
Gate oxide film of MOS transistor, 204... first layer polycrystalline silicon layer, 205, 208... oxide film for element isolation, 206... silicon substrate, 30
1,302...Leak resistance of transfer MOS transistor, 11,12...Load MOS transistor, 20
7...Polycrystalline silicon layer.

Claims (1)

[Claims] 1. In a bistable flip-flop memory cell including at least two drive MOS transistors and two transfer MOS transistors, the two drive MOS transistors are formed on a silicon substrate, and the silicon substrate a memory cell first storage node region that operates as at least one of a source region and a drain region of one of the transfer MOS transistors by forming the two transfer MOS transistors with a silicon layer formed on the upper insulating film; and driving one of the above memory cells.
a first single region of the silicon layer formed on the insulating film, and a gate electrode of the MOS transistor and a gate electrode of the other drive MOS transistor in the memory cell. A memory device connected to the drain region via the first connection portion and operating as at least one of the source region and the drain region of the other transfer MOS transistor.
a cell storage second node region and a gate electrode of the other drive MOS transistor in the memory cell are configured by a second single region of the silicon layer formed on the insulating film; A semiconductor memory integrated circuit device, characterized in that a single region is connected to the drain region of one of the drive MOS transistors in the memory cell via a second connection portion. 2. The semiconductor memory integrated circuit device according to claim 1, wherein the silicon layer is a polycrystalline silicon layer. 3. The single region of the silicon layer that operates as the memory cell storage node region and the gate electrode of the one drive MOS transistor is a first silicon layer on the insulating film, and 2. The semiconductor memory integrated circuit device according to claim 1, wherein the gate electrode of the MOS transistor is formed of a second layer of silicon, metal, or metal silicide on the insulating film. 4 Transferring the information retention current of the memory cell
2. The semiconductor memory integrated circuit device according to claim 1, wherein the semiconductor memory integrated circuit device is supplied through a leakage resistor between a source and a drain of a MOS transistor. 5. According to claim 1, the silicon layer is formed by monocrystallizing polycrystalline silicon formed on the insulating film using a thermal means such as a laser. The semiconductor memory integrated circuit device described. 6. The two load MOS transistors in the memory cell are of opposite conductivity type to the two drive MOS transistors, and the gate electrodes of the two load MOS transistors are shared with the gate electrodes of the two drive MOS transistors; the two loads
2. The semiconductor memory integrated circuit device according to claim 1, wherein the MOS transistor is stacked on top of the two drive MOS transistors. 7. Claims 1 to 6, characterized in that the insulating film is formed on a semiconductor substrate.
3. The semiconductor memory integrated circuit device according to any one of the items.