JPH04162777A - Bidirectional voltage checking semiconductor device - Google Patents

Bidirectional voltage checking semiconductor device

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Publication number
JPH04162777A
JPH04162777A JP2289855A JP28985590A JPH04162777A JP H04162777 A JPH04162777 A JP H04162777A JP 2289855 A JP2289855 A JP 2289855A JP 28985590 A JP28985590 A JP 28985590A JP H04162777 A JPH04162777 A JP H04162777A
Authority
JP
Japan
Prior art keywords
semiconductor
semiconductor layer
junction
layer
bidirectional voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2289855A
Other languages
Japanese (ja)
Inventor
Kazuyasu Yoneyama
米山 和穏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP2289855A priority Critical patent/JPH04162777A/en
Publication of JPH04162777A publication Critical patent/JPH04162777A/en
Pending legal-status Critical Current

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  • Thyristors (AREA)

Abstract

PURPOSE:To facilitate manufacturing and improve reliability by exposing the junction on the side of a supporting plate on the bevel face by mesa-etching thereby making it into a mesa structure, and exposing the junction on the opposite side on the main face thereby making it into a planar structure. CONSTITUTION:The third semiconductor layer 3 is the region selectively made in one side of the first semiconductor layer 1, and the junction 13 between the first and third semiconductor layers 1 and 3 is covered with the first protective film, and the other side of the first semiconductor layer 1 is in contact with the second semiconductor layer 2, and the junction 12 between the first and second semiconductor layers 1 and 2 is exposed on the side 41, which has an inclination such that the area of the second semiconductor layer 2 decreases as the distance from the junction increases, and is covered with the second protective film 42. That is, the third semiconductor layer side 3 is of a planar structure, and the second semiconductor layer side 2 is of a mesa structure, and the junction between the first and second semiconductor layers 1 and 2 is apart from a conductive supporting plate 6. Hereby, the facilitation of the manufacturing and the improvement of reliability can be realized.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、一つのより高比抵抗の半導体層をはさんで二
つの逆導電型の半導体層が設けられてそれぞれの間に順
方向の同きが逆のPN接合を有する、逆阻止型サイリス
タ、トライアック、ダイアック等の双方向電圧阻止型半
導体装置に関する。
[Detailed Description of the Invention] [Industrial Field of Application] The present invention is characterized in that two semiconductor layers of opposite conductivity type are provided with one semiconductor layer of higher resistivity sandwiched therebetween, and a semiconductor layer of a forward direction is formed between the two semiconductor layers of opposite conductivity type. The present invention relates to bidirectional voltage blocking semiconductor devices such as reverse blocking thyristors, triacs, diacs, etc., which have opposite PN junctions.

〔従来の技術〕[Conventional technology]

双方向電圧阻止型半導体装置においては、双方向の阻止
電圧が等しいことが望ましい。しかし、板状半導体素体
はその一面により支持体上に支持されるため、表裏の条
件を同様にすることが難しく、それに対しで種々の方式
が考案されている。
In a bidirectional voltage blocking semiconductor device, it is desirable that the blocking voltages in both directions be equal. However, since the plate-shaped semiconductor element is supported on a support by one side, it is difficult to make the conditions on the front and back sides the same, and various methods have been devised to solve this problem.

第2図に示すプレーナ型サイリスタでは、n−シリコン
基板1をはさんで、nエミツタ層となるp型拡散層2と
pベース層となるp型拡数層3が存在し、基板1の残っ
た部分がn<−ス層となり、pベース層3の表面部にn
エミツタ層となるn゛拡散層4が形成されている。nエ
ミツタ層2は、両面からのp型拡散層21.22により
nエミツタ層4の存在する表面まで延長されている。こ
の結果、高比抵抗のnベースIIIと21472層2と
の間のPN接合12.pベース層3との間のPN接合1
3は、基板の同一表面に露出し、拡散マスクとして用い
られた酸化膜5によって保護されている。そして、21
472層2に接触する裏面電極6には7ノード端子7が
、n←纂冶エミフタ層4に接触する上部電8i81には
カソード・端子9が、pベース層3の露出面に接触する
上部電8i82にはゲート端子10が接続されている。
In the planar thyristor shown in FIG. 2, there are a p-type diffusion layer 2, which becomes an n-emitter layer, and a p-type expansion layer 3, which becomes a p-base layer, sandwiching an n-silicon substrate 1. The part where n<- becomes a layer, and n
An n-diffusion layer 4 serving as an emitter layer is formed. The n-emitter layer 2 is extended to the surface where the n-emitter layer 4 is present by p-type diffusion layers 21, 22 from both sides. This results in a PN junction 12. between the high resistivity n-base III and the 21472 layer 2. PN junction 1 between p base layer 3
3 is exposed on the same surface of the substrate and protected by an oxide film 5 used as a diffusion mask. And 21
The back electrode 6 in contact with the 472 layer 2 has a 7 node terminal 7, the upper electrode 8i81 in contact with the n← emitter layer 4 has a cathode/terminal 9, and the upper electrode in contact with the exposed surface of the p base layer 3 The gate terminal 10 is connected to 8i82.

このようにこのサイリスタでは二つのPN接合を基板同
一面に露出させることによって耐圧に対する条件を同じ
にしている。
In this way, in this thyristor, the two PN junctions are exposed on the same surface of the substrate, thereby making the conditions for breakdown voltage the same.

第3図に示す両面プレーナ型サイリスタの場合は、n−
シリコン基板]の両面からの選択拡散により、対称的に
21472層2およびpベース層3が形成されており、
PN接合12および13は両面にそれぞれ露出している
。これらのPN接合の耐圧向上のため裏面側にはp型ガ
ードリング31が、表面側にはp型ガードリング32が
それぞれ2個ずつnエミツタ層2およびpベース層3を
囲んで形成されている。
In the case of the double-sided planar thyristor shown in Figure 3, n-
A 21472 layer 2 and a p base layer 3 are formed symmetrically by selective diffusion from both sides of the silicon substrate.
PN junctions 12 and 13 are exposed on both sides, respectively. In order to improve the breakdown voltage of these PN junctions, two p-type guard rings 31 are formed on the back side, and two p-type guard rings 32 are formed on the front side, surrounding the n emitter layer 2 and the p base layer 3. .

第4図に示す両面メサ型サイリスタでは、PN接合12
.13共に基板面に平行に形成されており、その露出部
が正へベル面41となるようにメサエッチが施されてい
る。そして、各ベベル面41を保護膜としてのガラス膜
42が覆っている。
In the double-sided mesa type thyristor shown in Fig. 4, the PN junction 12
.. 13 are both formed parallel to the substrate surface, and mesa-etched so that the exposed portion thereof becomes a positive helical surface 41. Each beveled surface 41 is covered with a glass film 42 serving as a protective film.

これらの半導体装置のシリコン基板は、電極6の側で導
電性支持板に支持され、その支持板と電気的に接続され
る。
The silicon substrates of these semiconductor devices are supported by a conductive support plate on the electrode 6 side and electrically connected to the support plate.

〔発明が解決しようとする課B] 上に述べた双方向電圧阻止型半導体装置のうち、第2図
に示した片面プレーナの場合には、裏面側の9層2を表
面まで延長するため、つきぬけ拡散という非常に長時間
を必要とする拡散工程で深い拡散層21 、22を形成
するため、装置稼働率の低下。
[Problem B to be Solved by the Invention] Among the bidirectional voltage blocking semiconductor devices described above, in the case of the single-sided planar shown in FIG. 2, in order to extend the nine layers 2 on the back side to the front surface, Since the deep diffusion layers 21 and 22 are formed by a diffusion process called through-diffusion, which requires a very long time, the operating rate of the device decreases.

特性劣化、良品率低下を招く欠点があった。また、第3
図に示した両面プレーナの場合には、パッシベーション
膜5が薄いため、裏面側のパッシベーション膜5が損傷
を受けやすく、信頼性が十分でないという欠点があった
。また裏面のシリコン基板1の端面と裏面電極6と等電
位の導電性支持板との距離が十分にとれないため、シリ
コン基板と支持板との間で放電を起こす欠点があった。
There were drawbacks that led to deterioration of characteristics and a decrease in the rate of non-defective products. Also, the third
In the case of the double-sided planar shown in the figure, since the passivation film 5 is thin, the passivation film 5 on the back side is easily damaged, and the reliability is insufficient. Furthermore, since there is not a sufficient distance between the end surface of the silicon substrate 1 on the back side, the back electrode 6, and the conductive support plate having the same potential, there is a drawback that discharge occurs between the silicon substrate and the support plate.

さらに、第4図に示した両面メサ型の場合には、このよ
うな半導体片を1枚のシリコンウェー八から多数つくる
際、両面からメサエッチを施すためにメサ溝によってウ
ェーハの強度が低下し、半導体片分割前の工程でのウェ
ーハ取扱いに注意を払わなければならないという欠点が
あった。
Furthermore, in the case of the double-sided mesa type shown in FIG. 4, when a large number of such semiconductor pieces are made from one silicon wafer, the strength of the wafer is reduced due to mesa grooves because mesa etching is performed from both sides. There is a drawback that care must be taken in handling the wafer in the process before dividing into semiconductor pieces.

本発明の目的は、上述の欠点を除き、製造が容易で信頼
性の高い双方向電圧阻止型半導体装置を提供することに
ある。
SUMMARY OF THE INVENTION An object of the present invention is to provide a bidirectional voltage blocking semiconductor device that is easy to manufacture and has high reliability, while eliminating the above-mentioned drawbacks.

〔課題を解決するための手段〕[Means to solve the problem]

上記の目的を達成するために、本発明は、半導体基板内
においてより高圧抵抗の第一導電型の第一半導体層が第
二導電型の第二および第三半導体層にはさまれており、
第二半導体層側で導電性支持板に支持される双方向電圧
阻止型半導体装置において、第三半導体層は第一半導体
層の一面から選択的に形成された領域であり、第一、第
三半導体層の間の接合が第一保護膜で覆われ、第一半導
体層の他面は全面が第二半導体層に接し、第一。
In order to achieve the above object, the present invention provides a semiconductor substrate in which a first semiconductor layer of a first conductivity type having a higher voltage resistance is sandwiched between second and third semiconductor layers of a second conductivity type,
In a bidirectional voltage blocking semiconductor device supported by a conductive support plate on the second semiconductor layer side, the third semiconductor layer is a region selectively formed from one surface of the first semiconductor layer; The junction between the semiconductor layers is covered with a first protective film, the other surface of the first semiconductor layer is entirely in contact with the second semiconductor layer, and the first semiconductor layer is in contact with the second semiconductor layer.

第二半導体層の間の接合がその接合から遠ざかるにつれ
て第二半導体層の面積が小さくなるような慄斜をもつ側
面に露出して第二保護膜に覆われたものとする。そして
、第一保護膜が半導体材料の酸化物よりなり、第二保護
膜がガラスよりなるか、第一、第二保護膜共にガラスよ
りなることが有効である。また、このような半導体装置
としては、逆狙止型サイリスタ、トライチックあるいは
ダイアノクがある。
It is assumed that the junction between the second semiconductor layers is exposed and covered with the second protective film on a side surface having a slope such that the area of the second semiconductor layer decreases as the distance from the junction increases. It is effective that the first protective film is made of an oxide of a semiconductor material and the second protective film is made of glass, or that both the first and second protective films are made of glass. Furthermore, such semiconductor devices include a reverse aiming type thyristor, a tritic, and a dianoch.

〔作用〕[Effect]

上記の半導体装置は第三半導体層側がブレーナ構造で、
第二半導体層側がメサ型構造であり、つきぬけ拡散を必
要としない。そして半導体基板の支持板側の面にはパッ
シベーション膜が存在しないのでパッシベーション族の
損傷の問題はない。
The above semiconductor device has a brainer structure on the third semiconductor layer side,
The second semiconductor layer side has a mesa-type structure and does not require through-diffusion. Since no passivation film is present on the support plate side surface of the semiconductor substrate, there is no problem of damage to the passivation group.

また、第一、第二半導体層の間の接合は導電性支持板よ
り離れているため、第一半導体層と支持板との間の放電
発生のおそれがない、さらにこのような半導体装置の半
導体片を1枚のウェーハから多数造る場合も、メサ溝は
片側だけに形成すればよいのでウェーハの強度低下は少
なく、工程中のウェーハ取扱いが容易になる。
In addition, since the junction between the first and second semiconductor layers is separated from the conductive support plate, there is no risk of electrical discharge occurring between the first semiconductor layer and the support plate. Even when a large number of pieces are made from one wafer, it is only necessary to form the mesa groove on one side, so there is little deterioration in the strength of the wafer, and wafer handling during the process becomes easier.

〔実施例〕〔Example〕

第1図は本発明の一実施例の逆阻止型サイリスタを示し
、第2図ないし第4図と共通の部分には同一の符号が付
されており、上面側がブレーナ構造、下面側がメサ型構
造となっている。このサイリスタは次のようにして製作
される。先ずn−シリコン基板1に一面からは全面拡散
、他面からは酸化膜5をマスクとする選択拡散によりp
型拡散層2および複数のp型拡散層3を形成する。同時
にp型拡散層3を囲んで二重にp型ガードリング32を
形成する0次にあらためて酸化膜マスクを形成して各p
型拡散層3に選択的にn゛拡散層4を形成する。そして
下面側には格子状に開口部を有するマスクを例えばレジ
スト膜で形成し、メサエッチングを施してベベル面41
を形成する。このあと、上面には酸化膜5に開けた窓で
0層4に接触する上部電極81,9層3に接触する上部
電極82を形成し、また下面に電極6を形成する。この
のち、メサ溝部で分割して第1図に示す半導体片の複数
個を得る0次いで電極81をカソード端子9に、電8i
82をゲート端子10に接続し、電極6をアノード端子
7に接続する。ベベル面41はガラス膜42で被覆する
。このようにして、pエミツタ層2+  nベース層1
.  I)ベース層3+  nエミツタ層4を有し、2
層2とn−層1の間の接合12の露出面はガラス膜42
で保護され、9層3とn−層lの間の接合13ならびに
9層3と0層4の間およびp型ガードリング32とn−
層1の間の接合がすべて酸化膜で保護されたサイリスタ
が得られる。
FIG. 1 shows a reverse blocking thyristor according to an embodiment of the present invention, in which the same parts as in FIGS. 2 to 4 are given the same reference numerals, and the upper surface side has a brainer structure and the lower surface side has a mesa type structure. It becomes. This thyristor is manufactured as follows. First, p is applied to the n-silicon substrate 1 by full diffusion from one side and selective diffusion using the oxide film 5 as a mask from the other side.
A type diffusion layer 2 and a plurality of p-type diffusion layers 3 are formed. At the same time, an oxide film mask is formed again for the 0th order to form a double p-type guard ring 32 surrounding the p-type diffusion layer 3, and each
An n' diffusion layer 4 is selectively formed in the type diffusion layer 3. Then, on the lower surface side, a mask having openings in a grid pattern is formed using, for example, a resist film, and mesa etching is performed to form the beveled surface 41.
form. Thereafter, an upper electrode 81 in contact with the 0 layer 4 and an upper electrode 82 in contact with the 9 layer 3 are formed on the upper surface through a window opened in the oxide film 5, and an electrode 6 is formed on the lower surface. Thereafter, the electrode 81 is divided at the mesa groove to obtain a plurality of semiconductor pieces as shown in FIG.
82 is connected to the gate terminal 10, and the electrode 6 is connected to the anode terminal 7. The beveled surface 41 is covered with a glass film 42 . In this way, p emitter layer 2 + n base layer 1
.. I) base layer 3 + n emitter layer 4, having 2
The exposed surface of the junction 12 between layer 2 and n-layer 1 is covered with a glass membrane 42.
The junction 13 between the 9-layer 3 and the n-layer l and the junction 13 between the 9-layer 3 and the 0-layer 4 and between the p-type guard ring 32 and the n-
A thyristor is obtained in which all the junctions between layers 1 are protected by an oxide film.

第5図は本発明の別の実施例の逆阻止型サイリスタを示
し、第1図のサイリスタと異なる点は、上面の周縁部に
浅いエツチングを施し、n−層1と9層3およびp型ガ
ードリング32との間のPN接合の露出部をガラス膜(
グラシベーション層)42で保護したことである。
FIG. 5 shows a reverse blocking thyristor according to another embodiment of the present invention, which differs from the thyristor in FIG. The exposed part of the PN junction between the guard ring 32 is covered with a glass film (
It is protected by a glacivation layer) 42.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、双方向電圧阻止型半導体装置の支持板
側の接合はメサエッチングによるベベル面に露出させて
メサ型構造にし、反対側の接合は半導体基板の主面に露
出させてブレーナ構造にすることにより、片面プレーナ
型構造でのつきぬけ拡散を不要にし、両面ブレーナ型構
造での支持板側の保II膜の信頼性低下および支持板と
の間の放電の問題を除き、メサ型構造の場合のウェーハ
の強度低下の問題を解決することにより、高信頼性の逆
阻止型サイリスタ、トライアックあるいはダイアックを
得ることができる0両接合の保護膜としてはガラス膜あ
るいは酸化膜を有効に組合わせることができる。
According to the present invention, the junction on the support plate side of a bidirectional voltage blocking semiconductor device is exposed on the bevel surface by mesa etching to form a mesa-type structure, and the junction on the opposite side is exposed on the main surface of the semiconductor substrate to form a brainer structure. This eliminates the need for through-diffusion in a single-sided planar structure, and eliminates the problem of reduced reliability of the retainer II membrane on the support plate side and discharge between the support plate and the mesa-type structure in a double-sided planar structure. Highly reliable reverse blocking thyristors, triacs or diacs can be obtained by solving the problem of wafer strength reduction in the case of be able to.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例のサイリスタの断面図、第2
図、第3図、第4図はそれぞれ従来のサイリスタの異な
る構造を示す断面図、第5図は本発明の別の実施例のサ
イリスタの断面図である。 1:n−シリコン基板、2.3:1)型拡散層、4:n
゛拡散層、5二酸化膜、7:アノード端子、9;カソー
ド端子、10:ゲート端子、32:p型ガードリング、
41:ベベル面、42ニガラス膜。
FIG. 1 is a cross-sectional view of a thyristor according to an embodiment of the present invention, and FIG.
3 and 4 are cross-sectional views showing different structures of conventional thyristors, respectively, and FIG. 5 is a cross-sectional view of a thyristor according to another embodiment of the present invention. 1: n-silicon substrate, 2.3: 1) type diffusion layer, 4: n
゛Diffusion layer, 5 dioxide film, 7: anode terminal, 9: cathode terminal, 10: gate terminal, 32: p-type guard ring,
41: Beveled surface, 42 Niglass film.

Claims (1)

【特許請求の範囲】 1)半導体基板内においてより高比抵抗の第一導電型の
第一半導体層が第二導電型の第二および第三半導体層に
はさまれており、第二半導体層側で導電性支持板に支持
されるものにおいて、第三半導体層は第一半導体層の一
面から選択的に形成された領域であり、第一、第三半導
体層の間の接合が第一保護膜で覆われ、第一半導体層の
他面は全面が第二半導体層に接し、第一、第二半導体層
の間の接合がその接合から遠ざかるにつれて第二半導体
層の面積が小さくなるような傾斜をもつ側面に露出して
第二保護膜に覆われたことを特徴とする双方向電圧阻止
型半導体装置。 2)請求項1記載の半導体装置において、第一保護膜が
半導体材料の酸化物よりなり、第二保護膜がガラスより
なる双方向電圧阻止型半導体装置。 3)請求項1記載の半導体装置において、第一、第二保
護膜共にガラスよりなる双方向電圧阻止型半導体装置。 4)請求項1、2あるいは3記載の半導体装置において
、逆阻止型サイリスタである双方向電圧阻止型半導体装
置。 5)請求項1、2あるいは3記載の半導体装置において
、トライアックである双方向電圧阻止型半導体装置。 6)請求項1、2あるいは3記載の半導体装置において
、ダイアックである双方向電圧阻止型半導体装置。
[Claims] 1) A first semiconductor layer of a first conductivity type having a higher specific resistance is sandwiched between second and third semiconductor layers of a second conductivity type in the semiconductor substrate, and the second semiconductor layer is sandwiched between second and third semiconductor layers of a second conductivity type. In the case where the third semiconductor layer is supported by a conductive support plate on the side, the third semiconductor layer is a region selectively formed from one side of the first semiconductor layer, and the junction between the first and third semiconductor layers is the first protection layer. The other surface of the first semiconductor layer is covered with a film, the entire other surface of the first semiconductor layer is in contact with the second semiconductor layer, and the area of the second semiconductor layer decreases as the junction between the first and second semiconductor layers moves away from the junction. A bidirectional voltage blocking type semiconductor device characterized by having an exposed side surface with an inclined surface and covered with a second protective film. 2) A bidirectional voltage blocking semiconductor device according to claim 1, wherein the first protective film is made of an oxide of a semiconductor material and the second protective film is made of glass. 3) A bidirectional voltage blocking semiconductor device according to claim 1, wherein both the first and second protective films are made of glass. 4) A bidirectional voltage blocking semiconductor device according to claim 1, which is a reverse blocking thyristor. 5) A bidirectional voltage blocking semiconductor device according to claim 1, 2 or 3, which is a triac. 6) A bidirectional voltage blocking semiconductor device according to claim 1, 2 or 3, which is a diac.
JP2289855A 1990-10-26 1990-10-26 Bidirectional voltage checking semiconductor device Pending JPH04162777A (en)

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001185727A (en) * 1999-10-15 2001-07-06 Fuji Electric Co Ltd Semiconductor device and method of manufacturing the same
DE102011083230A1 (en) 2010-09-22 2012-03-22 Mitsubishi Electric Corp. Semiconductor device
JP2023066526A (en) * 2021-10-29 2023-05-16 三菱電機株式会社 Silicon carbide semiconductor device manufacturing method and silicon carbide semiconductor chip

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49124989A (en) * 1973-04-02 1974-11-29

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS49124989A (en) * 1973-04-02 1974-11-29

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2001185727A (en) * 1999-10-15 2001-07-06 Fuji Electric Co Ltd Semiconductor device and method of manufacturing the same
DE102011083230A1 (en) 2010-09-22 2012-03-22 Mitsubishi Electric Corp. Semiconductor device
CN102412261A (en) * 2010-09-22 2012-04-11 三菱电机株式会社 Semiconductor device
US8643146B2 (en) 2010-09-22 2014-02-04 Mitsubishi Electric Corporation Semiconductor device
DE102011083230B4 (en) 2010-09-22 2020-06-18 Mitsubishi Electric Corp. Semiconductor devices
JP2023066526A (en) * 2021-10-29 2023-05-16 三菱電機株式会社 Silicon carbide semiconductor device manufacturing method and silicon carbide semiconductor chip

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