JPH04162829A - A/d converter - Google Patents

Abstract

PURPOSE:To obtain an accurate A/D conversion result by providing a voltage current conversion section converting a voltage applied to an analog input terminal into a current, 1st and 2nd current sources whose current changes depending on the converted current, a differential input and active load transistor (TR), a D/A converter and 1st and 2nd output drive sections to the title A/D converter. CONSTITUTION:A voltage applied to an analog input terminal 1 is converted into a current by a voltage/current conversion section 2, a current equal to the converted current is supplied also to a 2nd current source 6 comprising a P-channel MOS TR. Moreover, a current from a 1st current source 3 changes in interlocking with a current converted by the voltage current conversion section 2. Then a drain level of an N-channel MOS TR QN2 of a feedback circuit drive section 7 comprising the 1st current source 3, a differential input TR 4, an active load TR 5, the output drive section 7, a frequency correction TR 15, and a frequency correction capacitor 16 is kept to a voltage V1 (constant) of a reference voltage source 12. Thus, accurate A/D conversion is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an A/D converter, and more particularly to an A/D converter that uses a current comparison method and is suitable for fabrication into a monolithic IC.

[Conventional technology]

Conventionally, successive approximation type A/D converters using MOSFETs have been known as such A/D converters.

FIG. 3 is a circuit diagram of an A/D converter illustrating an example of such a conventional A/D converter.

As shown in FIG. 3, the conventional A/D converter includes a differential amplifier 19 connected to an analog input terminal 1 and a P channel (Pch) transistor (Tr) Qpt.
and N Ch MOS T r QNI and resistor R
A voltage/current converter 2 consisting of a
A second current source 6 consisting of chMO8Tr and NchM
A first output drive unit 7 consisting of O8Tr QN21QN3 and Nch MO3Tr QN4. A second pressure drive section 9 consisting of QN5 and a 6-bit current pressure type D/
An A converter 8, an analog switch 10, a comparator 11, a reference voltage source 12 and a pulse generator 17 connected to these analog switches 1O, etc., and a successive approximation unit connected to the output side of the comparator 11 and the digital output terminal 14. Frequency correction Tr1 connected between the register 13, one input terminal of the differential input Tr4, and the active load Tr5
5 and a capacity 16, and first and second pressure drives 7,
9 and a reference voltage source 18 connected to the reference voltage source 18.

For convenience, the D/A converter 8 described above has a resolution of 6 blt.

In such an A/D converter, a voltage applied to an analog input terminal 1 is converted into a voltage/current by a voltage/current converter 2. At this time, it is assumed that equal currents flow through the Pch MO8TrQp+ and the P channel MO8Tr constituting the second current source 6. Also, the first current source 3. Differential input Tr4, active load Tr5. Fifth. Current source 6. The circuit consisting of the first pressure drive unit 72 frequency correction Tr 15 and frequency correction capacitor 16 forms the first output drive unit 7 so that the output voltage (V l) of the reference voltage source 12 is constant. MO8Tr Controls the drain terminal of QN2.

On the other hand, the reason why the input terminal of the comparator 11 is short-circuited by the pulse from the analog switch 10 and the pulse generator 17 is to equalize the currents flowing through the current mirror circuit composed of NchMO8TrQN3 and QNj. By this analog switch 10, comparator 1
With the input terminal 1 open, N c h MOS T r QN
The drain potential of < oscillates with the output voltage 1 of the reference voltage source 12 as the boundary.

As described above, if the A/D converter has n-bit resolution, the above operation is repeated n times via the successive approximation register 13.

[Problem to be solved by the invention]

The conventional A/D converter described above includes a first current source 3, a differential input Tr 4. Active load Tr・5. Second current source 6 consisting of PchMO8Tr. Output drive unit 7, frequency correction T
r15. A feedback circuit consisting of a frequency correction capacitor 16 is configured. In this feedback circuit, the mutual fundductance G, , 1 at the input stage can be expressed by the following equation (1).

However, μ is mobility and ε. . is the dielectric constant of the gate oxide film,
t. , is the thickness of the gate oxide film, L + r W+ rV
Q81 is each P Ch MOS T r Qp
t gate width, gate length, gate-source voltage, V7
p is the threshold voltage of PchMO8Tr.

Also, the mutual conductance G in the output stage. 2 can be expressed by the following equation (2).

However, L 2 , W2 r VO52 are each Nc
The gate width, gate length, gate-source voltage, and VT)J of hMO3TrQNx are the threshold voltages of Nch MO3Tr.

Here, in the high frequency region of ω,=Gi2/CC (CC is the capacitance value of the frequency correction capacitor 16), the frequency correction capacitor 1
6 is the drain of TrQNz of the output driver 7 and TrQN3
Start shorting between the gates.

Therefore, the small signal current of the first stage flows into the impedance (110, 2) looking into the diode-connected output driver 7. That is, the gain in this band is as follows. Note that Az is the gain at the zero point.

The stability condition at the Zero point of this circuit is determined by the equation, so by substituting the above-mentioned equations (1) and (2) into equation (4), the following is obtained.

Now, the current converted by the voltage/current converter 2 is IL
If SB=1μA, 6b it A shown in FIG.
/ When a full-scale voltage is applied to the analog input terminal 1 in the D converter 8, it is converted to a current of 64 μA by the voltage/current converter 2, so a current of 64 μA is also applied to the second current source 6 made of PchMO8Tr. flows. At this time, if the current source 3 is set so that the current flowing through Qp4 of the differential input Tr4 is 1 μA, and the parameters of TrQp4 are set equal to Tr QN3, the gain at the zero point in the feedback circuit described above is as follows. of (6
) and is stable.

=0.125<0.316 ・・・・・・
(6) When A/D conversion is performed in this state, a 6-bit full-scale code is obtained at the digital output terminal 14.

Next, when a voltage corresponding to ILSB is applied to the analog input terminal 1, it is converted to a current of 1 μA by the voltage/current converter 2, and the second current source 6 consisting of PchMO8Tr is converted to a current of 1 μA.
A current of 1 μA flows through both. At this time, N c h MO
The drain potential of S T r QN2 is V+ (constant)
1μA to NchMO3Tr QN3 while being kept at
The gate potential changes so that the current flows. The operation of the feedback circuit here is expressed by the formula: In other words, when the analog input voltage fluctuates between the full-scale value and the zero-scale value with a period of ω = G e12 / cc, N c h MOS T r QN3
The gate electrodes of QN5 and QN5 oscillate, making it impossible to accurately compare the current output from the D/A converter 8 and the current pulled by the TrQNs, and the output contains a zero-scale error despite the zero-scale input. However, it becomes a digital output waveform.

An object of the present invention is to provide an A/D converter that achieves accurate A/D conversion by obtaining a stable current from zero scale to full scale.

[Means to solve the problem]

The A/D converter of the present invention includes: a voltage/current conversion circuit connected to an analog input terminal; a first current source whose current changes in accordance with changes in the current of the voltage/current conversion circuit; a differential input transistor connected to the first current source;
an active load transistor connected to the drain electrode of the differential input transistor; first and second output driving sections connected to the differential input transistor and the active load transistor; a second current source connected to the drain electrode; a D/A converter connected to the drain electrode of the second output driver; a first or second input terminal of the differential input transistor; an analog switch and a comparator connected between the drain electrodes of the second output driver; a reference voltage source connected to one input terminal of the comparator; a pulse generator connected to the analog switch; The output terminal of the D/A converter and a successive approximation register connected to the input terminal and digital output terminal of the D/A converter.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 shows a successive approximation type A/D showing the first embodiment of the present invention.
FIG. 2 is a circuit diagram of a converter.

As shown in FIG. 1, this embodiment also describes an A/D converter having a 6-bit resolution for convenience.

First, the A/D converter of this embodiment has a PchMO8T connected between the first power supply ■o and the second power supply Vss.
r Qp+ and N c h MOS T r QNI
It has a voltage/current converter 2 configured of a resistor R, and a differential amplifier 19 connected to an analog input terminal l. Interlocking with the current converted by the voltage/current converter 2, the amount of current of the first current source 3 consisting of PchTr QP2 and the second current source 6 consisting of Pch MO8Tr changes. This first current source 3 includes P
Ch MOS T r QP3. N c h T r QN6 via differential input Tr4 consisting of QP4
An active load Tr5 consisting of the following is connected. Further, the second current source 6 includes N Ch T r QN2 , QN
The output drive unit 7 consisting of the frequency correction capacitor 16 and the frequency correction Tr 15 are connected to each other, and the differential input Tr 4 is connected to the active load Tr 5. Also, 6bit
A current output type D/A converter 8, an output drive unit 9 consisting of an Nch MO8Tr QN4゜Q, . . . connected to the D/A converter 8, and a differential input T
The analog switch IO and the comparator 11 are connected to one input terminal of r4, the pulse generator 17 is connected to the reference voltage source 12.18 and the analog switch 10, and the output side of the comparator 11 and the digital output terminal 14 are connected. It has a successive approximation register 13.

In such an A/D converter, the voltage applied to the analog input terminal 1 is converted into a current by the voltage/current converter 2, and a current equal to the current is caused to flow through the second current source 6 made of PchMO8Tr. It has become. Also,
The amount of current of the first current source 3 changes in conjunction with the current converted by the voltage/current converter 2.

These first current sources 3. Differential input Tr 4. Active load T
r5. Iff force drive unit 71 Feedback circuit consisting of a frequency correction Tr 15° and a frequency correction capacitor 16 N of the output drive unit 7
The drain potential of the ch MOS T r QN2 is kept at the output voltage Vt (constant) of the reference voltage source 12.

The operation of this feedback circuit will be explained below.

First, when a full-scale voltage is applied to the analog input terminal 1, the voltage/current converter 2 converts
Since it is converted into a current of 64 μA, a current of 64 μA also flows through the second current source 6 made of PchMO8Tr. At this time, a current of 2 μA flows through the first current source consisting of PchMO8Tr QP2, and P c h T r
Qp3. Differential input Tr4 consisting of QP4 and NC
h T r Assuming that the parameter settings of the active load Tr5 consisting of QN6 are the same as in the conventional example, ωz = G
=, 2/ The gain at Cc is the same as the above-mentioned equation (6), and finally a 6-bit full scale code is obtained from the digital pressure terminal 14.

Next, when a voltage corresponding to ILSB is applied to the analog input terminal 1, it is converted into a current of 1 μA by the voltage/current converter 2, so that a current of 1 μA also flows through the second current source 6 made of PchMO8Tr. At this time, P c h
A current of 0.03125 μA flows through the first current source 3 consisting of MOS T r QP2. Now, if we consider the stable state at ω2-G, 2/Co due to the feedback circuit described above, it becomes as follows.Since it can operate in a stable state, it is possible to finally obtain stable digital pressure from zero scale to full scale. .

FIG. 1 is a circuit diagram of an A/D converter showing a second embodiment of the present invention.

As shown in FIG. 3, this embodiment uses Pch TrQP2
a first current source 3 consisting of a Pch Tr QP3゜QPI, and a differential input Tr4 consisting of a Pch Tr QP3゜QPI;
The amplifier circuit configured with the active load Tr20 consisting of rQN6゜QN7 can obtain the same gain as the circuit consisting of the first current source 3, differential input Tr4, and active load Tr5 shown in FIG. If it is set to
Equations (6) and (8) described above can be satisfied, and stable A/D conversion results can be obtained as in the first embodiment.

〔Effect of the invention〕

As explained above, the A/D converter of the present invention includes a voltage/current converter that converts a voltage applied to an analog input terminal into a current, and a first and second converter whose current amount changes depending on the current. By providing a current source, a differential input transistor, an active load transistor, a D/A converter, and a first and second output driver, a stable current can be obtained from zero scale to full scale. By comparing this current with the current from the D/A converter, an accurate A/D conversion result can be obtained.

[Brief explanation of drawings]

FIG. 1 shows a successive approximation type A/D showing the first embodiment of the present invention.
2 is a circuit diagram of a successive approximation type A/D converter showing a second embodiment of the present invention, and FIG. 3 is a circuit diagram of a successive approximation type A/D converter showing a conventional example. It is a circuit diagram. 1... Analog input terminal, 2... Voltage/current converter, 3, 6... Current source, 4...
...Differential input Tr, 5.20...Active load Tr
, 7, 9...output drive section, 8...D/
A converter, 10... Analog switch, 11.
... Comparator, 12.18 ... Reference voltage source, 13 ... Successive approximation register, 14 ...
... Digital output terminal, 15 ... Frequency correction Tr, 16 ... Frequency correction capacitor, 17.
...Pulse generator, 19...Differential amplifier, C1pt~QP5...P channel MO8T
r, Q, +1~QNT...N channel MO8
Tr, R...Resistance. Agent: Susumu Uchihara, Patent Attorney Figure 2, Figure 3

Claims (1)

[Claims] A voltage/current conversion circuit connected to an analog input terminal, a first current source whose current changes in accordance with changes in the current of the voltage/current conversion circuit, and a differential connected to the first current source. a dynamic input transistor; an active load transistor connected to the drain electrode of the differential input transistor; first and second output drivers connected to the differential input transistor and the active load transistor; a second current source connected to the drain electrode of the output driver; a D/A converter connected to the drain electrode of the second output driver; and a first or second of the differential input transistor. an analog switch and a comparator connected between the input terminal of and the drain electrode of the second output driver, a reference voltage source connected to one input terminal of the comparator, and a pulse generator connected to the analog switch. and a successive approximation register connected to the output terminal of the comparator and the input terminal and digital output terminal of the D/A converter.
/D converter.