JPH04164338A - Mounting method for semiconductor integrated circuit - Google Patents

Mounting method for semiconductor integrated circuit

Info

Publication number
JPH04164338A
JPH04164338A JP2291589A JP29158990A JPH04164338A JP H04164338 A JPH04164338 A JP H04164338A JP 2291589 A JP2291589 A JP 2291589A JP 29158990 A JP29158990 A JP 29158990A JP H04164338 A JPH04164338 A JP H04164338A
Authority
JP
Japan
Prior art keywords
chip
electrodes
chip carrier
wiring board
wire
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2291589A
Other languages
Japanese (ja)
Inventor
Hiromi Sakata
坂田　博美
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP2291589A priority Critical patent/JPH04164338A/en
Publication of JPH04164338A publication Critical patent/JPH04164338A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/303—Assembling printed circuits with electric components, e.g. with resistors with surface mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/328—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by welding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H10W72/5522—Materials of bond wires comprising metals or metalloids, e.g. silver comprising gold [Au]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

PURPOSE:To make terminal pitches fine by connecting a chip carrier on which an IC chip is mounted with a wiring board by a wire bonding method. CONSTITUTION:An IC chip 5 is mounted on a chip carrier 3 by using Ag paste 4. Electrodes of an IC chip 5 and electrodes of the chip carrier 3 are wire- bonded by using Au wires 6, and chip coat resin 7 is applied. Whether the chip carrier 3 is acceptable is selected by the electric inspection of the single body. The pitch P1 of outer electrodes of the chip carrier 3 used in this case is 0.2mm. The chip carrier 3 is mounted on a wiring board 1 and temporarily fixed by using adhesive resin 8. Outer electrodes of the chip carrier 3 and electrodes on the wiring board side are wire-bonded by using Au wires 6. Finally, wire coat resin 9 is spread on a bonding part, which is protected. The width W and the pitch P2 of the electrodes on the wiring board side used in this case are 0.2mm and 0.2mm, respectively.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体ＩＣの実装方法に関し、特に半導体ＩＣ
と配線基板を接続する工程を含む半導体ＩＣの実装方法
に関する。[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a method for mounting a semiconductor IC, and in particular to a method for mounting a semiconductor IC.
The present invention relates to a semiconductor IC mounting method including a step of connecting a wiring board and a wiring board.

〔従来の技術〕[Conventional technology]

従来の半導体ＩＣチップの配線基板への実装方法は、第
３図に示すように、配線パターン２を有する絶縁性基板
１の上にＩＣチップ５を直接搭載してＡｕ線（又はＡｐ
線）６を用いてワイヤボンディング法による接続する方
法、もしくは、第４図に示すように、ＩＣチップ５のホ
ンディングパッド部にはんだバンプ１０を形成してリフ
ロー法により接続する方法、または、第５図に示すよう
に、予め半田ペーストを配線基板１側のはんだ付ランド
部にスクリーン印刷法などにより供給してこの上にモー
ルドパッケージングされたモールドＩＣＩＩを搭載して
リフロー法によりはんだ１２にて接続する方法がとられ
ていた。As shown in FIG. 3, the conventional method for mounting a semiconductor IC chip on a wiring board is to directly mount an IC chip 5 on an insulating substrate 1 having a wiring pattern 2, and then attach an Au wire (or Ap
6, or as shown in FIG. 4, a solder bump 10 is formed on the bonding pad portion of the IC chip 5 and the connection is made by a reflow method. As shown in Fig. 5, solder paste is supplied in advance to the soldering lands on the wiring board 1 side by screen printing, etc., and the molded ICII packaged in the mold is mounted on top of this, and solder 12 is applied by the reflow method. There was a way to connect.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来の半導体ＩＣの実装方法のうちＩＣチップ
を直接配線基板に搭載する方法では、ＩＣチップ状態で
完全な電気的検査が難しいので多数個搭載した場合に歩
留の低下を招き、また、動作スピードのランクが要求さ
れる場合には適用出来ないという問題点があった。Among the conventional semiconductor IC mounting methods described above, in the method of directly mounting an IC chip on a wiring board, it is difficult to conduct a complete electrical test while the IC chip is in the state, resulting in a decrease in yield when a large number of IC chips are mounted. There is a problem that this method cannot be applied when a rank of operation speed is required.

一方、モールドパッケージされたＩＣを搭載し、はんだ
リフロー法で接続する方法では、リードピッチがＱ、５
ｍｍ以下になるとリード間のはんだブリッジ、未はんた
。はんた量適不足といった不良が発生し易く、手直し、
修正が多く工数が増大すると共に接続の信頼性が低下す
るという問題点があった。On the other hand, in the method of mounting a mold-packaged IC and connecting it using the solder reflow method, the lead pitch is Q, 5.
If it is less than mm, there will be solder bridges between leads and unsolder. Defects such as insufficient amount of solder are likely to occur, and rework is required.
There were problems in that the number of corrections required increased man-hours and the reliability of the connection decreased.

本発明の目的は、リードピッチがＱ、５ｍｍ以下でも容
易に然も歩留良く適用出来、接続の信頼性が高い半導体
ＩＣの実装方法を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor IC mounting method that can be easily applied with good yield even when the lead pitch is Q and 5 mm or less, and has high connection reliability.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は、半導体ＩＣの実装方法に於いて、ＩＣチップ
をチップキャリアに搭載し前記ＩＣチップの電極と前記
チップキャリアの電極とをワイヤホンディング法により
接続を行ない樹脂コートする工程と、前記チップキャリ
アを配線基板に搭載し前記チップキャリアの電極と前記
配線基板の電極とをワイヤボンディング法により接続す
る工程とを含んでいる。The present invention provides a method for mounting a semiconductor IC, including the steps of mounting an IC chip on a chip carrier, connecting electrodes of the IC chip and electrodes of the chip carrier by a wire bonding method, and coating the chip with a resin. The method includes the steps of mounting the carrier on a wiring board and connecting the electrodes of the chip carrier and the electrodes of the wiring board by wire bonding.

〔実施例〕 次に本発明の実施例について図面を参照して説明する。〔Example〕 Next, embodiments of the present invention will be described with reference to the drawings.

第１図（ａ）、（ｂ）は本発明の第１の実施例を説明す
る断面図及び平面図である。FIGS. 1(a) and 1(b) are a sectional view and a plan view illustrating a first embodiment of the present invention.

第１の実施例は、第１図（ａ）、（ｂ）に示すように、
まず、ＩＣチップ５をチップキャリア３にＡｇペースト
４を用いてマウントし、１５０℃で１時間キュアする。The first embodiment, as shown in FIGS. 1(a) and (b),
First, the IC chip 5 is mounted on the chip carrier 3 using Ag paste 4, and cured at 150° C. for 1 hour.

次に、Ａｕ線６を用いてＩＣチップ５の電極とチップキ
ャリア３の電極とをワイヤボンディングを行ない、チッ
プコート樹脂７を塗布し、例えば１５０℃で２時間キュ
アを行なう。Next, wire bonding is performed between the electrodes of the IC chip 5 and the electrodes of the chip carrier 3 using Au wires 6, a chip coat resin 7 is applied, and curing is performed at, for example, 150° C. for 2 hours.

次に、チップキャリア３単体での電気的検査を行ない良
否の選別を行なう。ここで用いたチップキャリア３の外
部電極のピッチＰ１は０．２ｍｍである。Next, the chip carrier 3 alone is electrically inspected to determine whether it is good or bad. The pitch P1 of the external electrodes of the chip carrier 3 used here is 0.2 mm.

次に、チップキャリア３を配線基板１上に搭載し接着樹
脂８で仮止めしてチップキャリア３の外部電極と配線基
板側電極をＡｕ線６を用いてワイヤボンディングを行う
。Next, the chip carrier 3 is mounted on the wiring board 1 and temporarily fixed with adhesive resin 8, and wire bonding is performed between the external electrode of the chip carrier 3 and the wiring board side electrode using Au wire 6.

最後に、ホンディング部をワイヤコート樹脂９を塗布し
保護する。ここで用いた配線基板側の電極はパターン巾
Ｗか０．２ｍｍ、とッチＰ２か０．２ｍｍである。Finally, wire coat resin 9 is applied to the honding portion to protect it. The electrode on the wiring board side used here has a pattern width W of 0.2 mm and a width P2 of 0.2 mm.

第２図は本発明の第２の実施例を説明する断面図である
。FIG. 2 is a sectional view illustrating a second embodiment of the present invention.

第２の実施例は、第２図に示すように、配線基板１上に
複数のチップキャリア３を搭載した例である。The second embodiment is an example in which a plurality of chip carriers 3 are mounted on a wiring board 1, as shown in FIG.

配線基板１上に複数のチップキャリア３を搭載する場合
には、チップキャリア３間の電極を直接ワイヤバンディ
ング法にて接続する。When a plurality of chip carriers 3 are mounted on the wiring board 1, the electrodes between the chip carriers 3 are directly connected by a wire banding method.

この実施例では、チップキャリア３間を直接接続するの
で実装密度が向上出来る利点がある。In this embodiment, since the chip carriers 3 are directly connected, there is an advantage that the packaging density can be improved.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、ＩＣチップか搭載された
チップキャリアを配線基板にワイヤボンディング法によ
り接続する事により、端子ピッチが０．５ｍｍ以下でも
容易に然も歩留良く製造する事が出来、接続の信頼を高
めることが出来るという効果を有する。As explained above, the present invention enables manufacturing with ease and high yield even when the terminal pitch is 0.5 mm or less by connecting the chip carrier on which the IC chip is mounted to the wiring board by the wire bonding method. This has the effect of increasing the reliability of the connection.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図（ａ）、（ｂ）は本発明の第１の実施例を説明す
る断面図及び平面図、第２図は本発明の第２の実施例を
説明する断面図、第３図は従来のＩＣチップをワイヤボ
ンディング法により接続する実装方法の一例を説明する
断面図、第４図は従来のＩＣチップをリフロー法により
接続する実装方法の一例を説明する断面図、第５図はモ
ールドＩＣをリフロー法により接続する実装方法の一例
を説明する断面図である。 １・・・配線基板、２・・・配線パターン、３・・・チ
ップキャリア、４・・・Ａｇペースト、５・・・ＩＣチ
ップ、６・・・Ａｕ線、７・・・チップコート樹脂、８
・・・接着樹脂、９・パ・ワイヤコート樹脂、１０・・
・はんだバンプ、１１・・・モールドＩＣ１１２・・・
はんだ。1(a) and (b) are a sectional view and a plan view explaining a first embodiment of the present invention, FIG. 2 is a sectional view explaining a second embodiment of the present invention, and FIG. 3 is a sectional view explaining a second embodiment of the present invention. A cross-sectional view illustrating an example of a mounting method for connecting conventional IC chips using a wire bonding method, FIG. 4 is a cross-sectional view illustrating an example of a mounting method for connecting conventional IC chips using a reflow method, and FIG. FIG. 2 is a cross-sectional view illustrating an example of a mounting method for connecting ICs by a reflow method. DESCRIPTION OF SYMBOLS 1... Wiring board, 2... Wiring pattern, 3... Chip carrier, 4... Ag paste, 5... IC chip, 6... Au wire, 7... Chip coat resin, 8
...Adhesive resin, 9.Pa wire coat resin, 10..
・Solder bump, 11...Mold IC112...
Solder.

Claims (1)

【特許請求の範囲】[Claims] 　半導体ＩＣの実装方法に於いて、ＩＣチップをチップ
キャリアに搭載し前記ＩＣチップの電極と前記チップキ
ャリアの電極とをワイヤボンディング法により接続を行
ない樹脂コートする工程と、前記チップキャリアを配線
基板に搭載し前記チップキャリアの電極と前記配線基板
の電極とをワイヤボンディング法により接続する工程と
を含むことを特徴とする半導体ＩＣの実装方法。A semiconductor IC mounting method includes the steps of mounting an IC chip on a chip carrier, connecting electrodes of the IC chip and electrodes of the chip carrier by a wire bonding method and coating with resin, and attaching the chip carrier to a wiring board. A method for mounting a semiconductor IC, comprising the step of mounting the chip carrier and connecting the electrodes of the chip carrier and the electrodes of the wiring board by a wire bonding method.
JP2291589A 1990-10-29 1990-10-29 Mounting method for semiconductor integrated circuit Pending JPH04164338A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2291589A JPH04164338A (en) 1990-10-29 1990-10-29 Mounting method for semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2291589A JPH04164338A (en) 1990-10-29 1990-10-29 Mounting method for semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPH04164338A true JPH04164338A (en) 1992-06-10

Family

ID=17770899

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2291589A Pending JPH04164338A (en) 1990-10-29 1990-10-29 Mounting method for semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPH04164338A (en)

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