JPH04165532A - Method and device for controlling program sequence - Google Patents

Abstract

PURPOSE:To improve the processing speed of a CPU which can execute instantaneously a bug check by collating point discrimination data generated by the CPU in each point and point discrimination data held in a register means and generating selectively an interrupting signal to the CPU. CONSTITUTION:Whenever a bug is detected in a use stage, a hook number (hi) of a point of this side of the bug is written successively in hook number registers RG1 - RGn in its detected sequence. In such a state, at the time of executing a ROM program, when it reaches each point, a CPU 18 outputs its hook number (hi) onto a data bus 12, and simultaneously, writes it in a register 20. Its hook number (hi) is given to comparators CP1 - CPn from the register 20, and in each comparator CPj, its hook number (hi) is compared with a hook number (hj) held in a hook number register RGj. In such a way, the time required for a bug check is minimized and a processing speed of the CPU is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a program sequence control method and apparatus for avoiding bugs in programs stored in a mask ROM or the like.

[Prior Art] After a mask ROM in which a program has been burned is installed in computer equipment and shipped, an unexpected defect (bug) may be found in the program during use. Since it is costly to revise the mask ROM every time such a bug is found, as shown in Figure 4, multiple points are added to the program written to the mask ROM in advance: HO, H1, . . . are set at predetermined intervals, and the bugs b go, b g3. detected during the use stage are set at predetermined intervals.・・・・・・
For, the points in front of it HO, H3,...
The partial program PO for replacement is stored in RAM in
, P3′, and those bugs b g(1, b
g3. I am trying to avoid the execution of...

These partial programs PO', P3' contain bugs b go, b g3 . Each time something was discovered, I debugged it and partially re-created the program, /
R from a storage medium such as a floppy disk when starting the system.
Loaded into AM.

In order to replace the buggy part with a dehugged partial program in the RAM while the program in the mask ROM is being executed, conventionally, the following process has been performed. In other words, every time a bug is found during use, a partial program is created to debug it, and data (hook number) hl that identifies the point before the bug is written in a table like the one shown in Figure 5, along with the corresponding baldness. The addresses m1 (on RAM) of the partial program Pi' to be executed are sequentially listed. Then, as shown in FIG.
+ (for example, instruction C), it executes the call instruction and jumps to a bug-checking buroutine, where the hook number hl of the point H1 is listed in the bug number table (Figure 5). Check out the squid. For this inspection, the hook number hi of point Hi is written to the CPU reno star by instruction B immediately before point Hi. As a result of this check, if the hook number h1 is listed in the bug or table, jump to the corresponding replacement partial program Pi'' in RAM, execute that partial program Pi'', and then execute i: in the ROM program. Returns to the next address (instruction K) of the replaced part P1.If the hook number h1 is not listed in the bug table, execute the bug check subroutine without jumping to the replacement part program. After completion, return 7 to the next ROM address (instruction D) at point H1.

[Problem to be Solved by the Invention] As described above, in the conventional program/kenos control system, bug checks are always performed at all points (HO, Hl, . . . ) set in advance in the ROM program.

jumps to the subroutine, where it sets the hook number h1 of the point in question to the hook numbers hO, h3 . I compared each one one by one to see if there was a match, and then conditionally replaced the partial program in RAM according to the test results.

However, points H1 and H where no bug has occurred
2. However, if such a bug/check/work subroutine is executed, the CPU will spend a lot of time on incidental processing (processing other than the original processing), which will reduce the processing speed or throughput. was causing a decline in especially,
If a loop process is repeated many times and a point is inside the loop, a bug will occur each time the loop runs.
Processing speed decreased significantly due to execution of subroutines.

The present invention was made in view of such problems, and the RO
It is an object of the present invention to provide a program sequence control method and apparatus that improves the processing speed of a CPU by minimizing the time required for bug checking at each preset point in an M program.

[Means for Solving the Problems] In order to achieve the above object, the program sequence control method of the present invention includes a register means for holding data identifying a point located before each bug, and a CPU control method at each point. A means for collating data identifying the generated point with point identification data held in the register means, and selectively executing a partial program for replacement on the CPU based on the collation result of the collation means. The configuration also includes means for generating an interrupt signal to cause an interruption.

In addition, the program sequence control method of the present invention is characterized in that the data identifying the point located before the bug is first stored in advance.
The CPU generates data for identifying the point at each point in a write cycle and writes it to the second register means, and the point identification data written to the second register means is stored in the register means. and the point identification data held in the first register means, and the result of the verification is read into the CPU in successive cycles immediately after the write cycle, and when a matching result is obtained, the CPU is We decided to run a replacement partial program as part of the installation process.

[Operation] If a bug is discovered during use, the identification data (hook number) of the point before the bug is written to the register means and held. This point identification data is also conventionally listed in the bug table.

When the CPU reaches each point in the execution of the system program (ROM program), it outputs identification data for that point. The collation means collates the point identification data from the CPU with the point identification data held in the 7 star means. If the point in question is listed in the bug table, that is, if there is a bug between the point in question and the next point, the point identification data is already registered (held) in the register means. Therefore, a matching result is obtained from the matching means, and in this case, a partial program for replacement is executed in order to use it as a bug table. Furthermore, if the point is not listed in the bug table, that is, if there is no bug between the point and the next point, the point identification data is not registered (held) in the register means. A match/mismatch matching result is obtained, in which case the next command is entered in this program.

Verification according to the present invention is instantaneously executed by comparing the point identification data with each registered point identification data in parallel and simultaneously.

Compared to executing a conventional bug check subroutine in software, it takes much less time.

Therefore, according to the present invention, it is possible to proceed with the execution of the program at points where there are no bugs without making any detours, and at points where there are bugs, it is possible to proceed with the execution of the program in the minimum necessary time.
It is possible to replace it with a partial program of AM.

Further, as an operation of the CPU, the output of point identification data at each point is stored in the first register means in a write cycle, the collation means is made to perform the above collation, and then a read cycle is executed. If the verification result of the verification means is read in the form of an interrupt in that cycle, even a CPU with an instruction queue can switch to conditional interrupt processing.

[Embodiment] An embodiment of the present invention will be described below with reference to FIGS. 1 to 3.

First, as shown in FIG. 2, program sequence controller 18 according to this embodiment has data bus 12 . A read/write control line 141 is connected to a CPU (central processing unit) 10 of the system via a stray signal line 16.

FIG. 1 shows the internal configuration of the control device 10. As shown in FIG. CPU18 (
(not shown) is connected to the input terminals of registers 20, and N hook number registers RG1. . . . is connected to the input terminal of RGN. The output terminal of the register 20 is the comparator circuit CP.
I, . . . are connected to one input terminal of CPN, and the output terminals of the hook number registers RGl, .

are respectively connected to the other input terminals of the CPN, and the comparator c
The output terminals of pt, . . . , CPN are connected to the input terminal of the interrupt request output circuit 22.

Regarding the control lines, the write control line L4b from the CPU 18 is connected to the write control terminal WR of the register 20, and the continuous control line 14a is connected to the output control terminal σ1- of the interrupt request output circuit 22.
connected to. In addition, hook number register RGL
. . , the write control lines AL+, . . . , ALn from the address 0 decoder are connected to the write side @ terminal WR of RGN.

In the program stored in the ROM (not shown) of this system, a plurality of points are set in advance at predetermined intervals, as in the past. Each time a bug is found during use, a partial program is created to debug it, and data (hook number) hI that identifies the point before the bug is stored in a bug table as shown in Figure 5.
and (RAM
(above) addresses mi are sequentially listed (. However, unlike before, there is no bug check subroutine. Instead, the hook number hi of the point before the bug is
are sequentially written into the hook number registers RGI, . . . RGN in the order in which the bugs were discovered. In this write, the CPU 18 writes the target hook number register R via the address decoder and control line ALi.
Gj is selectively enabled for writing, and the hook number hj is loaded into the register RGj via the data bus 12.

In this way, the same point identification data as the hook numbers listed in the bug table (FIG. 5) are held in the hook number registers RGI, . . . RGN.

As shown in FIG. 3, when the CPU 18 reaches each point (instruction C) in executing the ROM program, the CPU 18 transfers the hook number hi to the data bus 1.
By outputting the hook number h[ to the register 2o and at the same time making the write control signal WR active, the hook number h[ is written to the register 2o. Then, that), kunamba hi
is given to the comparators CPI, . . . CPN from the register 20, and in each comparator CPj, its hook number h
1 is compared with the hook number hj held in the hook number register RGj. Therefore, if the hook number h1 of the point is listed in the bug table (i.e., if there is a bug b after the point)
g), the comparison − dispersion (hi
=hj) is obtained), and the comparator outputs an "H" level comparison match signal, and this signal is sent to the interrupt request output circuit 22.
is input. However, this hook number hj or bug
If it is not listed in the table (that is, if there is no bug bg after the point), no comparison match will be obtained in any of the comparators, and therefore an “H” level signal will be sent to the interrupt request output circuit 22. Not entered.

On the other hand, the CPU 18 makes the read signal RD active ("L") with the instruction c' following the instruction C, thereby making the interrupt request output circuit 22 ready for output. As described above, if any of the comparators outputs a comparison match signal at the "H" level, the interrupt request output circuit 22 outputs the interrupt signal INT (or NMI) at the H level. Ru.

When the CPU 18 receives this interrupt signal INT (NMI), it jumps to the address ml of the replacement partial program P1' stored in the RAM and executes the partial program P1'. As a result, execution of bug bgl is avoided. When such a bug bgi does not exist, the interrupt request output circuit 22 outputs the interrupt signal INT (NMI).
Since the CPU 18 does not output any interrupt processing (execution processing of the replacement partial program Pi), the CPU 18 proceeds to execute the instruction at the next ROM address following the instruction C".

In this way, in this embodiment, the bug check at each point H1 of the ROM program is performed by the CPU 18 at that time.
This is done by simultaneously comparing the hook numbers generated by the bug table with all the hook numbers listed in the bug table and held in registers in hardware. As a result, points with no bugs can be replaced with partial programs in RAM without wasting time, and points with bugs can be replaced with the minimum necessary time.

Note that in this embodiment, the CPU 18
After outputting the hook number hi with the instruction (C), an interrupt signal is selectively received from the control circuit by executing a read cycle with the next instruction C''. This is because we considered the case where the CPU has an instruction queue.
Since the PU fetches the next instruction without waiting for an interrupt during the write cycle of instruction C, a problem arises in that even if an interrupt occurs, the CPU cannot start the interrupt processing. However, when a read cycle is inserted, there is a pause for data acquisition within this cycle, so even if an interrupt occurs, it is possible to respond to it.

Further, the number of hook number registers RG can be arbitrarily selected. Operation mode (character input.

By replacing the hook numbers each time (printing, etc.), it is possible to handle even a small number of prints.

[Effects of the Invention] The present invention achieves the following effects by performing the above-described configuration or steps.

According to the program sequence system tII device of claim 1, data for identifying a point located before a bug is held in the register means, and point identification data generated by the CPU at each point is held in the register means. By comparing the point identification data with the existing point identification data and selectively generating an interrupt signal to the CPU according to the comparison result, bug checking is performed instantly using hardware, so points without bugs are wasted. You can proceed with the execution of this program without spending a lot of time, and at the point where there is a bug, the RAM is saved in the minimum amount of time necessary.
It can be replaced with a partial program. Therefore, the processing speed of CPtJ is improved, and a great effect can be obtained especially when there is a point in loop processing.

According to the program sequence control method of claim 2, causing the CPU to generate point identification data in a write cycle;
Next, we made the CPU read the results of the above verification in the read cycle, so even if an interrupt occurs depending on the verification results, CPtJ can respond to this and switch to the replacement partial program. As a result, even a CPU with an instruction queue can obtain the effects of the present invention as described above.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a configuration example of a program sequence control device according to an embodiment of the present invention, FIG. 2 is a block diagram showing a connection configuration between the control device of the embodiment and a CPU, and FIG. A program diagram for explaining the operation of the embodiment, FIG. 4 is a program diagram showing a normal method for avoiding bugs in ROM programs, and FIG. 5 is a bug table for replacing a partial program in RAM. and FIG. 6 are program diagrams for explaining the operation of the conventional system. In the drawing, 10...CPU. 18...Program sequence control device, 20...
...Register, RGI, ~RGn...Hook number register, C
Pl, ~CPn... Comparator, 22... Interrupt request output circuit. Figure 2 Figure 3 ROM program diagram Figure 4

Claims (2)

[Claims] (1) Multiple points are set in advance at predetermined intervals in a program stored in a storage device, and when the CPU reaches each point, a bug exists between that point and the next point. In a computer system that checks whether there is a bug, and if such a bug exists, executes a replacement partial program temporarily stored in another storage device to avoid execution of the bug, register means for holding data for identifying a point located in front of each bug; and means for collating data for identifying the point generated by the CPU at each point with point identification data held in the register means; , means for generating an interrupt signal for selectively causing a CPU to execute the replacement partial program according to the verification result of the verification means. (2) Multiple points are set in advance at predetermined intervals in a program stored in a storage device, and when the CPU reaches each point, it is determined that a bug exists between that point and the next point. In a computer system that checks whether there is a bug, and if such a bug exists, executes a replacement partial program temporarily stored in another storage device to avoid execution of the bug, Data for identifying a point located in front of the bug is held in advance in the first register means, and at each point, data for identifying that point is generated by the CPU in a write cycle and is stored in the second register means. writing, comparing the point identification data written in the second register means with the point identification data held in the first register means, and reading the result of the comparison in a read cycle immediately after the write cycle. A program sequence control method characterized in that the partial program for replacement is read into a CPU, and when a matching result is obtained, the CPU is caused to execute the replacement partial program as an interrupt process.