JPH0416945B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit device, and particularly to a semiconductor integrated circuit device in which power supply lines are connected so that input level margins are not reduced.

Conventionally, a semiconductor integrated circuit using a package with about 40 pins has one V _CC power supply pin and one GND (ground) pin, and the power supply wiring on the semiconductor substrate is as shown in FIG. 1, for example.

In FIG. 1a, 1 is a V _CC that externally drives an internal circuit 5, an input circuit 6, and an output circuit 7, which will be described later.
V _CC power pad for inputting power supply voltage, 2 is
GND (ground) power pad, 3 is V _CC power pad 1
4 connects the _GND power supply pad 2 and the internal circuit 5, input circuit 6, and output circuit 7.
A GND (ground) power supply line, 5 is an internal circuit that is composed of desired circuit elements and performs circuit operation, 6 is an input circuit that serves as an interface for inputting external input signals and outputting it to the internal circuit 5. Internal circuit 5
This is an output circuit that serves as an interface for inputting the output signal of the device and outputting it to the outside.

FIG. 1b is a diagram illustrating connections among the input circuit 6, internal circuit 5, and output circuit 7. FIG. That is, an input signal 25 from the outside enters the input circuit 6, and the input signal 25 enters the input circuit 6.
is the signal 26 to the inverter 51 of the internal circuit 5, for example.
Output. Logic is realized by an inverter 51, a 2-input NAND 52, etc. of the internal circuit 5, and a signal 27 is inputted from, for example, the 2-input NAND 52 of the internal circuit 5 to the output circuit 7, and the output circuit 7 outputs a signal 28 to the outside.

Recently, as semiconductor integrated circuits have become larger in scale, the number of pins has also increased, and packages with about 72 pins have come into use. Figure 2 shows the power supply wiring on the semiconductor substrate in this case. In FIG. 2, the same reference numerals as in FIG. 1 indicate the same or equivalent parts. Two V _CC pads 11 and 12 and the V _CC connected to them
Power line 3 and two GND (ground) pads 21,
22 and a GND (ground) power line 4 connected to them.

FIG. 3 shows how the semiconductor substrate is mounted on a package.

A semiconductor substrate 31 is housed in a package 30,
The GND pads 21 and 22 are electrically connected to two GND pins 33 via bonding wires 32.

In the conventional power supply wiring method and package mounting method, the GND of the internal circuit 5, input circuit 6, and output circuit 7 included in the semiconductor integrated circuit device is
When the power supply line 4 is shared and a large number of output circuits 7 are switched from "1" to "0",
There is a drawback that the input circuit 6 is directly affected by changes in the GND level, resulting in a reduction in the input high level margin.

This will be explained using FIG. 4.

Inside the semiconductor integrated circuit, there are a large number of input circuits 6,
A large number of internal circuits, such as an inverter 51, a two-input NAND 52, and a large number of output circuits 7 are provided, and these are connected to a common GND (ground) power supply line 4. Then, the GND power line 4 is connected to the system GND 4 through the wiring resistance 45 and wiring inductance 46 included in the package, socket, etc.
Connected to 7. In this state, a large number of output circuits 7
is switched from "1" to "0" at the same time, the charge stored in the load capacitor 48 turns on.The NMOS transistor 49, the wiring resistance 45,
System GND via wiring inductance 46
47 discharged. Therefore, A of GND power line 4
The potential V _F at a point is as shown in equation (1). However, R is the wiring V _F =Ri+Ldi/dt (1) resistance 45, L is the wiring inductance 46, and i is the current flowing into the system GND 47. for example,
The value of V _F is L = 50nH, and a current change of 300mA is
If it occurs in 25nsec, it will reach 0.6V just by Ldi/dt. The input high level V _IH of the input circuit 6 is directly affected by this. That is, the logic threshold voltage _VLT of the input circuit 6 is expressed as in equation (2).

However, V _CC is the power supply voltage, which is common to the input circuit, internal circuit, and output circuit, and is 5 V. V _TN is the threshold voltage of the NMOS transistor, and V _TP is the PMOS transistor.
The threshold voltage of the transistor, √ is a constant determined by the mobility of electrons and holes, the channel width and channel length of the transistor, and is proportional to the square root of the ratio between the channel width W _P of a PMOS transistor and the channel width W _N of an NMOS transistor √ _{P N} and 0.3
It is a value of degree. Therefore, when V _F becomes 0.6V,
The change in V _LT ΔV _LT is 0.46V.

Here, normally TTL compatible input circuit 6
The maximum value of the input low level, V _ILnax , is 0.8V, and the minimum value of the input high level, V _IHnio , is 2.0V, so the input circuit's V _LT is designed to be 1.4V, which is in the middle of them, but the output When switching circuit 7, _VLT of input circuit 6 is 1.86V according to the previous calculation. Therefore, the power supply voltage V _CC and threshold voltage V _TN ,
When V _TP changes, the minimum input high level V _IHnio
margin is almost gone.

Next, when the input circuit power supply voltage is 3V, the internal circuit,
The case where the power supply voltage of the output circuit is lower than 5V will be explained. In this case, the logic threshold voltage V _LT of the input circuit is expressed as in equation (2). however,
V _CC = 3V and V _LT is 1.4V in the middle of the TTL level.
√ is large, approximately 0.8, due to the setting. Here, if V _F noise occurs at 0.6V as before, V _LT
is 1.73V, which is higher than when the input circuit power supply voltage is 5V, which is equal to the internal circuit and output circuit power supply voltages.
There is a V _IHnio margin. However, if the power supply voltage is lowered, the speed of the input circuit will decrease, it cannot be used as a CMOS interface, and it will become more susceptible to noise on the V _CC side, which will be described later. Therefore, it is recommended to set the power supply voltage of the input circuit to 5V like other circuits. Common.

Therefore, the power supply voltage of the input circuit is
It can be seen that in the case of 5V, the margin of V _IHnio of the input circuit becomes very strict.

In the explanation so far, many output circuits are "1"
Although the case of switching from "0" to "0" has been described, a similar problem occurs when a large number of outputs switch from "0" to "1".
That is, it is electrically connected from a system V _CC power supply (not shown) to the V _CC section of the semiconductor integrated circuit via wiring resistance and wiring inductance.

Therefore, a voltage expressed by equation (3) is applied to the V _CC portion of the semiconductor integrated circuit when the output is switched from "0" to "1".

V _CC −(Ri+Ldi/dt) ……(3) where R is wiring resistance, L is wiring inductance,
i is the current flowing out from the system V _CC power supply.
Logic threshold voltage of input circuit 6 at this time
V _LT is expressed as in equation (4).

However, the symbols are the same as in equation (2). Therefore, in this case, the maximum value _VILnax margin of the input low level is reduced.

However, if we compare equations (1) and (3), we can see that
The level fluctuation is larger when switching from "1" to "0".

An object of the present invention is to eliminate the above-mentioned drawbacks, and to eliminate fluctuations in the GND level and V _CC level even if the output circuits switch simultaneously in a device where the power supply voltages of the input circuit, internal circuit, and output circuit are equal. An object of the present invention is to provide a semiconductor integrated circuit whose input level margin does not decrease.

The semiconductor integrated circuit device of the present invention that achieves the above object is characterized in that when the power supply voltages of the input circuit, internal circuit, and output circuit are equal, the power supply line of the input circuit and the power supply line of the output circuit are electrically connected. The purpose is to insulate the

In a preferred embodiment of the invention, the GND power line of the input circuit is connected to a first GND power pad, and the GND power line of the output circuit is connected to a second GND power pad. Connected to power pad.

Further, in a preferred embodiment of the present invention, the GND (ground) power line of the internal circuit is connected to the GND (ground) power line of the input circuit.

Hereinafter, the present invention will be specifically explained based on Examples, but the present invention is not limited to these Examples, and various modifications can be made within the scope of the idea of the present invention.

In FIG. 5, the same symbols as in FIG. 4 indicate the same or equivalent items.

of a large number of input circuits 6 in a semiconductor integrated circuit.
The GND section and the GND sections of many internal circuits, such as the inverter 51 and the 2-input NAND circuit 52, are connected to a common first GND (ground) power supply line 41, and the system GND 47 is connected to the system GND 47 through a wiring resistance 451 and a wiring inductance 461. grounded.

On the other hand, the GND part of the output circuit 7 is the second
It is connected to the GND (ground) power supply line 42 of , and is grounded to the system GND 47 via a wiring resistance 452 and a wiring inductance 462.

According to this embodiment, since the first GND power line 41 and the second GND power line 42 are voltage-insulated, a large number of output circuits 7 can change from "1" to "0".
Switching to the level and connecting the second GND power line 4
Even if the potential of the first GND power supply line 41 rises, the potential of the first GND power supply line 41 does not rise. Therefore, the input circuit 6
V _LT is the value obtained by setting V _F in equation (2) above to zero, and even if many output circuits 7 are switched at the same time, approximately
1.4V, which is the minimum value of sufficient input high level
V _IHnio margin (approximately 0.6V) can be taken.

Fig. 6 shows the entire power supply wiring on the semiconductor substrate to achieve the arrangement shown in Fig. 5;
The same symbols as those in the figures and FIG. 3 indicate the same or equivalent parts.

In FIG. 6, 5 is an internal circuit that is composed of desired circuit elements and performs circuit operations, 6 is an input circuit that serves as an interface for inputting external input signals and outputting it to the internal circuit 5, and 7 is an internal circuit that performs circuit operations. Output circuits 11 and 12 act as an interface for inputting the output signal of the internal circuit 5 and outputting it to the outside, and drive the internal circuit 5, input circuit 6, and output circuit 7 from the outside.
V _CC power supply pad common to all circuits for inputting the V _CC power supply voltage, 201 is the first GND for connecting the first GND power supply line 41 to the external system GND
(Ground) power pad 202 is a second GND (ground) power pad for connecting the second GND power line 42 to external system GND.

As shown in FIG. 6, by providing a first GND power pad 201 for the input circuit 6 and internal circuit 5 and a second GND power pad 202 for the output circuit 7, the input circuit 6 and The GND power supply line 41 for the internal circuit 5 and the GND power supply 42 for the output circuit 7 are electrically insulated.

FIG. 7 shows a method of mounting a semiconductor substrate with power supply wiring as shown in FIG. 6 onto a package.

A semiconductor substrate 310 is housed in a package 70, and a first GND for input circuit 6 and internal circuit 5 is provided.
The power supply pad 201 is connected to the GND pin 71 for the input circuit 6 and internal circuit 5 via the bonding wire 73.
The GND power supply pad 202 for the output circuit 7 is electrically connected to the GND pin 72 for the output circuit 7 via a bonding wire 74.

The equivalent circuit shown in FIG. 5 can be realized by the power supply wiring shown in FIG. 6 and the mounting method of the semiconductor substrate on the package shown in FIG. 7.

According to this embodiment, since there is an input high level margin, it is possible to obtain a semiconductor integrated circuit device that can withstand simultaneous switching of a large number of data buses.

Although the present embodiment describes a CMOS circuit, it goes without saying that the present invention is also effective for semiconductor integrated circuit devices using other processes such as bipolar, NMOS, and PMOS.

In addition, in this embodiment, the GND part of the internal circuit 5 and the GND part of the input circuit 6 are connected to a common first GND power supply line 4.
1, the same effect can be obtained by connecting the GND section of the internal circuit 5 to the GND power supply line 42 for the output circuit 7, and the present invention can also be applied to such a case.

Furthermore, although this embodiment has been described using the GND power line as an example, the invention can also be applied to the V _CC power line.

According to the present invention, since the simultaneous switching of the output circuits does not affect the input circuits, it is possible to obtain a semiconductor integrated circuit device in which the GND level and the V _CC level do not fluctuate and the input level margin does not decrease.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the power wiring of a semiconductor integrated circuit device which is one conventional example, and FIG. 2 is a diagram showing the power wiring of a semiconductor integrated circuit device which is another conventional example.
Fig. 3 is a diagram of mounting the semiconductor substrate shown in Fig. 2 onto a package, Fig. 4 is an equivalent circuit diagram of power supply wiring of a conventional semiconductor integrated circuit device, and Fig. 5 is an embodiment of the present invention. FIG. 6 is an equivalent circuit diagram of power supply wiring of a semiconductor integrated circuit device as an example, FIG. 6 is a diagram showing power supply wiring of a semiconductor integrated circuit device according to an embodiment of the present invention, and FIG. FIG. 3 is a diagram of mounting the semiconductor substrate of the example onto a package. 5, 51, 52... Internal circuit, 6... Input circuit, 7... Output circuit, 41... First GND power line, 42... Second GND power line, 201... First GND power supply Pad, 202...Second GND power pad.

Claims (1)

[Scope of Claims] 1. An internal circuit having at least a large number of circuits that perform logical operations is arranged on the same semiconductor substrate, and an input signal from the outside is input and converted to the signal level of the internal circuit. A large number of input circuits serve as interfaces for outputting to the internal circuits, and a large number of output circuits serve as interfaces for inputting the output signals of the internal circuits, converting them to external signal levels, and outputting the signals to the external circuits. placed around the
In a semiconductor integrated circuit device in which the input circuit, the output circuit, and the internal circuit are driven by the same power supply voltage V _CC , a first ground power supply line to which the plurality of input circuits are commonly connected; A semiconductor integrated circuit device comprising: a second ground power line that is electrically insulated from the first ground power line and to which the plurality of output circuits are commonly connected. 2. Claim 1 states that the power line of the input circuit to be insulated is connected to the first power pad, and the power line of the output circuit to be insulated is connected to the second power pad. Features of semiconductor integrated circuit devices. 3 In claim 1 or 2, it is provided that the power lines of the multiple input circuits and the power lines of the multiple output circuits are insulated within the package and also at the power pins. Features of semiconductor integrated circuit devices. 4. The semiconductor integrated circuit device according to claim 1 or 2, wherein power lines of the plurality of internal circuits are connected to power lines of the plurality of input circuits.