JPH04169873A - Device testing apparatus and method - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Summary] This invention relates to device testing equipment and testing methods for performing various tests on devices under test such as integrated circuits and determining their acceptability. When adding hardware such as relays to perform
Our goal is to provide device testing equipment and testing methods that are not limited by the number of relay control lines from a C tester, etc., and perform various tests on devices under test to determine the quality of the devices under test. a test control section for determining the test control section, an external circuit system that operates the device under test in combination with a test signal supplied from the test control section, and the test signal and the device under test of the external circuit system. a switching unit for forming a test measurement system for the device under test by switching the connection state to the device under test; and a switching control section that controls the switching operation and selects the test signal and external circuit system indicated by the specified code, or when performing various tests on the device under test. A specific code is specified according to the mode, the switching unit is operated by a control signal generated based on the specified code, the test measurement system of the device under test is set, and the set test is performed. The device under test is operated by a measurement system to determine its acceptability, or the switching control section is configured to decipher a designation code from the test control section and generate a decoded signal indicating the type of the test and measurement system. An output decoder and an OR circuit that generates a control signal for performing the switching operation based on the decode signal from the decoder using an OR element, or the decoder and the OR circuit,
PL consisting of multiple types of logic elements that can be combined arbitrarily
Consists of D.

[Industrial application field]

The present invention relates to a device testing apparatus and a testing method for performing various tests on a device under test such as an integrated circuit to determine its acceptability.

In recent years, high-performance integrated circuits (for example, PLL circuits) that are used together with various external circuits such as LC resonant circuits have been actively developed. Furthermore, in order to quickly commercialize this type of integrated circuit ahead of other companies, it is necessary to develop it efficiently in a short period of time without requiring any human resources. For this reason,
There is also a need to complete development in a short period of time regarding various tests during the shipping stage of the integrated circuits. In addition to measuring the characteristics of a single integrated circuit, these tests include
It also includes characteristic measurements performed in combination with external circuits to confirm the special functions each integrated circuit has.

The present invention refers to one measure for efficiently developing the various tests mentioned above.

[Conventional technology]

FIG. 5 is a circuit diagram showing an example of a conventional device testing apparatus. However, here, the device under test 7 (OUT (Device Under
We will explain the case where three types of tests are performed on (also called Te5t) as a representative example.

In FIG. 5, a test control section 1 is provided for performing various tests on the device under test 7 to determine whether or not the device under test 7 is a good product. This test control section 1 is usually composed of an IC tester having a CPU. The device under test 7 is sent from the CPU to the device under test 7 according to a test program created in advance by the software in this IC tester.
test signal St (or special function test signal St')
), it is possible to automatically test the device under test 7. Note that the power supply voltage Vd applied to the device under test 7 is also supplied from the IC tester. moreover,
External circuit systems such as a resonant circuit 8 and a capacitor 9 are connected to the device under test 7. These external circuit systems are necessary to operate the device under test 7 in combination with the test signal St. Further, on the measurement board, a switching section consisting of three relays rl, r2, and r3 is arranged together with the device under test 7. A device testing apparatus is constituted by the test control section 1, the external circuit system, and the switching section.

When performing various tests using this conventional device test equipment, control signals Srl'S+1 and Srl'S+1 for relay switching are sent from the test program in the test control section 1 to the relay control line.
By supplying r3, the test signal S and the connection state of the external circuit system to the device under test 7 are switched. In this way, the relay rl can be adjusted according to the purpose of each test.

By selecting the on/off states of r2 and r3, a desired test and measurement system can be configured. For example, Figures 6 to 8
In the figure, three relays rl.

Three types of test and measurement systems are configured by combinations of on/off states of r2 and r3. In this case, when each I/NO is off, its contact is on the test signal St side, and when it is on, its contact is on the special function test signal St' side (rl contact) or the external circuit system. side (contact point of r2 and r3).

More specifically, in the first test and measurement system shown in FIG. 6, relays rl, r2, and r3 are all in the off state, and the digital test signal St is supplied to the device under test 7. A continuity check, etc. is performed. In addition, in the second test measurement system shown in FIG. Measurement of the center oscillation frequency of 17 (display) is performed. Furthermore, in the third test measurement system shown in FIG. 8, relays r1, r2, and r3 are all turned on, and the analog special function test signal St', the resonant circuit 8, and the capacitor 9 are connected to the device under test. 7, and the PLL circuit 27 (PD
(indicates a phase detector, and AMP indicates an amplifier) is checked for operation.

[Problem to be solved by the invention]

As mentioned above, when testing the device under test 7 such as an integrated circuit using conventional device test equipment, depending on the purpose of each test, the test program (software) of the IC tester etc. can be used to turn on relays, etc. The desired test and measurement system was configured by controlling the on/off switching operation.

Therefore, when improving the test method for the device under test 7 or adding a new test method, the test measurement system may be changed or a new one may be required, and hardware such as relays may be added.・There will be cases where changes need to be made. At this time, the test program for relay control must also be changed, and changes to the hardware will also affect the software. This is t1
As the functions of the device under test 7 become more complex, the burden on the software increases, causing a problem in that errors in test program creation are more likely to occur. Furthermore, in this case, the number of relays etc. that can operate independently is limited by the number of relay control lines from the IC tester, that is, the number of output terminals (for example, 30). A problem also arises in that not all tests on the device 7 can be performed satisfactorily.

The present invention has been made in view of the above-mentioned problems, and when adding hardware such as a relay to perform a new test on a device under test such as an integrated circuit, the burden on the software side may be increased. It is an object of the present invention to provide a device testing apparatus and a testing method in which the number of independently operating relays is not limited by the number of relay control lines from an IC tester or the like.

[Means to solve the problem]

FIG. 1 is a flowchart showing the principle configuration of the present invention. Note that components similar to those described above are denoted by the same reference numerals.

As shown in FIG. 1, the device testing apparatus of the present invention includes a test control section l for performing various tests on a device under test 7 to determine the quality of the device under test 7, and a test control section an external circuit system 2 that operates the device under test 7 in combination with the test signal St supplied from the external circuit system 1; and a switch that switches the test signal St and the connection state of the external circuit system 2 to the device under test 7 3, controls the switching operation of the switching section 3 based on the test specification code output from the test control section 1 when performing the test, and generates a test signal S indicated by the specification code. , and a switching control section 4 that selects the external circuit system 2.

Alternatively, in the device testing method of the present invention using the device testing apparatus including the test control section 1, external circuit system 2, and switching section 3 shown in FIG. A specific code is specified according to the test mode, and the switching unit 3 is operated by a control signal generated based on the specified code to set the test measurement system of the device under test 7. The device under test 7 is operated using the set test and measurement system to determine its quality.

More preferably, the switching control unit 4 in the device testing apparatus of the present invention includes a decoder that decodes the code from the test control unit 1 and outputs a decode signal indicating the type of the test measurement system, and It is provided with an OR circuit 6 that generates a control signal for performing the switching operation using an OR element based on the signal.

More preferably, the decoder section and the OR circuit are composed of a plurality of types of logic elements that can be combined in any desired manner.
L D (Programmable Logic D)
evice).

[For production]

In the device testing apparatus of the present invention, if a test measurement system designation code is input from the test control section 1 of an IC tester etc. to the external switching control section 4, the switching control section 4 will switch the relay in the switching section 3. Control signals for on/off switching operations such as the following are output. That is, by simply sending out a binary designation code from the test control unit 1 without supplying a control signal to the relay control line, the relays in the switching unit 3 operate to control the test and measurement system according to the designation code. is set.

Therefore, even when adding hardware such as a relay to test the device under test 7 in a different mode, this can be handled by adding a logic element (logic gate) to the OR circuit of the switching control section 4. Therefore, the software in the test control section 1 is not affected. Furthermore, if the switching control section 4 is constructed from a PLD, operation patterns for relays and the like can be easily written by combining a plurality of logic gates. Note that, instead of the switching control section 4 described above, it is also possible to provide a peripheral device or the like external to the test control section 1 with the role of relay switching control.

Furthermore, since the designation code output from the test control unit 1 is displayed in binary numbers, the number of such codes is much smaller than the number of relay control lines, so unlike the conventional method (Fig. 5), There is no possibility that the number of operating relays will be limited by the number of output terminals of the test control section 1 such as an IC tester.

Thus, in the present invention, when adding hardware such as a relay to perform a new test on a device under test such as an integrated circuit, the burden on the software side can be reduced compared to conventional methods, and the software can operate independently. It is possible to prevent the number of relays etc. from being limited by the number of relay control lines from an IC tester etc.

〔Example〕

FIG. 2 is a block diagram showing one embodiment of the present invention. Here, the test control section 1 is configured by an IC tester 10 having a CPU II. Further, as the switching unit 3, a relay group 30 in which a large number of relays are arranged is mounted on the measurement board.

Further, the switching control unit 4 includes a decoder 5 that decodes the specified code from the IC tester 10 and outputs a decoded signal indicating the type of test and measurement system, and controls the relay group 30 based on the decoded signal from the decoder 5. at least 1 signal
and an OR circuit 6 generated by more than one OR element. When testing the device under test 7, if the designation code of the test measurement system for performing this test is 2.
If the base number is input from the IC tester 10 to the decoder 5, the number of the test and measurement system is output as a decoded signal. Therefore, if the IC tester 10 has N terminals for outputting specified codes, 2N decoded signals are output, so it is possible to set up 29 test and measurement systems, and the control from the IC tester 10 is possible. The number of signals (designation codes) is much smaller than in the past. Furthermore, in the OR circuit 6, the OR element generates a control signal for ON/OFF switching operation of the relay according to each test mode of the device under test 7, and supplies these control signals to each relay. The test signal S and the external circuit system 2 are selected to set the target test and measurement system. In this case, the decoder 5 is a circuit that does not depend on the device under test 7, but the OR circuit 6 needs to be prepared for each device under test 7. However, since the above-mentioned OR circuit 6 can be easily configured with a simple OR element, when a relay with a new operation pattern is added, one
By simply adding two logical OR elements, rapid response can be achieved without changing the software within the IC tester 10.

FIG. 3 is a circuit diagram showing a specific example of FIG. 2.

Here, circuit configurations for performing three types of tests on the device under test 7 will be illustrated. It is assumed that the test and measurement system for conducting the above three types of tests is the same as that shown in FIGS. 6 to 8 described above.

In Figure 3, the 3-digit designation code D. -D2 is input to the decoder 5, so from this decoder 5 there are 8 ways (
23=8) decoded signals are output. The levels of these decoder signals 80 to S7 are "H" ()Iigh) or "L" (Low), and the "H" decoder signal corresponds to the number of the test measurement system. That is,
When S2 is "H", one relay r2 in the relay group is turned on by the logical sum circuit 6 to configure a second test measurement system, and when S3 is "H", the above logical sum It is shown that all relays rl, r2, and r3 are turned on by circuit 6 to constitute a third test and measurement system. In addition, when configuring the first test measurement system,
Since any relay in the relay group can remain in the off state, the decoded signal is not connected to the OR circuit 6. To explain in more detail, since relay r2 is turned on when configuring the second and third test and measurement systems, decoded signal S2. An OR element having S3 as an input is connected to the relay r2. On the other hand, relay r1. Since both r3 are turned on when configuring the third test and measurement system, only one decoder signal S3 is input, and the OR element can be omitted.

In the above specific example, the OR circuit 6 is configured with only one OR element, but it is possible to easily add a plurality of OR elements depending on the type of test of the device under test 7. In other words, it is possible to deal with this by simply changing the hardware such as OR elements and relays without changing the test program using software, so it is possible to completely separate the software side from the hardware side and eliminate errors in program creation. It becomes possible to prevent this.

FIG. 4 is a block diagram showing another embodiment of the present invention.

Here, the decoder 5 and OR circuit 6 in FIG.
This is realized by LD14. This PLD 14 is constructed by randomly arranging a plurality of types of logic elements such as OR elements and AND elements, and can generate any control signal by selecting these logic elements. In this case, when performing a new test, it is possible to configure a desired test and measurement system by simply changing the combination of logic elements in advance using signals from the outside. Therefore,
There is no need to newly add an OR element as in the embodiment (FIG. 2), and the number of parts and connection lines can be reduced.

〔Effect of the invention〕

As explained above, according to the present invention, when conducting new tests on devices under test such as integrated circuits, it is possible to perform new tests by simply adding hardware such as relays and logic elements without affecting the software. Because you can
The independence of the software and hardware sides is increased, allowing efficient development of device test equipment and test methods on both sides. Furthermore, the number of independently operating relays, etc. is not limited by the number of relay control lines from an IC tester, etc., so all tests on devices under test, which will become increasingly complex in the future, can be performed without exception. It becomes possible to appropriately judge the quality.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the principle configuration of the present invention, Fig. 2 is a block diagram showing an embodiment of the invention, Fig. 3 is a circuit diagram showing a specific example of Fig. 2, and Fig. 4 is a block diagram showing the present invention. FIG. 5 is a circuit diagram showing an example of a conventional device test apparatus; FIG. 6 is a diagram showing a configuration of the first test and measurement system in FIG. 5; This figure shows a state in which the second test and measurement system is configured in FIG. 5, and FIG. 8 is a diagram showing a state in which the third test and measurement system in FIG. 5 is configured. In the figure, 1... test control section, 2... external circuit system, 3...
...Switching section, 4...Switching control section, 5...
Decoder, 6...OR circuit, 7...Device under test, 14...PLD0 A circuit diagram showing a specific example of Fig. 2. National policy showing the state in which the first test and measurement system is configured in Fig. 5. Figure 6 is a diagram showing the configuration of the second test and measurement system in Figure 5.

Claims (1)

[Claims] 1. A test control section (1) for performing various tests on the device under test (7) to determine the quality of the device under test (7); ) is supplied from the test signal (S_t
), and an external circuit system (2) that operates the device under test (7) in combination with the test signal (S_t) and the connection state of the external circuit system (2) to the device under test (7). In a device testing apparatus having a switching unit (3) for switching to configure a test and measurement system for the device under test (7), the test output from the test control unit (1) when performing the test is provided. The switching operation of the switching unit (3) is controlled based on the specified code of the test signal (S) indicated by the specified code.
_t) and a switching control unit (2) that selects the external circuit system (2);
4) A device testing apparatus comprising: 2. The test control section (1) according to claim 1, the external circuit system (2)
) and a switching unit (3), the device under test (7)
When conducting various tests on the subject, a specific code is specified according to the mode of the test, and the switching section (3) is operated by a control signal generated based on the specified code. Measuring device (7
), and the set test and measurement system measures the device under test (7).
) is operated to determine its acceptability. 3. A decoder (5) in which the switching control unit (4) decodes the designation code from the test control unit (1) and outputs a decoded signal indicating the type of the test and measurement system; and the decoder (5) 2. The device testing apparatus according to claim 1, further comprising an OR circuit (6) that generates a control signal for performing the switching operation using an OR element based on a decode signal from the device. 4. A PLD consisting of a plurality of types of logic elements in which the decoder (5) and the OR circuit (6) can be combined in any desired manner.
The device testing apparatus according to claim 3, which is realized by (14).